Drive control device for power semiconductor element and power module

Abstract

A classification circuit (22) generates first information for classifying an operation state of a power semiconductor element (Q) into one of a plurality of operation regions decided in advance. A selection circuit (27) generates second information for selecting a plurality of modes different in switching speed in accordance with a user input (INext2). A characteristic control circuit (21) stores a drive adjustment signal in advance for each combination of the plurality of operation regions and the plurality of modes, and outputs the drive adjustment signal in the combination of one operation region and one mode selected in accordance with the first information and the second information. At turn-on and turn-off of the power semiconductor element (Q), a gate drive circuit (20) charges and discharges a gate at a charging speed and a discharging speed variable in accordance with the drive adjustment signal from the characteristic control circuit (21).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a drive control device for a power semiconductor element and a power module. BACKGROUND

[0002] For switching operation of a voltage drive type semiconductor element typified by a MOS-FET (Metal-Oxide-Semiconductor Field-Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor), a drive control device is applied which charges and discharges a control electrode (gate) of the semiconductor element in accordance with an on-off control signal.

[0003] It is known that there is a trade-off relationship between the magnitude of power loss (so-called switching loss) of the semiconductor element and the magnitude of surge at the time of such switching operation. That is, the surge becomes large when the charging and discharging speed of the gate is increased in order to reduce the switching loss, and on the other hand, the switching loss becomes large when the charging and discharging speed of the gate is reduced in order to reduce the surge. In the drive control device for the semiconductor element, it is required to appropriately adjust this trade-off.

[0004] For example, in Japanese Patent Application Publication No. 2010-283973 (Patent Literature 1), a structure is described in which, in a drive device for a power semiconductor element which is controlled by a switch, a plurality of switching elements are connected in parallel to a charging path and a discharging path of a gate of the power semiconductor element, and the charging and discharging speed of the gate is adjusted in accordance with the number of switching elements which are turned on.

[0005] In particular, in Patent Literature 1, the number of switching elements which control the charging path and the discharging path is controlled in accordance with a switching pattern stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory). In addition, it is described that the switching pattern is variably set in accordance with the current, temperature, or atmospheric pressure of the power semiconductor element.

[0006] PRIOR ART DOCUMENTS

[0007] Patent Literature 1: Japanese Patent Application Publication No. 2010-283973 SUMMARY

[0008] However, it is assumed that the switching loss and surge level which are allowed in the power semiconductor element vary depending on the circuit structure or electrical specifications of the power converter when the structure of the power semiconductor element, and specifically the power converter in which the power semiconductor element is mounted, is different.

[0009] In contrast, in Patent Literature 1, if the current, temperature, and the like of the power semiconductor element are the same, the charge-discharge speed of the gate, in other words, the gate drive capability does not change. Therefore, in a case where the structure, electrical specifications of the application destination are changed, the switching loss or the surge can exceed the allowable value of the power semiconductor element. Or conversely, since the gate drive capability is not suitable for the structure or the electrical specifications, there is also a concern that the performance of the power semiconductor element cannot be sufficiently exerted.

[0010] On the other hand, there is a concern that adjustment of the gate drive capability reflecting the application as described above imposes a large burden on the user side.

[0011] The present disclosure is completed in order to solve such a point, and an object of the present disclosure is to provide a structure in which a trade-off characteristic of the switching loss and the surge of a power semiconductor element controlled by switching can be easily adjusted on the user side.

[0012] In one aspect of the present disclosure, it is a drive control device of a power semiconductor element controlled by switching, including a classification circuit, a characteristic control circuit, a selection circuit, and a gate drive circuit. The classification circuit generates first information for classifying an operation state of the power semiconductor element into one operation region of a plurality of operation regions decided in advance. The characteristic control circuit adjusts a charging speed of a control electrode of the power semiconductor element in an on operation of the power semiconductor element and a discharging speed of the control electrode in an off operation of the power semiconductor element. The selection circuit generates second information for selecting one mode of a plurality of modes different in switching speed of the power semiconductor element in accordance with a user input. The characteristic control circuit pre-stores a drive adjustment signal for setting the charging speed and the discharging speed for each combination of the plurality of operation regions and the plurality of modes, and outputs the drive adjustment signal in a combination of one operation region of the plurality of operation regions and one mode of the plurality of modes selected in accordance with the first information and the second information. The gate drive circuit charges and discharges the control electrode with the charging speed and the discharging speed variably set in accordance with the drive adjustment signal from the characteristic control circuit at the time of the on operation and at the time of the off operation.

[0013] In another aspect of the present disclosure, it is a power module including the above-described drive control device and a power semiconductor element turned on and off by the drive control device.

[0014] According to the present disclosure, by selectively reading out a plurality of drive adjustment signals that are stored in advance in accordance with a combination of an operation state of the power semiconductor element and a mode selected based on a user input, it is possible to adjust the charge / discharge speed of the gate at the time of turning on and at the time of turning off, so it is possible to easily adjust the trade-off characteristics of the switching loss and the surge of the power semiconductor element through mode selection by the user side. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a schematic diagram illustrating the structure of a power conversion system shown as an example of an application destination of the drive control device according to the present embodiment.

[0016] Figure 2 is a block diagram illustrating a structure example of the drive control device according to Embodiment 1.

[0017] Figure 3 is a circuit diagram illustrating one example of the structure of the gate drive circuit shown in Figure 2

[0018] Figure 4 is a conceptual diagram illustrating the classification of the operation state of the power semiconductor element.

[0019] Figure 5 is a conceptual diagram for explaining Figure 2 the retention pattern of the drive adjustment signal data in the memory shown in

[0020] Figure 6 is a conceptual diagram illustrating the mode selection of the switching speed.

[0021] Figure 7 is a flowchart illustrating the control processing for the switching speed control of the power semiconductor element according to Embodiment 1.

[0022] Figure 8 is a waveform chart for explaining an operation example of the switching speed control of the power semiconductor element according to Embodiment 1.

[0023] Figure 9 is a block diagram illustrating a structure example of the drive control device according to Embodiment 2.

[0024] Figure 10 is a flowchart illustrating the control processing for the switching speed control of the power semiconductor element according to Embodiment 2.

[0025] Figure 11 is a waveform chart for explaining an operation example of the switching speed control of the power semiconductor element according to Embodiment 2.

[0026] Figure 12 is a block diagram illustrating Figure 11 ​Conceptual diagram of mode change in the illustrated example of operation of the switching speed control.

[0027] Figure 13 is a diagram Figure 2 Circuit diagram of a first modification example of the structure of the gate drive circuit illustrated.

[0028] Figure 14 is a diagram Figure 2 Circuit diagram of a second modification example of the structure of the gate drive circuit illustrated.

[0029] Figure 15 is a diagram DETAILED DESCRIPTION

[0030] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Furthermore, the same or corresponding portions in the drawings are added with the same symbol, and the description thereof will not be repeated in principle.

[0031] Embodiment 1.

[0032] Figure 1 is a diagram

[0033] Referring to Figure 1 , the power conversion system 100 is provided with a direct-current power supply 101, a direct-current support capacitor (DC link capacitor) 102, a three-phase inverter 103 which is a representative example of a power converter, and a drive control device 10A.

[0034] The direct-current power supply 101 is a voltage source that outputs a constant direct-current voltage Vdc, and can be constituted by an electric storage device such as a battery or a capacitor, an AC / DC converter that converts an alternating-current voltage from a commercial system into a direct-current voltage, or a combination thereof. By using an electric storage device, regenerative electric power can be recovered.

[0035] The direct-current support capacitor 102 is connected between a high-voltage side power line PL and a low-voltage side power line NL that connect the direct-current side of the three-phase inverter 103 and the direct-current power supply 101. The voltage (Vdc) of the direct-current side of the three-phase inverter 103 is smoothed by removing an alternating-current fluctuation component by the direct-current support capacitor 102.

[0036] The three-phase inverter 103 includes a branch of a three-phase section (U phase, V phase, and W phase) that is connected in parallel between the power lines PL and NL. The branch of the U phase has power semiconductor elements Qup and Qun that are connected in series between the power lines PL and NL via an alternating-current node Nu.

[0037] Likewise, the leg of the V phase has power semiconductor elements Qvp, Qvn connected in series between the power lines PL and NL via an AC node Nv. The leg of the W phase has power semiconductor elements Qwp, Qwn connected in series between the power lines PL and NL via an AC node Nw.

[0038] The power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, Qwn are each constituted by a power semiconductor element that is switch-controlled in response to a voltage of a control electrode (gate) of a MOS-FET, an IGBT, or the like. In the present embodiment, a structure example using an IGBT is shown. For each of the power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, Qwn, a freewheeling diode Dup, Dun, Dvp, Dvn, Dwp, Dwn is connected in antiparallel. Figure 1

[0039] The AC motor 104 is connected to the AC nodes Nu, Nv, Nw, which correspond to the AC side of the three-phase inverter 103. The three-phase inverter 103 converts the direct-current voltage Vdc from the direct-current power supply 101 into a three-phase alternating-current voltage applied to the AC motor 104 through switch control of the power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, Qwn. Thereby, the AC motor 104 can be driven at variable speed.

[0040] For example, the power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, Qwn are turned on and off in accordance with control signals Sup, Sun, Svp, Svn, Swp, Swn in accordance with output instructions of pulse width modulation control (PWM) for converting a direct-current voltage into a three-phase alternating-current voltage.

[0041] The drive control device 10A drives and controls the voltage of the control electrode (gate) of the power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, Qwn in accordance with the control signals Sup, Sun, Svp, Svn, Swp, Swn. Thereby, the power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, Qwn are each switch-controlled.

[0042] ​The power semiconductor element controls a main current flowing between the first main electrode and the second main electrode in accordance with the voltage of the control electrode (gate electrode). In the case where the power semiconductor element Q is an IGBT, the first main electrode is the "collector electrode" and the second main electrode is the "emitter electrode", and the collector-emitter current (hereinafter, simply referred to as the collector current Ic) as the main current is controlled in accordance with the gate voltage Vg. Further, hereinafter, in the case where the power semiconductor elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn are included, the power semiconductor element Q is also simply referred to. Similarly, in the case where the control signals Sup, Sun, Svp, Svn, Swp, and Swn are included, the control signal S is described.

[0043] In each of the power semiconductor elements Q, in the off state, the voltage between the first and second main electrodes (collector-emitter voltage Vce) (Vce > 0) is generated, and on the other hand, Ic = 0. In contrast, in the on state, Ic > 0, and on the other hand, the collector-emitter saturation voltage Vcesat is very small, so Vce is substantially 0 (V) with respect to the direct current voltage Vdc.

[0044] In the conduction operation in which the power semiconductor element Q is switched from the off state to the on state, Vce decreases toward 0 in accordance with the rise of the gate voltage Vg, and on the other hand, Ic rises from 0. In contrast, in the cutoff operation in which the power semiconductor element Q is switched from the on state to the off state, Ic decreases toward 0 in accordance with the decrease of the gate voltage Vg, and on the other hand, Vce rises from 0.

[0045] In the transition period in which the gate voltage Vg changes along with the cutoff operation and the conduction operation, a period in which both Vce and Ic are not 0 occurs, so in this period, a power loss (switching loss) corresponding to the time integral value of Ic Vce occurs.

[0046] Further, it is known that a surge current occurs in the conduction operation in addition to the switching loss. The surge current occurs in association with the reverse recovery characteristics of the freewheeling diode located in the opposite branch of each of the power semiconductor elements Q. For example, the surge current occurring at the time of conduction of the power semiconductor element Qup depends on the amount of current change (dlc / dt) at the time of conduction and the characteristics of the freewheeling diode Dun connected in antiparallel with the power semiconductor element Qun opposite to the power semiconductor element Qup.

[0047] In addition, it is known that a surge voltage occurs in the cutoff operation in addition to the switching loss. The surge voltage occurs in accordance with the product of the wiring inductance (parasitic inductance) of the power converter (three-phase inverter 103) including the power lines PL and NL and the amount of current change (dlc / dt) at the time of cutoff.

[0048] By reducing the rate of change of Vce, Ic in the off operation and the on operation, i.e., by reducing the switching speed, the surge voltage and the surge current are suppressed. On the other hand, when the switching speed is reduced, the time until Ic = 0 at the time of off and the time until Vce = 0 at the time of on become longer, so the switching loss increases. Thus, in each of the on operation and the off operation of the power semiconductor element, the switching loss and the surge component generally become in a trade-off relationship.

[0049] For example, in a case where the switching speed is low although the surge tolerance is sufficient, the power conversion efficiency is reduced due to the increase in the switching loss. On the other hand, in a case where the switching speed is excessively high for the pursuit of the power conversion efficiency, if the surge occurring exceeds the tolerance, it can lead to the destruction of the element or the like.

[0050] Therefore, in the present embodiment, a structure for appropriately adjusting the switching speed without excessively increasing the adjustment burden on the user of the power semiconductor element is described.

[0051] Figure 2 is a block diagram illustrating a structure example of the drive control device according to Embodiment 1.

[0052] Referring to Figure 2 , the drive control device 10A according to Embodiment 1 includes a gate drive circuit 20, a characteristic control circuit 21, a classification circuit 22, and a selection circuit 27. In Figure 2 , a structure corresponding to one power semiconductor element Q is illustrated.

[0053] The gate drive circuit 20 turns on and off, i.e., performs switching control of the corresponding power semiconductor element Q in accordance with a control signal S at a switching speed variably set in accordance with drive adjustment signals Sp1 to Spn, Sn1 to Snn output from the characteristic control circuit 21.

[0054] The control signal S and the drive adjustment signals Sp1 to Spn, Sn1 to Snn are each a 2-value signal set to one of "1 (logic high level)" and "0 (logic low level)". Further, the control signal S is set to "1" during the on period of the power semiconductor element Q, and the control signal S is set to "0" during the off period of the power semiconductor element Q.

[0055] Figure 3 is a circuit diagram illustrating one example of the structure of the gate drive circuit illustrated in Figure 2 .

[0056] Referring to Figure 3The gate drive circuit 20 has n (n: a natural number of 2 or more) p-type MOS-FETs (hereinafter referred to as PMOS transistors) MP1 to MPn connected in parallel between the first power supply line VDL and a node Ng, and n N-type MOS-FETs (hereinafter referred to as NMOS transistors) NP1 to NPn connected in parallel between the second power supply line VSL and the node Ng. The node Ng is electrically connected to the gate of the power semiconductor element Q.

[0057] The second power supply line VSL transmits a power supply voltage Vss for turning off the power semiconductor element Q. The power supply voltage Vss is set to the same voltage as the emitter voltage of the power semiconductor element Q. The first power supply line VDL transmits a power supply voltage Vdd for turning on the power semiconductor element Q. For example, for an IGBT, Vdd = 15 [V] can be set.

[0058] Hereinafter, the voltage difference of the node Ng with respect to the power supply voltage Vss is referred to as a gate voltage Vg. When the gate voltage Vg is higher than the threshold voltage (Vt) of the power semiconductor element Q, the power semiconductor element Q becomes in an on state.

[0059] Control signals gpl to gpn are input to the gates of the PMOS transistors MP1 to MPn, respectively. When the control signals gpl to gpn are "0", respectively, the PMOS transistors MP1 to MPn are turned on, respectively, and a charging current of the node Ng (i.e., the gate of the power semiconductor element Q) is supplied by the power supply voltage Vdd.

[0060] The control signals gpl to gpn of the PMOS transistors MP1 to MPn are set in accordance with a control signal S of the power semiconductor element Q and drive adjustment signals Spl to Spn from the characteristic control circuit 21. When the control signal S is "0", the control signals gpl to gpn are all set to "1", and the PMOS transistors MP1 to MPn are all turned off. Therefore, a charging path of the node Ng is not formed.

[0061] In contrast, when the control signal S is "1", the control signals gpl to gpn are set to "1" or "0" in correspondence with the drive adjustment signals Spl to Spn. Specifically, when the drive adjustment signals Spl to Spn are "1", respectively, the control signals gpl to gpn are set to "0", respectively, and when the drive adjustment signals Spl to Spn are "0", respectively, the control signals gpl to gpn are set to "1", respectively.

[0062] As a result, the number of turned-on PMOS transistors MP1 to MPn changes in accordance with the drive adjustment signals Sp1 to Spn at the time of the on operation in which the control signal S changes from "0" to "1". That is, the charging current of the node Ng at the time of the on operation, that is, the charging drive capability of the gate, is adjusted in accordance with the drive adjustment signals Sp1 to Spn. For example, the control signals gp1 to gpn can be set by NAND (NOT AND) operation of the control signal S and the control signals gp1 to gpn. It is understood that the greater the charging current, the higher the charging drive capability, and the higher the gate charging speed.

[0063] When the gate charging speed is set to be high in accordance with the drive adjustment signals Sp1 to Spn, the switching loss at the time of the on of the power semiconductor element Q decreases, and instead, the inrush current increases. On the other hand, when the gate charging speed is set to be low, the switching loss at the time of the on of the power semiconductor element Q increases, and instead, the inrush current decreases.

[0064] Similarly, the control signals gn1 to gnn of the NMOS transistors MN1 to MNn are set in accordance with the control signal S and the drive adjustment signals Sn1 to Snn from the characteristic control circuit 21. When the control signal S is "1", the control signals gn1 to gnn are all set to "0", and the NMOS transistors MN1 to MNn are all turned off. Therefore, a discharge path of the node Ng is not formed.

[0065] On the contrary, when the control signal S is "0", the control signals gn1 to gnn are set to "1" or "0" in correspondence with the drive adjustment signals Sn1 to Snn. Specifically, when the drive adjustment signals Sn1 to Snn are "1", respectively, the control signals gn1 to gnn are set to "1", respectively, and when the drive adjustment signals Sn1 to Snn are "0", respectively, the control signals gn1 to gnn are set to "0", respectively.

[0066] As a result, the number of turned-on NMOS transistors MN1 to MNn changes in accordance with the drive adjustment signals Sn1 to Snn at the time of the off operation in which the control signal S changes from "1" to "0". That is, the discharge current of the node Ng at the time of the off operation, that is, the discharge drive capability of the gate, is adjusted in accordance with the drive adjustment signals Sn1 to Snn. For example, the control signals gp1 to gpn can be set by AND (AND) operation of the inverted signal ( / S) of the control signal S and the control signals gp1 to gpn. It is understood that the greater the discharge current, the higher the discharge drive capability, and the higher the gate discharge speed.

[0067] When the discharging speed of the gate becomes high according to the drive adjustment signal Sn1 to Snn, the switching loss at the time of the cutoff of the power semiconductor element Q decreases, and instead, the surge increases. On the other hand, when the discharging speed of the gate becomes low, the switching loss at the time of the cutoff of the power semiconductor element Q increases, and instead, the surge decreases.

[0068] Further, the more the number (N) of the PMOS transistors and the NMOS transistors is, the more finely the charging speed and the discharging speed can be adjusted, and on the other hand, the cost increases. Therefore, regarding the number N, a proper value is designed in consideration of the adjustment demand of the user side and the cost. Or, the transistor size (current driving ability) of the PMOS transistors and the NMOS transistors can be set in stages according to the factorial of 2, and the charging speed and the discharging speed can be set to 2 n stages using n PMOS transistors or NMOS transistors.

[0069] Referring again to Figure 2 , the setting of the drive adjustment signals Sp1 to Spn, Sn1 to Snn will be described in detail.

[0070] The characteristic control circuit 21 has a counter 23, a register 24, a memory 25, and a writing circuit 26. The counter 23, the register 24, and the memory 25 operate in synchronization with a clock signal CLK input from the outside to the drive control device 10A. The counter 23 and the register 24 are each configured by a flip-flop and a latch, which are not shown.

[0071] The writing circuit 26 has a function of writing the drive adjustment signals Sp1 to Spn, Sn1 to Snn to the memory 25 by an external input INext1 to the drive control device 10A.

[0072] The selection circuit 27 generates a mode instruction value MD for designating one mode of a plurality of modes in which the switching speed is different, in accordance with an external input INext2 to the drive control device 10A. The mode instruction value MD is input to the memory 25.

[0073] The classification circuit 22 has a current detection section 28, a temperature detection section 29, a current measurement section 30, and a temperature measurement section 31.

[0074] The current measurement section 30 measures the main current (collector current Ic) flowing in the ON state of the power semiconductor element Q. The current measurement section 30 can be configured by, for example, a current sensor of a Hall element type or a shunt resistor installed to the collector terminal of the power semiconductor element Q (IGBT). The measurement value of the current measurement section 30 is input to the current detection section 28.

[0075] The current detection section 28 detects which of the (M+l) current regions the element current Iq in the current operation state of the power semiconductor element Q belongs to, by comparison of the element current Iq calculated from the measurement value of the current measurement section 30 and the M boundary values (M: a natural number) set in advance by the user.

[0076] For example, the element current Iq can be calculated using the collector current Ic of the power semiconductor element Q during the on period other than the conduction period during which the collector current Ic of the power semiconductor element Q is transiently changed. That is, the current detection section 28 can be configured in a manner including a low-pass filter for removing the transient change, and the element current Iq can be calculated from the collector current Ic after the low-pass filter during the on period.

[0077] Alternatively, the current measurement section 30 can also be configured to measure the load current which is the output of the three-phase inverter 103, and output the measured load current to the current detection section 28, and the element current Iq can be calculated.

[0078] The temperature measurement section 31 is disposed in the vicinity of or on the same chip as the power semiconductor element Q, and measures the temperature of the power semiconductor element Q (hereinafter also referred to as the element temperature Tq) by measuring the temperature of the disposition site. The temperature measurement section 31 is configured, for example, by a thermistor, a temperature sensing diode, or a thermocouple element. The measurement value of the temperature measurement section 31 is input to the temperature detection section 29.

[0079] The temperature detection section 29 detects which of the (L+l) temperature regions the element temperature Tq in the current operation state of the power semiconductor element Q belongs to, by comparison of the measurement value of the temperature measurement section 31 and the L boundary values (L: a natural number) set in advance by the user.

[0080] Figure 4 is a conceptual diagram illustrating the classification of the operation state of the power semiconductor element.

[0081] Referring to Figure 4 , the element temperature Tq of the power semiconductor element Q is classified into one of the (L+l) temperature regions by comparison with the above-described L boundary values. Similarly, the element current Iq of the power semiconductor element Q is classified into one of the (M+l) current regions by comparison with the above-described M boundary values. It can be understood that the operation state of the power semiconductor element Q is classified into (M+l)x(L+l) regions by the combination of the classification of the element temperature Tq and the classification of the element current Iq.

[0082] In the present embodiment, L = M = 2, the element temperature Tq is classified into 3 stages of 1 to 3, and the element current Iq is classified into 3 stages of A to C. As a result, 3 regions are classified. As a result, the operation state of the power semiconductor element Q is classified into 3 x 3 = 9 regions (operation regions) of A1 to A3, B1 to B3, and C1 to C3.

[0083] Thus, by the classification circuit 22 of Figure 2 , the current operation state of the power semiconductor element Q is classified according to the element current Iq and the element temperature Tq, and one of the (M + 1) x (L + 1) operation regions defined in advance is selected.

[0084] Generally, in the power semiconductor element typified by an IGBT, there is a tendency that the switching characteristics vary depending on the main current and the temperature. Specifically, there is a tendency that the greater the main current, and the higher the junction temperature becomes by being in a high temperature, the greater the switching loss at the time of turn-on and turn-off. Therefore, when the main current or the temperature of the power semiconductor element varies, the relationship between the switching loss and the surge also varies.

[0085] Therefore, it is preferable that on the user side of the power conversion system in which the power semiconductor element is mounted, the relationship between the switching loss and the surge (i.e., the trade-off characteristics) can be adjusted in accordance with the classification of the operation state defined by the combination of the temperature and the current.

[0086] Referring again to Figure 2 , a specific operation example of the drive control device 10A will be described.

[0087] The drive adjustment signal data of the switching speed of the power semiconductor element Q is written to the memory 25 by an external input INext1 input from the outside to the drive control device 10A.

[0088] In Figure 5 , a conceptual diagram for explaining the holding pattern of the drive adjustment signal data in the memory is shown.

[0089] Referring to Figure 5 , in each of the operation regions A1 to A3, B1 to B3, and C1 to C3 of the power semiconductor element Q shown by the combination of the classification (A to C) of the element current Iq and the classification (1 to 3) of the element temperature Tq, the drive adjustment signal data composed of the drive adjustment signals Sp1 to Spn (for charging speed adjustment) and Sn1 to Snn (for discharging speed adjustment) is held only the number of modes selectable by the user.

[0090] Figure 6 is a conceptual diagram for explaining the mode selection of the switching speed.

[0091] Referring toFigure 6 In the present embodiment, the user can select a high-speed mode (MD1), a medium-speed mode (MD2), and a low-speed mode (MD3) with respect to the mode of the switching speed.

[0092] As described above, the higher the switching speed, the lower the power loss, and on the other hand, the larger the surge. Conversely, the lower the switching speed, the lower the surge, and on the other hand, the larger the power loss. In order to lower the switching speed, it is necessary to reduce the gate charge current (i.e., the charge drive capability) at the time of the on operation and the gate discharge current (i.e., the discharge drive capability) at the time of the off, and to lower the charge and discharge speed of the gate.

[0093] The user can select the modes MD1 to MD3 in accordance with the application of the power semiconductor element. For example, in a case where the power semiconductor element is mounted in a system in which the parasitic inductance is small, the surge occurs with a margin, so in order to preferentially reduce the switching loss, the high-speed mode (MD1) can be selected. Or conversely, in an application in which the margin of the surge is small, in order to preferentially reduce the surge, the low-speed mode (MD3) can be selected. Or, the medium-speed mode (MD2) can also be selected so as to balance the two.

[0094] Further, in the present embodiment, the selection within the three modes MD1 to MD3 is explained with respect to the switching speed, but the number of selectable modes can be set to any natural number of two or more.

[0095] Referring again to Figure 5 , for example, in the operation region Al on the lowest temperature side and with a small current, the drive adjustment signal data DA1(MD1) to DA1(MD3) corresponding to the modes MD1 to MD3, respectively, are held. The drive adjustment signal data DA1(MD1) to DA1(MD3) each include one set of drive adjustment signals Sp1 to Spn, Sn1 to Snn.

[0096] In order to increase the switching speed, it is necessary to increase the charge drive capability (discharge current) of the gate at the time of the on operation and the discharge drive capability (discharge current) of the gate at the time of the off, and to increase the charge and discharge speed of the gate. Therefore, DA1(MD1) is set in a manner so as to increase the number of turn-on of the PMOS transistors MP1 to MPn( Figure 2 ) compared to DA1(MD2) and DA1(MD3), and DA1(MD1) is set in a manner so as to increase the number of turn-on of the NMOS transistors MN1 to MNn( Figure 2 ) compared to DA1(MD2) and DA1(MD3).

[0097] On the contrary, in order to reduce the gate charge / discharge speed, DA1 (MD3) for the low speed mode is set in a manner that the number of turn-on of the PMOS transistors MP1 to MPn and the NMOS transistors MN1 to MNn is reduced compared to DA1 (MD1) and DA1 (MD2). Figure 2 ) are set in a manner that the number of turn-on of the PMOS transistors MP1 to MPn and the NMOS transistors MN1 to MNn is reduced compared to DA1 (MD1) and DA1 (MD2).

[0098] Thus, in the memory 25, the drive adjustment signal data that is different in each of the modes MD1 to MD3 is held for each of the operation regions of the power semiconductor element Q. In the example of Figure 5 , the number of selectable modes is three, so three sets of drive adjustment signals are held in each of the nine operation regions, and thus a total of 9 x 3 = 27 drive adjustment signal data are stored.

[0099] By determining the current classification (A to C), the temperature classification (1 to 3), and the mode selection (MD1 to MD3) from the memory 25, one drive adjustment signal data can be read out from the plurality of (for example, 27) drive adjustment signal data that are held in advance.

[0100] Further, the drive adjustment signal data illustrated in Figure 5 may be written in advance at the time of factory shipment or at the stage of construction work by the manufacturer side of the drive control device 10A, the three-phase inverter (power converter) 103, or the power conversion system 100, using the above-described external input INext1. Also, at the user side of the power conversion system 100, it is also possible to rewrite an arbitrary drive adjustment signal data using the external input INext1. At this time, the drive adjustment signal data can be rewritten in conjunction with the selection of the current classification (A to C), the temperature classification (1 to 3), and the mode selection (MD1 to MD3).

[0101] Referring back to Figure 2 , the user can input a mode selection instruction of the switching speed through the external input INext2. The selection circuit 27 generates a mode instruction value MD indicating which one of the modes MD1 to MD3 is selected, based on the external input INext2. In Embodiment 1, the mode instruction value MD is fixed in the operation of the power semiconductor element Q.

[0102] Next, the control processing for the switching speed control of the power semiconductor element according to Embodiment 1 will be described using the flowchart of Figure 7 Figure 7 ​is a diagram showing a series of control processes in the operation of the power conversion system 100, i.e., in the operation of the power semiconductor element Q. For example, the processes of the respective steps described below can be executed by software processing implemented by a predetermined program executed by a CPU (Central Processing Unit) or the like not shown. Alternatively, the processes of the respective steps can also be implemented by hardware processing of a dedicated electronic circuit or the like, or a combination of software processing and hardware processing.

[0103] Referring to Figure 7 After the operation of the power semiconductor element Q starts due to the start of the operation of the power conversion system 100, the drive control device 10A reads a mode selection by a user according to the external input INext2 in step (hereinafter abbreviated as "S") 100. Thereby, in S110, the above-described mode instruction value MD is generated. The mode instruction value MD corresponds to one embodiment of the "first information". Further, the processing of S110 is implemented by the selection circuit 27. Further, with respect to the external input INext2, the previous input value can also be held in the inside of the drive control device 10A until a different value is input.

[0104] The drive control device 10A repeatedly executes the processing of S120 to S180 in synchronization with the clock signal CLK until the operation of the power conversion system 100 stops, i.e., in the operation of the power semiconductor element Q (when the "No" determination of S180).

[0105] The drive control device 10A acquires the element current Iq and the element temperature Tq in each clock cycle in S120. As described above, the element current Iq and the element temperature Tq can be found from the measurement values of the current measuring section 30 and the temperature measuring section 31. Further, in S130, the classification information of the element temperature Tq (for example, information indicating which one of 1 to 3) and the classification information of the element current Iq (for example, information indicating which one of A to C) are generated by classifying the element current Iq and the element temperature Tq in accordance with the above-described "first information". Figure 4 The classification information generated by S130 corresponds to one embodiment of the "first information". Figure 2 The classification information generated by S130 corresponds to one embodiment of the "first information".

[0106] The drive control device 10A determines whether the classification information generated in S130 has changed from the previous clock cycle in S140. Further, at the start of the operation of the power semiconductor element Q, S140 of the initial processing is determined as "Yes".

[0107] When the affirmative determination is made in S140, the drive control device 10A reads out one of the plurality of drive adjustment signal data held in the memory 25 in accordance with the combination of the classification information generated in S130 and the mode instruction value MD through S150. Thus, one set of the drive adjustment signals Sp1-Spn, Sn1-Snn is read out from the memory 25. The read-out drive adjustment signals Sp1-Spn, Sn1-Snn are temporarily held in the register 24 through S160. On the other hand, when the negative determination is made in S140, S150, S160 are skipped to maintain the held contents of the register 24.

[0108] The drive control device 10A outputs the drive adjustment signals Sp1-Spn, Sn1-Snn held in the register 24 for each clock period to the gate drive circuit 20 through S170. The gate drive circuit 20 performs the on operation of the power semiconductor element Q in accordance with the charge drive capability of the drive adjustment signals Sp1-Spn, and performs the off operation of the power semiconductor element Q in accordance with the discharge drive capability of the drive adjustment signals Sn1-Snn.

[0109] Thus, for each 1 period of the clock signal CLK, adjustment of the switching speed corresponding to the operation state (temperature and current) of the power semiconductor element Q can be achieved on the basis of the mode selection (high speed / medium speed / low speed) of the switching speed made by the user. For example, the period of the clock signal CLK is set to be the same as or an integer multiple of the switching period of the power semiconductor element Q.

[0110] In Figure 8 , a waveform chart for explaining an operation example of the switching speed control of the power semiconductor element according to Embodiment 1 is shown.

[0111] Referring to Figure 8 , with respect to the time axis of the horizontal axis, the main current (collector current Ic) of the power semiconductor element Q, the collector-emitter voltage Vce, the gate voltage Vg Figure 2 ), the charge drive capability, the discharge drive capability, and the element temperature Tq are shown on the vertical axis.

[0112] The charge drive capability is a parameter value indicating the magnitude of the charge current of the gate and the magnitude of the charge speed, and can be set to a value indicating the number of on of the PMOS transistors MP1-MPn in the gate drive circuit 20, for example. Similarly, the discharge drive capability is a parameter value indicating the magnitude of the discharge current of the gate and the magnitude of the discharge speed, and can be set to a value indicating the number of on of the NMOS transistors MN1-MNn in the gate drive circuit 20, for example.

[0113] In Figure 8In the example operation, the switching speed mode selection is assumed to be high-speed mode (MD1) specified by the user. As mentioned above, high-speed mode (MD1) is selected in applications where the parasitic inductance value in the main circuit of the power conversion system is small and surge protection can be ensured. The following example operation with high-speed mode selected is represented by solid lines.

[0114] Times t1 and t2 correspond to the timing of the conduction and cutoff operations during the period immediately following the start of the power conversion system 100 and the initial operation of the power semiconductor element Q. During this phase, the element current is low (Category A) and the temperature is low (Category 1), so switching losses and surges are relatively small. Therefore, in operating region A1, the configuration is set to a higher level for both charging and discharging drive capabilities. Figure 5 The drive adjustment signals Sp1~Spn and Sn1~Snn are generated from the drive adjustment signal data DA1(M1). As a result, at times t1 and t2, the switching speed is set relatively high, and the power semiconductor device Q is turned on and off.

[0115] After time t3, starting from the start of operation of the power semiconductor element Q, the conduction and cutoff operations are shown as time progresses, with the element current and element temperature rising.

[0116] At time ta, as the main current Ic increases, the component current Iq changes from category A (small current) to category B (medium current). Therefore, during the switching cycle after time t4, as the operating state of the power semiconductor element Q changes, the drive adjustment signals Sp1~Spn and Sn1~Snn of the drive adjustment signal data DB1 (MD1) constituting the operating region B1 are used. Consequently, the discharge drive capability during the cutoff operation decreases compared to time t2. Similarly, the charging drive capability during the cutoff operation decreases compared to time t1. Therefore, compared to the period from time t1 to t2, the switching speed of the power semiconductor element Q decreases slightly.

[0117] exist Figure 8 In this comparative example, we envision a scenario where a mode selection function for switching speed is not available. In this example, to prioritize avoiding component damage due to surges and adverse effects on the surrounding environment due to electromagnetic noise, we envision an adjustment that reduces the switching speed to a certain extent in response to increases in current and temperature. Figure 8 In the comparison example, dashed lines are used to represent the actions involved.

[0118] In the comparative example, the reduction amounts of the discharging drive capability in the off operation and the charging drive capability in the on operation are set larger than the high-speed mode in the present embodiment in correspondence with the change in the operation region at time ta. Thus, the switching speed of the power semiconductor element Q is lower than in the operation example of the present embodiment. Such adjustment is effective in preventing the destruction of the power semiconductor element Q by suppressing the surge, whereas, in the application capable of securing the margin against the surge as described above, the disadvantage of an increase in the switching loss with an increase in the switching loss accompanying the rise in the main current can become significant.

[0119] At time tb, the element temperature Tq changes from category 1 (low temperature) to category 2 (medium temperature) accompanying the temperature rise of the power semiconductor element Q with an increase in the on time. Further, when the power semiconductor element Q is continuously operated within the rating, the temperature range of category 2 can be set by assuming the temperature range that can be normally maintained by the cooling mechanism such as a heat sink provided to the power semiconductor element Q.

[0120] Thus, in the switching period after time t5, the drive adjustment signals Sp1 to Spn, Sn1 to Snn of the drive adjustment signal data DB2 (MD1) constituting the operation region B2 are used accompanying the change in the operation state of the power semiconductor element Q. Thus, the discharging drive capability in the off operation and the charging drive capability in the on operation are further reduced. Thus, the switching speed of the power semiconductor element Q is further lowered than in the operation in the operation region Bl.

[0121] In the comparative example, the reduction amounts of the charging drive capability and the discharging drive capability corresponding to the change in the operation state at time tb (temperature rise) are set larger than the high-speed mode in the present embodiment. Thus, it can be understood that the switching speed of the power semiconductor element Q is further reduced than in the control of the present embodiment.

[0122] Therefore, in the application in which the high-speed mode is selectable, the disadvantage of an increase in the switching loss with an increase in the switching loss accompanying the temperature rise can become significant when the switching speed control of the comparative example is executed.

[0123] On the contrary, in the present embodiment, the following structure can be realized: the switching speed control that gives priority to the surge suppression comparable to the comparative example is set in the low-speed mode (MD3), and the user can select the other mode in which the switching speed is high through the external input INext2. As a result, in the application in which the margin against the surge can be secured due to the small parasitic inductance value or the application in which the snubber circuit for the surge absorption is provided, the switching loss can be reduced by the user selecting the high-speed mode (MD1).

[0124] Thus, it is possible to achieve an increase in power conversion efficiency and a suppression of an increase in element temperature. As a result, the operating range of the power semiconductor element Q (IGBT) is expanded, and it is possible to expect that a wide range of applications can be dealt with by a single type of power semiconductor element Q. On the other hand, in applications in which the surge margin is small, the user can select the low-speed mode (MD1) or the medium-speed mode (MD2) by external input INext2.

[0125] Thus, according to the drive control device related to the present embodiment, in addition to the adjustment function of the switching speed corresponding to the operating state (for example, the current and the temperature) of the power semiconductor element Q, the user can also have the adjustment function of the switching speed that matches the situation of the application destination (the surge margin and the like). In particular, it is not necessary to directly rewrite the drive adjustment signal, but it is possible to adjust the switching speed by the mode selection instruction implemented by the external input INext2, so it is possible to easily adjust the trade-off characteristics of the switching loss and the surge of the power semiconductor element on the user side.

[0126] Further, a control structure is adopted in which the drive adjustment signals Sp1-Spn, Sn1-Snn of the gate drive circuit 20 are switched in accordance with a change in the operating region of the power semiconductor element Q based on the measured values of the element temperature Tq and the element current Iq. Figure 4 As a result, for applications in which the current range and the temperature range of the power semiconductor element Q are different, it is not necessary to change the structure of the current detection section 28, the temperature detection section 29, and the gate drive circuit 20, but it is possible to deal with them with a common structure.

[0127] Further, with regard to the gate drive circuit 20, as with the structure example of Figure 3 , it is possible to adjust the charging speed and the discharging speed of the gate by turning on and off the PMOS transistor and the NMOS transistor connected in parallel, so it is possible to make the node Ng that generates the gate voltage Vg low impedance. As a result, it is not necessary to provide a power supply of negative voltage, but it is possible to adjust the discharging speed.

[0128] Embodiment 2

[0129] In Embodiment 1, the mode selection of the switching speed is fixed in the operation of the power semiconductor element, but in Embodiment 2, a control structure is described in which the mode selection is automatically switched in accordance with the element current Iq and the element temperature Tq, that is, the operating state of the power semiconductor element.

[0130] Figure 9 is a block diagram that illustrates a structure example of the drive control device related to Embodiment 2.

[0131] Referring to Figure 9 , the drive control device 10B related to Embodiment 2 is different fromFigure 2 The drive control device 10A shown differs in that the selection circuit 27B is provided instead of the selection circuit 27.

[0132] The selection circuit 27B inputs an external input INext3 in addition to the external input INext2 common to Embodiment 1. At the start of operation of the power semiconductor element, the selection circuit 27B specifies the mode selected by the external input INext2 by the mode instruction value MD. That is, in Embodiment 2, the mode selected by the external input INext2 means the initial value of the mode selection.

[0133] The external input INext3 includes information for switching the mode selection in accordance with the operating state of the power semiconductor element Q (for example, the element temperature Tq and the element current Iq). As one example, the external input INext3 includes a temperature threshold value Tth and a current threshold value Ith for switching the mode selection, information for specifying the mode selected in the case where Tq > Tth (an over-temperature state), and information for specifying the mode selected in the case where Iq > Ith (an over-current state).

[0134] Here, upon detection of at least one of the over-current state and the over-temperature state, the selection circuit 27B generates the mode instruction value MD in such a manner that the low-speed mode (MD3) is selected in accordance with the above information. On the other hand, the selection circuit 27B generates the mode instruction value MD in such a manner that the high-speed mode (MD1) is selected in accordance with the external input INext2 in the case where Tq ≤ Tth and Iq ≤ Ith.

[0135] Further, the current threshold value Ith for detecting the over-current state can also be common to the boundary values of the classification B (medium current) and the classification C (large current) in Figure 4 . Likewise, the temperature threshold value Tth for detecting the over-temperature state can also be common to the boundary values of the classification 2 (medium temperature) and the classification 3 (high temperature) in Figure 4 .

[0136] In the drive control device 10B related to Embodiment 2, the structure of the portion other than the setting of the mode instruction value MD is the same as that of the drive control device 10A related to Embodiment 1, so a detailed explanation will not be repeated.

[0137] Figure 10 is a flowchart illustrating the control processing for the switching speed control of the power semiconductor element related to Embodiment 2. With regard to Figure 10 , the same applies to Figure 7 . The series of control processing in the operation of the power conversion system 100 is illustrated in the same manner, and the processing of each step can be realized by at least one of the above software processing and hardware processing.

[0138] Reference Figure 10 When the power semiconductor element Q starts operating, the drive control device 10B reads the mode selection information input by the user using external inputs INext2 and INext3 via S105. As described above, the mode selection information can include the initial value of the mode selection, the current threshold Ith and temperature threshold Tth for mode switching, and information specifying the mode selection after switching.

[0139] Drive control device 10B and Figure 7 Similarly, until the operation of the power semiconductor element Q stops (when "No" is determined in S180), that is, during the operation of the power semiconductor element Q, the processing of S120 to S180 is repeatedly executed in sync with the clock signal CLK.

[0140] Drive control device 10B in communication with Figure 7 Similarly, when obtaining the component temperature Tq and component current Iq in each clock cycle via S120, one of the modes MD1 to MD3 is selected via S125 based on the obtained component temperature Tq, component current Iq, and mode selection information (S105). Then, the mode instruction value MD is output from the selection circuit 27B to the memory 25.

[0141] For example, in S125, as described above, a high-speed mode (MD1) is selected when Tq≤Tth and Iq≤Ith, and a low-speed mode (MD3) is selected when at least one of Tq>Tth and Iq>Ith is true.

[0142] Drive control device 10B via and Figure 7 Similarly, in S130, based on the obtained component temperature Tq and component current Iq (S120), classification information of component temperature Tq (e.g., information indicating which one of 1 to 3) and classification information of component current Iq (e.g., information indicating which one of A to C) are generated.

[0143] In S145, the drive control device 10B determines whether at least one of the modes selected in S125 (mode command value MD) and the classification information generated in S140 has changed since the last clock cycle. Furthermore, at the start of operation of the power semiconductor element Q, the control device 10B determines whether, in conjunction with S140 (…), the mode selected in S125 (mode command value MD) has changed. Figure 7 Similarly, it is judged as "yes" in S145.

[0144] When the drive control device 10B determines "yes" in S145, it communicates with... Figure 7The same as S150 and S160, in accordance with the combination of the mode (one of MD1 to MD3) selected in S125 and the classification information generated in S130, one set of drive adjustment signals Sp1 to Spn, Sn1 to Snn is read out from the memory 25 and temporarily saved to the register 24. On the other hand, at the "No" determination in S145, S150, S160 are skipped and the saved content of the register 24 is maintained. Also, by the same as S140, the drive adjustment signals Sp1 to Spn, Sn1 to Snn saved in the register 24 at each clock cycle are output to the gate drive circuit 20. Figure 7 The same as S170, the drive adjustment signals Sp1 to Spn, Sn1 to Snn saved in the register 24 at each clock cycle are output to the gate drive circuit 20.

[0145] Thus, the gate drive circuit 20 performs the on operation of the power semiconductor element Q in accordance with the charge drive capability of the drive adjustment signals Sp1 to Spn and performs the off operation of the power semiconductor element Q in accordance with the discharge drive capability of the drive adjustment signals Sn1 to Snn.

[0146] Thus, in the drive control device 10B related to Embodiment 2, it is possible to switch the mode selection in the operation of the power semiconductor element Q in accordance with the mode selection information read in S105.

[0147] In Figure 11 , a waveform chart for explaining an operation example of the switching speed control of the power semiconductor element related to Embodiment 2 is shown. Figure 11 The horizontal axis and the vertical axis of Figure 8 are the same as those of

[0148] Referring to Figure 11 , the switching operation of the power semiconductor element Q in the period of time t1 to t2 is the same as that of Figure 8 , at time tx, the operation state of the power semiconductor element Q changes in the same manner as at time ta of Figure 8 . That is, the element current Iq changes from classification A (small current) to classification B (medium current) in association with the rise of the main current Ic. Thus, in the switching cycle after time t4, the drive adjustment signals Sp1 to Spn, Sn1 to Snn of the drive adjustment signal data DB1 (MD1) constituting the operation region B1 in the high-speed mode are used.

[0149] After that, the power semiconductor element Q continues the operation, and at the time point of time t6, in the operation region of the power semiconductor element Q, the element temperature Tq is classification 2 (medium temperature) and the element current Iq is classification B (medium current). At this time point, in the case where the switching loss increases in association with the rise of the current and the temperature, the high-speed mode (MD1) is maintained and the switching loss is suppressed.

[0150] And, at time ty, the element current Iq exceeds the current threshold Ith and becomes an overcurrent state. In correspondence therewith, in the operation of the power semiconductor element Q, as shown in Figure 12 the mode selection is switched from the high-speed mode (MD1) to the low-speed mode (MD3). Here, with Iq > Ith, the classification of the element current Iq also changes from the middle current (classification B) to the large current (classification C).

[0151] Referring again to Figure 11 In the switching period after time t7, the drive adjustment signal data DC2(MD3) of the low-speed mode (MD3) constituted by the drive adjustment signals Sp1-Spn, Sn1-Snn in the operation region C2 using the large current and the middle temperature is used.

[0152] Thus, the discharging drive capability at the time of cutoff and the charging drive capability at the time of conduction are reduced to the same as in the comparative example explained in Figure 8 As a result, in order to prevent the occurrence of a surge exceeding the allowable value under a large current, the conduction operation and the cutoff operation of the power semiconductor element Q can be controlled to a relatively slow speed that prioritizes the safe operation. Further, when the element current Iq decreases and escapes from the overcurrent state, the high-speed mode (MD1) is selected again, and thus the switching loss can be reduced.

[0153] Thus, in the embodiment 2, in the operation of the power semiconductor element Q, in the normal use state, the switching speed that matches the application is selected to reduce the switching loss, and on the other hand, in the case where the overcurrent state or the overtemperature state temporarily occurs due to the influence of disturbance or the like, the switching speed is automatically adjusted in a manner that prioritizes the safe operation. As a result, in addition to the effects explained in the embodiment 1, the effect of realizing a switching operation with high robustness against the influence of disturbance on the power semiconductor element Q is also produced.

[0154] In particular, with the mode selection information input before the start of the operation of the power semiconductor element Q, the mode selection of the switching speed that automatically corresponds to the overcurrent state or the overtemperature state is automatically switched without the user side coping later, and thus the adjustment of the user side is also easy in the part related to the embodiment 2.

[0155] Further, in the embodiment 2, instead of the setting of the above-mentioned current threshold Ith and the temperature threshold Tth, the switching speed that automatically corresponds to the overcurrent state or the overtemperature state can be selected in accordance with Figure 4Each of the action regions shown in the combination of the classification based on the element current Iq and the classification of the element temperature Tq is preset with a selected mode. In this case, the user inputs information on which of the modes MD1 to MD3 is selected for each of the action regions as mode selection information using an external input INext3 to the selection circuit 27B (S105). Also, the selection circuit 27B can accept classification information of the element current and the element temperature of the current detection section 28 and the temperature detection section 29 instead of the element current Iq and the element temperature Tq, and generate the mode instruction value MD (S125).

[0156] Further, in Embodiments 1 and 2, the trade-off characteristics of the switching loss and the surge are explained, but the switching speed also affects the electromagnetic noise that occurs in conjunction with the switching of the power semiconductor element Q. The electromagnetic noise has a tendency to become larger as the switching speed is higher, like the surge. Therefore, it is preferable to select the mode of the switching speed considering the allowance of the electromagnetic noise in addition to the above-described surge. Further, in the present embodiment, the switching speed can be adjusted by the selection of the mode, so even in the case where the electromagnetic noise is added to the factors to be considered, the user side can easily adjust the trade-off characteristics.

[0157] In addition, in each of Embodiments 1 and 2, regarding the gate drive circuit 20 Figure 2 , a circuit structure different from that of Figure 4 can also be applied.

[0158] Figure 13 is a circuit diagram that explains a first modification example of the structure of the gate drive circuit 20.

[0159] Referring to Figure 13 , in the first modification example, the gate drive circuit 20 has a PMOS transistor MP1, an NMOS transistor MN1, and a gate resistance variable circuit 60.

[0160] The PMOS transistor MP1 is connected between the first power supply line VDL and a node Nm. The NMOS transistor MN1 is connected between the node Nm and the second power supply line VSL. An inverted signal ( / S) of the control signal S is input to the gates of the PMOS transistor MP1 and the NMOS transistor MN1. / S is set to "0 (logic low level)" during the turn-on period of the power semiconductor element Q, and on the other hand, is set to "1 (logic high level)" during the turn-off period.

[0161] The gate resistance variable circuit 60 is connected between the node Nm and the node Ng to the gate of the power semiconductor element Q. The gate resistance variable circuit 60 has switches SW1 to SWn and resistance elements R1 to Rn. The switches SW1 to SWn are connected in series with the resistance elements R1 to Rn between the node Nm and the node Ng, respectively. Therefore, in the gate resistance variable circuit 60 as a whole, the groups of the switches SW and the resistance elements R connected in series are connected in parallel n times between the node Nm and the node Ng.

[0162] The switches SW1 to SWn are turned on and off in accordance with the drive adjustment signals Sp1 to Spn, respectively, when the inversion signal / S = "0" (during the turn-on of the power semiconductor element Q). On the other hand, the switches SW1 to SWn are turned on and off in accordance with the drive adjustment signals Sn1 to Snn, respectively, when the inversion signal / S = "1" (during the turn-off of the power semiconductor element Q).

[0163] When the power semiconductor element Q is turned on, the PMOS transistor MP1 is turned on and, on the other hand, the NMOS transistor MN1 is turned off in accordance with the inversion signal / S = "0", so that the gate of the power semiconductor element Q is charged via the node Ng.

[0164] The electrical resistance value of the charge path at the time of gate charging (so-called gate resistance value) changes in response to the turning on and off of the switches SW1 to SWn in accordance with the number of the resistance elements connected between the node Nm and the node Ng. Specifically, the more the number of the switches SW1 to SWn turned on increases, the more the number of the resistance elements connected in parallel increases, so that the charging speed becomes high due to the decrease in the gate resistance value.

[0165] That is, the gate resistance value at the time of charging is adjusted in accordance with the drive adjustment signals Sp1 to Spn which control the turning on and off of the switches SW1 to SWn, so that the charging speed of the gate can be adjusted.

[0166] On the other hand, when the power semiconductor element Q is turned off, the NMOS transistor MN1 is turned on and, on the other hand, the PMOS transistor MP1 is turned off in accordance with the inversion signal / S = "1", so that the gate of the power semiconductor element Q is discharged via the node Ng.

[0167] The electrical resistance value of the discharge path at the time of gate discharging (so-called gate resistance value) changes in response to the turning on and off of the switches SW1 to SWn in accordance with the number of the resistance elements connected between the node Nm and the node Ng, similarly to the time of gate charging. Specifically, the more the number of the switches SW1 to SWn turned on increases, the more the discharging speed becomes high due to the decrease in the gate resistance value.

[0168] That is, the gate resistance value at the time of discharging is adjusted in accordance with the drive adjustment signals Snl~Snn that control the on / off of the switches SWl~SWn, so that the discharging speed of the gate can be adjusted.

[0169] Thus, with the gate drive circuit 20 of the circuit structure shown in Figure 13 , as well as the circuit structure shown in Figure 4 , the gate charge / discharge speed of the power semiconductor element Q can be adjusted in accordance with the drive adjustment signals Sp1~Spn, Snl~Snn from the characteristic control circuit 21. Further, in the circuit structure of Figure 13 , the circuit design becomes easy, on the other hand, there is a tendency that the circuit scale increases for fine adjustment. In addition, the impedance of the node Ng (gate) becomes high compared to the circuit structure of Figure 4 , so there is a possibility that a negative power supply is required for discharging.

[0170] Figure 14 is a circuit diagram that illustrates a structure of the gate drive circuit 20.

[0171] Referring to Figure 14 , in the second modification example, the gate drive circuit 20 has a PMOS transistor MP1, an NMOS transistor MN1, and a power supply voltage variable circuit 65.

[0172] The PMOS transistor MP1 and the NMOS transistor MN1 are connected in series between the first power supply line VDL and the second power supply line VSL via the node Nm, as in the first modification example of Figure 13 . The inverted signal ( / S) of the control signal S is input to the gates of the PMOS transistor MP1 and the NMOS transistor MN1, as in Figure 13 . A single gate resistance Rg is connected between the node Nm and the node Ng.

[0173] The power supply voltage variable circuit 65 has n power supplies Vddl~Vddn that output different voltages. The power supply voltage variable circuit 65 connects one of the power supplies Vddl~Vddn to the first power supply line VDL in accordance with the drive adjustment signals Sp1~Spn when the inverted signal / S = "0" (during the turn-on of the power semiconductor element Q). On the other hand, the power supply voltage variable circuit 65 connects one of the power supplies Vddl~Vddn to the first power supply line VDL in accordance with the drive adjustment signals Snl~Snn when the inverted signal / S = "1" (during the turn-off of the power semiconductor element Q).

[0174] The charge current and the discharge current change when the power supply voltage supplied from the first power supply line VDL changes. The higher the power supply voltage, the larger the charge current and the discharge current become, so that the charging speed and the discharging speed can be improved.

[0175] Therefore, with the gate drive circuit 20 of the circuit structure shown in Figure 14 adjust the gate charge / discharge speed of the power semiconductor element Q by selecting the power supply Vdd1 to Vddn based on the drive adjustment signals Sp1 to Spn, Sn1 to Snn from the characteristic control circuit 21.

[0176] Further, in the circuit structure of Figure 14 the range of the power supply voltage is difficult to make wide, so there is a tendency that the adjustment range of the charge / discharge speed becomes narrow. In particular, in order to expand the adjustment range of the discharge speed, it is possible that a structure capable of selecting a negative voltage is required to be added also on the side of the 2nd power supply wiring VSL.

[0177] Thus, it can be understood that the gate drive circuit 20 in Embodiments 1 and 2 can apply any circuit structure as long as it can adjust the charge / discharge speed according to the drive adjustment signals Sp1 to Spn, Sn1 to Snn.

[0178] Embodiment 3.

[0179] Figure 15 is a block diagram illustrating a structure example of the power module related to Embodiment 3.

[0180] Referring to Figure 15 the power module 200 related to Embodiment 3 has the drive control device 10 and the power semiconductor element Q which is switch-controlled by the drive control device 10. The drive control device 10 generally represents the drive control device 10A related to Embodiment 1 and the drive control device 10B related to Embodiment 2.

[0181] For example, by providing the drive control device 10 and the power semiconductor element Q as a structure which is integrated with a power supply circuit, a control circuit, a cooling mechanism, and the like not shown in the same package by a sealing material, it is possible to configure the power module 200.

[0182] By the power module integration, it is possible to expect effects such as reduction of the circuit scale of the power conversion system 100, and easiness of adjustment input on the user side.

[0183] Further, in Embodiments 1 to 3, the power semiconductor element Q, which is turned on and off in conjunction with the charge and discharge of the control electrode, can be an element other than an IGBT, such as a MOSFET, a high electron mobility transistor (HEMT), or the like, as long as it is turned on and off by the drive control device of the present embodiment. Also, as to the material of the power semiconductor element, any material, such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN), can be used.

[0184] Further, in the present embodiment, although an example in which the power semiconductor element Q is applied to the three-phase inverter 103 is described, the application of the power semiconductor element, which is turned on and off by the drive control device according to the present embodiment, is not limited to a three-phase inverter, but can be a power converter of an arbitrary circuit structure.

[0185] It should be understood that the embodiments disclosed herein are merely illustrative and not restrictive in all aspects. The technical scope of the present disclosure is not shown by the above description but shown by the claims, and is intended to include all modifications equivalent in meaning and scope to the claims.

[0186] Explanation of Symbols

[0187] 10, 10A, 10B: drive control device; 20: gate drive circuit; 21: characteristic control circuit; 22: classification circuit; 23: counter; 24: register; 25: memory; 26: writing circuit; 27, 27B: selection circuit; 28: current detection section; 29: temperature detection section; 30: current measurement section; 31: temperature measurement section; 60: gate resistance variable circuit; 65: power supply voltage variable circuit; 100: power conversion system; 101: direct current power supply; 102: support capacitor; 103: three-phase inverter; 104: alternating current motor; 200: power module; A1 to A3, B1 to B3, C1 to C3: operation region (power semiconductor element); CLK: clock signal; INext1 to INext3: external input; Ic: main current (collector current); Iq: element current; Ith: current threshold value; MD: mode instruction value; NL, PL: power line; Nu, Nv, Nw: alternating current node; Q, Qun, Qup, Qvn, Qvp, Qwn, Qwp: power semiconductor element; Tq: element temperature; Tth: temperature threshold value; VDL: first power supply wiring; VSL: second power supply wiring.

Claims

1. A drive control device of a power semiconductor element controlled by a switch, comprising: a classification circuit that generates first information for classifying an operation state of the power semiconductor element into one of a plurality of operation regions decided in advance; a characteristic control circuit that adjusts a charging speed of a control electrode of the power semiconductor element in an on operation of the power semiconductor element and a discharging speed of the control electrode in an off operation of the power semiconductor element; a selection circuit that generates second information for selecting one of a plurality of modes in which a switching speed of the power semiconductor element is different; and a gate drive circuit that charges and discharges the control electrode with the charging speed and the discharging speed variably set in accordance with a drive adjustment signal set in accordance with the first information and the second information from the characteristic control circuit.

2. The drive control device of the power semiconductor element according to claim 1, wherein the characteristic control circuit pre-stores the drive adjustment signal for setting the charging speed and the discharging speed for each combination of the plurality of operation regions and the plurality of modes, and outputs the drive adjustment signal in the combination of one of the plurality of operation regions and one of the plurality of modes selected in accordance with the first information and the second information.

3. The drive control device of the power semiconductor element according to claim 1 or 2, wherein the selection circuit generates the second information in a manner that the selection of one of the plurality of modes is fixed to a user instruction at the start of the operation of the power semiconductor element.

4. The drive control device of the power semiconductor element according to claim 1 or 2, wherein the selection circuit generates the second information in a manner that the selection of one of the plurality of modes is switched in accordance with the second information and the operation state at each time point.

5. The drive control device of the power semiconductor element according to claim 1 or 2, wherein the drive control device further comprises: a current measurement circuit that measures a main current of the power semiconductor element; and a temperature measurement circuit that measures a temperature of the power semiconductor element, the classification circuit generates the first information in accordance with a combination of a classification of which current region of a plurality of current regions a device current of the power semiconductor element is and a classification of which temperature region of a plurality of temperature regions a device temperature of the power semiconductor element is, based on measurement values of the current measurement circuit and the temperature measurement circuit.

6. The drive control device of the power semiconductor element according to claim 1 or 2, wherein the characteristic control circuit includes a memory that stores a plurality of the drive adjustment signals corresponding to the plurality of modes respectively, in correspondence with each of the plurality of operation regions.

7. The drive control device of the power semiconductor element according to claim 1 or 2, wherein the characteristic control circuit includes a memory that stores a plurality of the drive adjustment signals corresponding to the plurality of modes respectively, in correspondence with each of the plurality of operation regions, and the selection circuit generates the second information in a manner that the selection of one of the plurality of modes is switched in accordance with the second information and the operation state at each time point.

8. The drive control device of the power semiconductor element according to claim 1 or 2, wherein the characteristic control circuit includes a memory that stores a plurality of the drive adjustment signals corresponding to the plurality of modes respectively, in correspondence with each of the plurality of operation regions, and the selection circuit generates the second information in a manner that the selection of one of the plurality of modes is fixed to a user instruction at the start of the operation of the power semiconductor element. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The drive control device further includes an input circuit configured to rewrite the plurality of drive adjustment signals stored in the memory based on a signal from outside of the drive control device.

7. A power module comprising: the drive control device according to any one of claims 1 to 6; and The power semiconductor element is turned on and off by the drive control device.

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