Differential receiving circuit and interface

Abstract

The present invention provides a differential receiving circuit and interface, comprising: a first-stage amplification module, wherein the first and second amplification units each include an input stage, a common-gate amplification stage, and a common-source amplification stage; the input end of the common-gate amplification stage is connected to the output end of the input stage, and the output end is connected to a power supply voltage via the common-source amplification stage; the input end of the input stage in the first amplification unit is connected to an inverting input signal, and the input end of the common-source amplification stage is connected to a non-inverting input signal; the input end of the input stage in the second amplification unit is connected to a non-inverting input signal, and the input end of the common-source amplification stage is connected to an inverting input signal; the output end of the first amplification unit serves as the inverting output end of the first stage, and the output end of the second amplification unit serves as the non-inverting output end of the first stage; and a second-stage amplification module that performs differential-to-single-ended amplification on the output signal of the first stage. The present invention has the ability to receive low common-mode differential signals, has little impact on the loading effect of the previous stage circuit, has low power consumption, a simple structure, occupies a small area, and has a high receiving rate.

Description

Technical Field

[0001] The present invention relates to the field of signal transmission, and in particular to a differential receiving circuit and interface. Background Art

[0002] Differential signaling and differential amplifier circuits are widely used in analog circuits. Compared to traditional single-ended signaling, which uses a single signal line and a single ground line, differential signaling transmits signals on both transmission lines, with the same amplitude and opposite phase. This offers advantages such as strong anti-interference capabilities, effective EMI suppression, and precise timing positioning, making it widely used in various interface fields.

[0003] Differential receiver circuits have strong suppression capabilities for common-mode input signals, while also amplifying differential-mode signals. The structural characteristics of differential receiver circuits can suppress the effects of changing external conditions, such as temperature noise. Differential receiver circuits are commonly used in interface transmission design and are key modules for determining maximum transmission rates and signal integrity. Requirements for differential receiver circuits include reception rate, common-mode voltage range, and power consumption. In areas such as MIPI (Mobile Industry Processor Interface), the low common-mode voltage reception capability of differential receiver circuits is also a key metric.

[0004] Traditional differential receiver circuits require additional current source branches for biasing, which increases power consumption. Therefore, it is of great significance to design a differential receiver circuit with high reception rate, large common-mode reception range, and low power consumption.

[0005] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a differential receiving circuit and interface for solving the problems of the prior art such as low receiving rate, small common-mode receiving range, and high power consumption of the differential receiving circuit.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a differential receiving circuit, which comprises at least:

[0008] A first-stage amplification module and a second-stage amplification module;

[0009] The first-stage amplification module includes a first amplification unit and a second amplification unit forming a differential structure, and each of the first amplification unit and the second amplification unit includes an input stage, a common-gate amplification stage, and a common-source amplification stage; wherein the input end of the common-gate amplification stage is connected to the output end of the input stage, and the output end is connected to the power supply voltage via the common-source amplification stage; the input end of the input stage in the first amplification unit is connected to an inverting input signal, and the input end of the common-source amplification stage is connected to a non-inverting input signal; the input end of the input stage in the second amplification unit is connected to the non-inverting input signal, and the input end of the common-source amplification stage is connected to the inverting input signal; the connection node of the common-gate amplification stage and the common-source amplification stage in the first amplification unit serves as the inverting output end of the first-stage amplification module, and the connection node of the common-gate amplification stage and the common-source amplification stage in the second amplification unit serves as the non-inverting output end of the first-stage amplification module;

[0010] The second-stage amplifying module is connected to the output end of the first-stage amplifying module and amplifies the output signal of the first-stage amplifying module.

[0011] Optionally, the input stage of the first amplifying unit includes a first NMOS tube, the source of which receives the inverting input signal, the gate is connected to the power supply voltage, and the drain is connected to the common-gate amplifying stage of the first amplifying unit; the input stage of the second amplifying unit includes a second NMOS tube, the source of which receives the positive-phase input signal, the gate is connected to the power supply voltage, and the drain is connected to the common-gate amplifying stage of the second amplifying unit.

[0012] More optionally, the common-gate amplifier stage of the first amplifier unit includes a third NMOS tube, the source of the third NMOS tube is connected to the input stage of the first amplifier unit, the gate is connected to the power supply voltage, and the drain is connected to the common-source amplifier of the first amplifier unit; the common-gate amplifier stage of the second amplifier unit includes a fourth NMOS tube, the source of the fourth NMOS tube is connected to the input stage of the second amplifier unit, the gate is connected to the power supply voltage, and the drain is connected to the common-source amplifier of the second amplifier unit.

[0013] More optionally, the common-source amplifier stage of the first amplifier unit includes a first PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the gate is connected to the positive input signal, and the drain is connected to the common-gate amplifier stage of the first amplifier unit; the common-source amplifier stage of the second amplifier unit includes a second PMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the gate is connected to the negative input signal, and the drain is connected to the common-gate amplifier stage of the second amplifier unit.

[0014] Optionally, the second-stage amplification module is a differential-to-single-ended amplification circuit.

[0015] More optionally, the load of the second-stage amplification module is a current source.

[0016] More optionally, the second-stage amplification module includes a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube and a fourth PMOS tube; the source of the fifth NMOS tube is grounded, the gate is connected to the positive-phase output terminal of the first-stage amplification module, and the drain is connected to the drain and gate of the third PMOS tube; the source of the third PMOS tube is connected to the power supply voltage; the source of the sixth NMOS tube is grounded, the gate is connected to the inverting output terminal of the first-stage amplification module, the drain is connected to the drain of the fourth PMOS tube and serves as the output terminal of the differential receiving circuit; the gate of the fourth PMOS tube is connected to the gate of the third PMOS tube, and the source is connected to the power supply voltage.

[0017] To achieve the above-mentioned object and other related objects, the present invention provides an interface, which at least includes: the above-mentioned differential receiving circuit.

[0018] Optionally, the transmission protocol of the interface is MIPI, USB, Ethernet, PCI-E, SATA, RS485, RS422, HDMI, LVDS or CAN.

[0019] As described above, the differential receiving circuit and interface of the present invention have the following beneficial effects:

[0020] 1. The input signal of the differential receiving circuit of the present invention is input from the source of the NMOS tube, and has the ability to receive low common-mode level differential signals. Theoretically, the common-mode voltage that can be received is as low as 0V.

[0021] 2. The equivalent input resistance of the differential receiving circuit of the present invention can reach tens of KΩ, which has little impact on the loading effect of the previous stage circuit.

[0022] 3. The differential receiving circuit of the present invention is a self-biased structure and does not require an additional current source bias, so the power consumption is reduced compared to the traditional differential receiving circuit structure.

[0023] 4. The differential receiving circuit of the present invention has a simple structure and occupies a small area. It is suitable for high-speed differential signal receiving circuits with low common mode levels and can achieve a relatively high receiving rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of the differential receiving circuit of the present invention.

[0025] Figure 2 Shown is a schematic diagram of a small signal equivalent model of a half-side circuit of the differential receiving circuit of the present invention.

[0026] Component number description

[0027] 1 Differential receiving circuit

[0028] 11. First-stage amplifier module

[0029] 111 First Amplification Unit

[0030] 112 Second amplifier unit

[0031] 12 Second stage amplifier module DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] See also Figures 1 and 2 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0034] like Figure 1 As shown, the present invention provides a differential receiving circuit 1, and the differential receiving circuit 1 includes:

[0035] A first-stage amplifying module 11 and a second-stage amplifying module 12 .

[0036] like Figure 1 As shown, the first-stage amplification module 11 receives an input signal and performs a first-stage amplification on the input signal.

[0037] Specifically, the first-stage amplification module 11 includes a first amplification unit 111 and a second amplification unit 112, and the first amplification unit 111 and the second amplification unit 112 form a differential amplification structure. The first amplification unit 111 and the second amplification unit 112 each include an input stage, a common-gate amplification stage, and a common-source amplification stage; wherein the input end of the common-gate amplification stage is connected to the output end of the input stage, and the output end is connected to the power supply voltage VDD via the common-source amplification stage; the input end of the input stage in the first amplification unit 111 is connected to the inverting input signal VINN, and the input end of the common-source amplification stage is connected to the positive-phase input signal VINP; the input end of the input stage in the second amplification unit 112 is connected to the positive-phase input signal VINP, and the input end of the common-source amplification stage is connected to the inverting input signal VINN; the connection node of the common-gate amplification stage and the common-source amplification stage in the first amplification unit 111 serves as the inverting output end (output voltage V X ), the connection node of the common gate amplifier stage and the common source amplifier stage in the second amplifier unit 112 serves as the positive phase output terminal (output voltage V Y ).

[0038] More specifically, the input stage transmits the input signal to the input of the common-gate amplifier stage, acting as a linear resistor and thereby increasing the input resistance of the differential receiving circuit 1. As an example, the input stage of the first amplifying unit 111 includes a first NMOS transistor M1, and the input stage of the second amplifying unit 112 includes a second NMOS transistor M2. The first NMOS transistor M1 has a source that receives the inverting input signal VINN, a gate that is connected to the power supply voltage VDD, and a drain that is connected to the input of the common-gate amplifier stage of the first amplifying unit 111. The second NMOS transistor M2 has a source that receives the non-inverting input signal VINP, a gate that is connected to the power supply voltage VDD, and a drain that is connected to the input of the common-gate amplifier stage of the second amplifying unit 112. Because the common-mode voltage level of the differential input signals (VINP and VINN) is relatively low, the first NMOS transistor M1 and the second NMOS transistor M2 operate in the linear region and are equivalent to linear resistors. The functions of the input stage include: 1) Since the input signal is input from the source of the first NMOS transistor M1 and the second NMOS transistor M2, it is equivalent to a resistor connected in series in the circuit, which can effectively increase the input resistance of the entire circuit. Considering the influence of the input resistance, the larger the input resistance, the smaller the loading effect, and therefore, the loading effect on the previous stage circuit is relatively small. 2) The input stage is equivalent to a linear resistor, which consumes a portion of the voltage drop through the form of resistor voltage division, thereby increasing the voltage across the common-gate amplifier stage, ensuring that the devices in the common-gate amplifier stage operate in the saturation region and operate as a common-gate amplifier structure. 3) The voltage at the output end of the first-stage amplifier module 11 is increased, resulting in an increase in the gate voltage of the main amplifier tube of the second-stage amplifier module 12 (in this example, the main amplifier tubes in the second-stage amplifier module are the fifth NMOS transistor M7 and the sixth NMOS transistor M8). According to the saturation region current formula, the current flowing through the main amplifier tube increases. Correspondingly, the current of the second-stage amplifier module 12 increases, thereby improving the data conversion rate.

[0039] It should be noted that any circuit structure having a resistance value and capable of transmitting an input signal to the input end of the common-gate amplifier stage is applicable to the input stage of the present invention, including but not limited to a resistor (one end of the resistor receives the input signal and the other end is connected to the input end of the corresponding common-gate amplifier stage), which will not be described in detail here.

[0040] More specifically, the common-gate amplifier stage amplifies the input signal transmitted through the input stage. As an example, the common-gate amplifier stage of the first amplifier unit 111 includes a third NMOS transistor M3, and the common-gate amplifier stage of the second amplifier unit 112 includes a fourth NMOS transistor M4; the source of the third NMOS transistor M3 is connected to the output of the input stage of the first amplifier unit 111 (the drain of the first NMOS transistor M1), the gate is connected to the power supply voltage VDD, and the drain is connected to the output of the common-source amplifier stage of the first amplifier unit 111; the source of the fourth NMOS transistor M4 is connected to the output of the input stage of the second amplifier unit 112 (the drain of the second NMOS transistor M2), the gate is connected to the power supply voltage VDD, and the drain is connected to the output of the common-source amplifier stage of the second amplifier unit 112.

[0041] More specifically, the common-source amplifier stage amplifies the input signal. As an example, the common-source amplifier stage of the first amplifier unit 111 includes a first PMOS transistor M5, and the common-source amplifier stage of the second amplifier unit 112 includes a second PMOS transistor M6. The source of the first PMOS transistor M5 is connected to the power supply voltage VDD, the gate is connected to the positive-phase input signal VINP, and the drain is connected to the output of the common-gate amplifier stage of the first amplifier unit 111 (the drain of the third NMOS transistor M3) and serves as the inverting output of the first-stage amplifier module 11. The source of the second PMOS transistor M6 is connected to the power supply voltage VDD, the gate is connected to the inverting input signal VINN, and the drain is connected to the output of the common-gate amplifier stage of the second amplifier unit 112 (the drain of the fourth NMOS transistor M4) and serves as the non-inverting output of the first-stage amplifier module 11.

[0042] It should be noted that the circuit structures of the common-gate amplifier stage and the common-source amplifier stage can be adaptively adjusted as needed, including but not limited to adding devices to improve performance, and are not limited to this embodiment.

[0043] like Figure 1 As shown, the second-stage amplifying module 12 is connected to the output end of the first-stage amplifying module 11 to amplify the output signal of the first-stage amplifying module 11 .

[0044] Specifically, in this embodiment, the second-stage amplification module 12 is a differential-to-single-ended amplifier circuit. Furthermore, to achieve more stable performance, the load of the second-stage amplification module 12 is a current source. As an example, the second-stage amplification module 12 includes a fifth NMOS transistor M7, a sixth NMOS transistor M8, a third PMOS transistor M9, and a fourth PMOS transistor M10. The source of the fifth NMOS transistor M7 is grounded, its gate is connected to the non-inverting output terminal of the first-stage amplification module 11, and its drain is connected to the drain and gate of the third PMOS transistor M9. The source of the third PMOS transistor M9 is connected to the power supply voltage VDD. The source of the sixth NMOS transistor M8 is grounded, its gate is connected to the inverting output terminal of the first-stage amplification module 11, and its drain is connected to the drain of the fourth PMOS transistor M10, serving as the output terminal OUT of the differential receiving circuit 1. The gate of the fourth PMOS transistor M10 is connected to the gate of the third PMOS transistor M8, and its source is connected to the power supply voltage VDD. The third PMOS transistor M9 and the fourth PMOS transistor M10 form a current mirror structure, with a current source as a load.

[0045] like Figure 1 As shown, the differential receiving circuit 1 of the present invention is a two-stage differential operational amplifier; the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, the first PMOS transistor M5, and the second PMOS transistor M6 form a first-stage differential amplifier structure, wherein the first NMOS transistor M1 and the second NMOS transistor M2 are equivalent to linear resistors, the third NMOS transistor M3 and the fourth NMOS transistor M4 form a common-gate amplifier stage, and the first PMOS transistor M5 and the second PMOS transistor M6 form a common-source amplifier stage; the fifth NMOS transistor M7, the sixth NMOS transistor M8, the third PMOS transistor M9, and the fourth PMOS transistor M10 form a second-stage differential amplifier structure. The output resistance of the positive-phase output terminal and the negative-phase output terminal of the first-stage amplifier module 11 satisfies:

[0046] g m3 r o3 r on1 / / r o5 ,

[0047] Among them, g m3 is the transconductance of the third NMOS tube M3, r o3 is the internal resistance of the third NMOS tube M3, r o5 is the internal resistance of the first PMOS tube M5, r on1 is the equivalent resistance of the first NMOS tube M1; therefore, the voltage gain V x / V INN =A v1satisfy:

[0048] A v1 =-(g m3 +g m5 )(g m3 r o3 r on1 / / r o5 );

[0049] Among them, g m5 The voltage gain of the first-stage amplifying module can also be analyzed based on the second amplifying unit 112, which will not be described in detail here.

[0050] The voltage gain V of the second stage amplifier module OUT / V x =A v2 satisfy:

[0051] A v2 =-g m8 (r o8 / / r o10 );

[0052] Among them, g m8 is the transconductance of the sixth NMOS tube M8, r o8 is the internal resistance of the sixth NMOS tube M8, r o10 is the internal resistance of the fourth PMOS transistor M10.

[0053] The total voltage gain of the differential receiving circuit 1 is:

[0054] A v2 =V OUT / V INN =A v1 A v2 .

[0055] like Figure 2 The figure shows the small signal equivalent model of the half-side circuit of the differential receiving circuit 1 of the present invention. The small signal equivalent model analysis of the input resistance is performed, and the input impedance can be expressed by V T / i T The expression is calculated to satisfy:

[0056] V sg5 =-V T ;

[0057] V gs3 =i T r on1 -V T ;

[0058] i T =g m5 Vsg5 +V X / r o5 ;

[0059] i T =-g m3 V gs3 +(V T -i T r on1 -V X ) / r o3 ;

[0060] Among them, V T The input voltage source for input resistance measurement, i T is the equivalent input current, V sg5 is the source-gate voltage of the first PMOS tube M5, V gs3 is the gate-source voltage of the third NMOS transistor M3.

[0061] From this we can deduce that the input resistance satisfies:

[0062]

[0063] It can be seen from the above calculation that the equivalent input resistance of the differential receiving circuit 1 of the present invention can reach more than tens of KΩ.

[0064] The differential receiving circuit 1 of the present invention can receive differential signals with lower common-mode levels, and the common-mode receiving range is improved; there is no additional current bias branch, low power consumption; high conversion rate; simple structure, small occupied area; large input resistance, and little impact on the loading effect of the previous circuit.

[0065] The present invention further provides an interface, which includes at least the differential receiving circuit 1. As an example, the transmission protocol of the interface includes but is not limited to MIPI, USB, Ethernet, PCI-E, SATA, RS485, RS422, HDMI, LVDS or CAN. Any differential signal interface transmitted through a low common mode voltage is applicable to the present invention and will not be described in detail here.

[0066] In summary, the present invention provides a differential receiving circuit and interface, comprising: a first-stage amplification module and a second-stage amplification module; the first-stage amplification module includes a first amplification unit and a second amplification unit forming a differential structure, and the first amplification unit and the second amplification unit both include an input stage, a common-gate amplification stage, and a common-source amplification stage; wherein the input end of the common-gate amplification stage is connected to the output end of the input stage, and the output end is connected to the power supply voltage via the common-source amplification stage; the input end of the input stage in the first amplification unit is connected to the inverting input signal, and the input end of the common-source amplification stage is connected to the positive-phase input signal; the input end of the input stage in the second amplification unit is connected to the positive-phase input signal, and the input end of the common-source amplification stage is connected to the inverting input signal; the connection node of the common-gate amplification stage and the common-source amplification stage in the first amplification unit serves as the inverting output end of the first-stage amplification module, and the connection node of the common-gate amplification stage and the common-source amplification stage in the second amplification unit serves as the positive-phase output end of the first-stage amplification module; the second-stage amplification module is connected to the output end of the first-stage amplification module to amplify the output signal of the first-stage amplification module. The differential receiver circuit of the present invention receives input signals from the source of an NMOS transistor, enabling it to receive differential signals with low common-mode levels. Its equivalent input resistance can reach tens of kilo-ohms, minimizing the loading effect on the preceding circuit. Its self-biasing structure eliminates the need for an additional current source bias, resulting in lower power consumption compared to traditional differential receiver circuits. Its simple structure and small footprint make it suitable for high-speed differential signal receiver circuits with low common-mode levels, while also achieving a high reception rate. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A differential receiving circuit, characterized in that: The differential receiving circuit at least includes: A first-stage amplification module and a second-stage amplification module; The first-stage amplification module includes a first amplification unit and a second amplification unit forming a differential structure. The first amplification unit and the second amplification unit each include an input stage, a common-gate amplification stage, and a common-source amplification stage. The input end of the common-gate amplification stage is connected to the output end of the input stage, and the output end of the common-gate amplification stage is connected to the power supply voltage via the common-source amplification stage. The input end of the input stage in the first amplification unit is connected to the inverting input signal, and the input end of the common-source amplification stage is connected to the non-inverting input signal. The input end of the input stage in the second amplification unit is connected to the non-inverting input signal, and the input end of the common-source amplification stage is connected to the inverting input signal. The common-gate amplification stage in the first amplification unit is connected to the output end of the input stage, and the output end of the common-source amplification stage is connected to the power supply voltage via the common-source amplification stage. The connection node of the amplifier stage and the common-source amplifier stage serves as the inverting output terminal of the first-stage amplifier module, and the connection node of the common-gate amplifier stage and the common-source amplifier stage in the second amplifier unit serves as the non-inverting output terminal of the first-stage amplifier module; wherein the input stage of the first amplifier unit includes a first NMOS transistor, the source of the first NMOS transistor receives the inverting input signal, the gate is connected to the power supply voltage, and the drain is connected to the common-gate amplifier stage of the first amplifier unit; the input stage of the second amplifier unit includes a second NMOS transistor, the source of the second NMOS transistor receives the non-inverting input signal, the gate is connected to the power supply voltage, and the drain is connected to the common-gate amplifier stage of the second amplifier unit; The second-stage amplifying module is connected to the output end of the first-stage amplifying module and amplifies the output signal of the first-stage amplifying module.

2. The differential receiving circuit according to claim 1, wherein: The common-gate amplifier stage of the first amplifier unit includes a third NMOS tube, the source of the third NMOS tube is connected to the input stage of the first amplifier unit, the gate is connected to the power supply voltage, and the drain is connected to the common-source amplifier of the first amplifier unit; the common-gate amplifier stage of the second amplifier unit includes a fourth NMOS tube, the source of the fourth NMOS tube is connected to the input stage of the second amplifier unit, the gate is connected to the power supply voltage, and the drain is connected to the common-source amplifier of the second amplifier unit.

3. The differential receiving circuit according to claim 2, wherein: The common-source amplifier stage of the first amplifier unit includes a first PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the gate is connected to the positive input signal, and the drain is connected to the common-gate amplifier stage of the first amplifier unit; the common-source amplifier stage of the second amplifier unit includes a second PMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the gate is connected to the negative input signal, and the drain is connected to the common-gate amplifier stage of the second amplifier unit.

4. The differential receiving circuit according to claim 1, wherein: The second-stage amplifier module is a differential-to-single-ended amplifier circuit.

5. The differential receiving circuit according to claim 1 or 4, wherein: The load of the second-stage amplification module is a current source.

6. The differential receiving circuit according to claim 5, wherein: The second-stage amplification module includes a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor; the source of the fifth NMOS transistor is grounded, the gate is connected to the non-inverting output terminal of the first-stage amplification module, and the drain is connected to the drain and gate of the third PMOS transistor; the source of the third PMOS transistor is connected to the power supply voltage; the source of the sixth NMOS transistor is grounded, the gate is connected to the inverting output terminal of the first-stage amplification module, the drain is connected to the drain of the fourth PMOS transistor and serves as the output terminal of the differential receiving circuit; the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor, and the source is connected to the power supply voltage.

7. An interface, characterized in that: The interface at least includes the differential receiving circuit according to any one of claims 1-6.

8. The interface according to claim 7, characterized in that: The transmission protocol of the interface is MIPI, USB, Ethernet, PCI-E, SATA, RS485, RS422, HDMI, LVDS or CAN.

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