Electrostatic protection circuit of the chip

Abstract

The present application provides an electrostatic protection circuit for a chip. The chip includes a power pad and a ground pad. The electrostatic protection circuit includes: a monitoring unit for generating a trigger signal when there is an electrostatic pulse on the power pad; a first discharge transistor located between the power pad and the ground pad, which is used to conduct under the control of the trigger signal when operating in the discharge mode to discharge the electrostatic charge to the ground pad; a first control unit connected to the first discharge transistor for switching the operating mode of the first discharge transistor; a second discharge transistor located between the power pad and the ground pad, which is used to conduct under the control of the trigger signal when operating in the discharge mode to discharge the electrostatic charge to the ground pad; and a second control unit connected to the second discharge transistor for switching the operating mode of the second discharge transistor. This solution provides an electrostatic protection circuit with adjustable electrostatic protection ability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to an electrostatic protection circuit for a chip. Background Art

[0002] Electrostatic charges are everywhere. Without an electrostatic protection circuit, a chip will soon be damaged by electrostatic charges introduced for various reasons and will almost be fatally damaged.

[0003] Therefore, an electrostatic protection circuit is usually provided in a chip. The electrostatic protection circuit is used to timely discharge electrostatic charges and prevent the protected circuit from failing or even burning out due to the high voltage brought by the electrostatic charges. Summary of the Invention

[0004] This application provides an electrostatic protection circuit for a chip, aiming to provide an electrostatic protection circuit with adjustable electrostatic protection ability.

[0005] This application provides an electrostatic protection circuit for a chip. The chip includes a power pad and a ground pad. The electrostatic protection circuit includes:

[0006] A monitoring unit, configured to generate a trigger signal when there is an electrostatic pulse on the power pad;

[0007] A first discharge transistor, located between the power pad and the ground pad, configured to conduct under the control of the trigger signal when operating in the discharge mode to discharge the electrostatic charge to the ground pad;

[0008] A first control unit, connected to the first discharge transistor, configured to switch the operating mode of the first discharge transistor; wherein, the operating mode includes the discharge mode;

[0009] A second discharge transistor, located between the power pad and the ground pad, configured to conduct under the control of the trigger signal when operating in the discharge mode to discharge the electrostatic charge to the ground pad;

[0010] A second control unit, connected to the second discharge transistor, configured to switch the operating mode of the second discharge transistor; wherein, the operating mode includes the discharge mode.

[0011] In one embodiment, the electrostatic protection circuit further includes:

[0012] A third discharge transistor, located between the power pad and the ground pad, configured to conduct under the control of the trigger signal when operating in the discharge mode to discharge the electrostatic charge to the ground pad;

[0013] A third control unit, connected to the third discharge transistor, configured to switch the operating mode of the third discharge transistor; wherein, the operating mode includes the discharge mode.

[0014] In one embodiment,

[0015] The first discharge transistor is further configured to be in a cut-off state when operating in a bypass mode;

[0016] The second discharge transistor is further configured to be in a cut-off state when operating in a bypass mode;

[0017] The third discharge transistor is further configured to be in a cut-off state when operating in a bypass mode.

[0018] In one embodiment, the sizes of the first discharge transistor, the second discharge transistor, and the third discharge transistor form an arithmetic sequence, a geometric sequence, or are equal.

[0019] In one embodiment, the aspect ratios of the first discharge transistor, the second discharge transistor, and the third discharge transistor form an arithmetic sequence, a geometric sequence, or are equal.

[0020] In one embodiment, the first discharge transistor, the second discharge transistor, and the third discharge transistor are of the same type.

[0021] In one embodiment,

[0022] The first control unit is connected to the monitoring unit and is also connected to the control terminal of the first discharge transistor;

[0023] The second control unit is connected to the monitoring unit and is also connected to the control terminal of the second discharge transistor.

[0024] In one embodiment, the first control unit includes:

[0025] A first switch, whose first end is connected to the control terminal of the corresponding discharge transistor, and whose second end is connected to the monitoring unit;

[0026] A second switch, whose first end is connected to the control terminal of the corresponding discharge transistor, and whose second end is connected to the monitoring unit.

[0027] In one embodiment, the first switch and the second switch are one-time programmable memories.

[0028] In one embodiment, the first switch and the second switch are laser fuse devices.

[0029] In one embodiment, the monitoring unit includes:

[0030] A monitoring resistor, whose first end is connected to the power supply pad, and whose first end is also connected to the second end of the second switch;

[0031] A monitoring capacitor, whose first end is connected to the second end of the monitoring resistor and then connected to the second end of the first switch, and whose second end is connected to the ground pad.

[0032] In one embodiment, if the first discharge transistor is a P-type transistor, the first switch is in a non-fused state, the second switch is in a fused state, and the first discharge transistor is in a discharge mode;

[0033] If the first discharge transistor is a P-type transistor, the first switch is in a fused state, the second switch is in a non-fused state, and the first discharge transistor is in a bypass mode.

[0034] In one embodiment, the monitoring unit includes:

[0035] A monitoring capacitor, whose first end is connected to the power pad,

[0036] A monitoring resistor, whose first end is connected to the second end of the monitoring capacitor and then to the second end of the first switch, and whose second end is connected to the ground pad and is also connected to the second end of the second switch.

[0037] In one embodiment,

[0038] If the first discharge transistor is an N-type transistor, the first switch is in a non-fused state, the second switch is in a fused state, and the first discharge transistor is in a discharge mode;

[0039] If the first discharge transistor is an N-type transistor, the first switch is in a fused state, the second switch is in a non-fused state, the first discharge transistor is in a bypass mode.

[0040] In one embodiment,

[0041] The third control unit is connected to the monitoring unit and is also connected to the control end of the third discharge transistor.

[0042] This application provides an electrostatic protection circuit for a chip. The electrostatic protection circuit includes a monitoring unit, a first discharge transistor, a second discharge transistor, a first control unit, and a second control unit. Among them, the monitoring unit is used to monitor the electrostatic charge on the power pad and generate a trigger signal when there is electrostatic charge on the power pad. Both the first discharge transistor and the second discharge transistor are used to conduct under the control of the trigger signal when operating in the discharge mode to discharge the electrostatic charge on the power pad to the ground pad. The first control unit is used to switch the working mode of the first discharge transistor, and the second control unit is used to switch the working mode of the second discharge transistor. By fabricating multiple chips in one wafer, dividing the chips into multiple groups, setting the working modes of the two discharge transistors through the first control unit and the second control unit, so as to set the number of discharge transistors in the discharge mode, to obtain electrostatic protection circuits with different electrostatic protection capabilities, and then using the set chips for testing to determine the electrostatic protection circuit with the optimal electrostatic protection capability, without multiple wafer fabrications, reducing the cost of electrostatic protection testing and simplifying the electrostatic protection testing process of the chip. Description of the Drawings

[0043] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0044] Figure 1 The specific circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of this application;

[0045] Figure 2 The structural block diagram of the electrostatic protection circuit of the chip provided by an embodiment of this application;

[0046] Figure 3 The specific circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of this application;

[0047] Figure 4 The specific circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of this application.

[0048] Through the above-mentioned accompanying drawings, the clear embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These accompanying drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. Specific Embodiments

[0049] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different accompanying drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0050] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other implementation schemes of this application. This application is intended to cover any variations, uses, or adaptive changes of this application, which follow the general principles of this application and include the common general knowledge or conventional technical means in the technical field not disclosed in this application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of this application are pointed out by the following claims.

[0051] Figure 1 An electrostatic protection circuit for a chip provided by an embodiment of this application, the chip includes a power supply pad VDD and a ground pad VSS. The electrostatic protection circuit includes a monitoring unit 101 and a discharge transistor 102. Among them, the monitoring unit 101 is located between the power supply pad and the ground pad, and the monitoring unit 101 is connected to the control end of the discharge transistor.

[0052] The monitoring unit 101 is used to generate a trigger signal when there is an electrostatic pulse on the power supply pad VDD. The trigger signal is used to control the conduction of the discharge transistor 102, so as to timely discharge the electrostatic charge on the power supply pad VDD to the ground pad VSS.

[0053] In one embodiment, the discharge transistor 101 is an N-type transistor. The monitoring unit 101 includes a monitoring capacitor C1 and a monitoring resistor R1. The first end of the monitoring capacitor C1 is connected to the power supply pad VDD, the second end of the monitoring resistor R1 is connected to the ground pad VSS, and the second end of the monitoring capacitor C1 is connected to the first end of the monitoring resistor R1 and then connected to the driving unit 101.

[0054] When there is an electrostatic pulse on the power supply pad VDD, the equivalent impedance of the monitoring capacitor C1 drops sharply, the voltage at the first end of the monitoring resistor R1 is pulled up, and the discharge transistor 102 conducts.

[0055] Among them, the size of the discharge transistor 102 will affect the electrostatic protection ability of the electrostatic protection circuit, and appropriate values need to be determined through multiple tests. In addition, Figure 1 The shown electrostatic protection circuit usually needs to be co-fabricated with the internal circuit of the chip to test the electrostatic protection level of the chip. If it is found that the electrostatic protection ability of the chip is relatively weak, it is necessary to redesign the size of the discharge transistor and then test the electrostatic protection ability of the chip after co-fabrication.

[0056] However, the cost of chip co-fabrication is expensive. If it is found that the electrostatic protection ability of the chip is relatively weak, it is necessary to redesign the size of the discharge transistor and then test it after re-co-fabrication. The test process is complex and the test cost is relatively high.

[0057] This application provides an electrostatic protection circuit for a chip, aiming to reduce the test cost of the electrostatic protection of the chip. The technical concept of this application is: setting a plurality of discharge transistors and a control unit for switching the working mode of the discharge transistors in the electrostatic protection circuit. Before the electrostatic protection ability of the electrostatic protection circuit is tested, by setting the number of discharge transistors in the discharge mode in the electrostatic protection circuit, the discharge ability of the electrostatic protection circuit is set, so as to realize setting the electrostatic protection ability of the electrostatic protection circuit. By fabricating multiple chips through one co-fabrication, setting the electrostatic protection ability of the electrostatic protection circuit according to the test requirements, and obtaining multiple electrostatic protection circuits with different electrostatic protection abilities, without multiple co-fabrications, the cost of electrostatic protection testing is reduced, and the electrostatic protection testing process of the chip is simplified.

[0058] Such as Figure 2As shown, the present application provides an electrostatic protection circuit for a chip. The chip includes a power supply pad VDD and a ground pad VSS. The electrostatic protection circuit includes a monitoring unit 201, a first discharge transistor 2031, a second discharge transistor 2032, a first control unit 2021, and a second control unit 2022.

[0059] Among them, the monitoring unit 201 is connected between the power supply pad VDD and the ground pad VSS. Both the first discharge transistor 2031 and the second discharge transistor 2032 are located between the power supply pad VDD and the ground pad VSS. The first control unit 2021 is connected to the first discharge transistor 2031, and the second control unit 2022 is connected to the second discharge transistor 2032.

[0060] The monitoring unit 201 is used to generate a trigger signal when there is an electrostatic pulse on the power supply pad VDD. The operating modes of the first discharge transistor 2031 include a discharge mode and a bypass mode. When the first discharge transistor 2031 operates in the discharge mode, it conducts under the control of the trigger signal to discharge the electrostatic charge to the ground pad VSS. When the first discharge transistor 2031 operates in the bypass mode, it is in the cut-off state, and the first discharge transistor 2031 cannot discharge the electrostatic charge to the ground pad VSS. The first control unit 2021 is used to switch the operating mode of the first discharge transistor 2031. When the first control unit 2021 receives a certain setting signal, it causes the first discharge transistor 2031 to switch from the bypass mode to the discharge mode, or from the discharge mode to the bypass mode.

[0061] The operating modes of the second discharge transistor 2032 include a discharge mode and a bypass mode. When the second discharge transistor 2032 operates in the discharge mode, it conducts under the control of the trigger signal to discharge the electrostatic charge to the ground pad VSS. When the second discharge transistor 2032 operates in the bypass mode, it is in the cut-off state, and the second discharge transistor 2032 cannot discharge the electrostatic charge to the ground pad VSS. The second control unit 2022 is used to switch the operating mode of the second discharge transistor 2032. When the second control unit 2022 receives a certain setting signal, it causes the second discharge transistor 2032 to switch from the bypass mode to the discharge mode, or from the discharge mode to the bypass mode.

[0062] The number of discharge transistors operating in the discharge mode affects the electrostatic protection ability of the electrostatic protection circuit. By fabricating multiple chips in one wafer, the chips are divided into multiple groups. Before the electrostatic test, by setting the operating states of the first control unit 2021 and the second control unit 2022, the operating modes of the first discharge transistor 2031 and the second discharge transistor 2032 are set, so that the number of discharge transistors operating in the discharge mode in each group of chips is different, and the discharge capabilities of each group of chips are also different. Then, the chips after setting are used for testing, and the electrostatic protection circuit with the optimal electrostatic protection ability is selected from them. Without multiple wafer runs, the cost of electrostatic protection testing can be reduced, and the electrostatic protection testing process of the chip can be simplified.

[0063] In one embodiment, the electrostatic protection circuit further includes a third discharge transistor 2033 and a third control unit 2023. The operating mode of the third discharge transistor 2033 includes a discharge mode and a bypass mode. When the third discharge transistor 2033 operates in the discharge mode, it conducts under the control of a trigger signal to discharge the electrostatic charge to the ground pad VSS. When the third discharge transistor 2033 operates in the bypass mode, it is in the cut-off state, and the third discharge transistor 2033 cannot discharge the electrostatic charge to the ground pad VSS. The third control unit 2023 is used to switch the operating mode of the third discharge transistor 2033. When the third control unit 2023 receives a certain setting signal, the third discharge transistor 2033 is switched from the bypass mode to the discharge mode, or from the discharge mode to the bypass mode.

[0064] In one embodiment, the sizes of the first discharge transistor 2031, the second discharge transistor 2032, and the third discharge transistor 2033 form an arithmetic sequence, a geometric sequence, or are equal.

[0065] When the three discharge transistors form an arithmetic sequence, the discharge currents of the three discharge transistors also form an arithmetic sequence accordingly. When the three discharge transistors form a geometric sequence, the discharge currents of the three discharge transistors also form a geometric sequence accordingly. When the three discharge transistors are equal, the discharge currents of the three discharge transistors are also equal. By arbitrarily combining the discharge modes of the three discharge transistors, electrostatic protection circuits with various electrostatic protection capabilities can be obtained, thereby increasing the setting range of the electrostatic protection ability of the electrostatic protection circuit.

[0066] In one embodiment, the aspect ratios of the first discharge transistor 2031, the second discharge transistor 2032, and the third discharge transistor 2033 form an arithmetic sequence, a geometric sequence, or are equal.

[0067] The discharge transistor uses an interdigital structure. For example, there are 36 interdigital structures, which are divided into 3 groups, with 12 interdigital structures in each group. The first group of interdigital structures forms the first discharge transistor 2031, the second group of interdigital structures forms the second discharge transistor 2032, and the third group of interdigital structures forms the third discharge transistor 2033, so that the aspect ratios of the three discharge transistors are equal.

[0068] In one embodiment, the first discharge transistor 2031, the second discharge transistor 2032, and the third discharge transistor 2033 are of the same type.

[0069] In one embodiment, the first control unit 2021 is connected to the monitoring unit 201, and the first control unit 2021 is also connected to the control terminal of the first discharge transistor 2031. The first control unit 2021 controls the path between the monitoring unit 201 and the first discharge transistor 2031. When the first control unit 2021 enables the first discharge transistor 2031 to receive a trigger signal, the first discharge transistor 2031 operates in the discharge mode. When the first control unit 2021 enables the first discharge transistor 2031 not to receive a trigger signal, the first discharge transistor 2031 operates in the bypass mode.

[0070] The second control unit 2022 is connected to the monitoring unit 201, and the second control unit 2022 is also connected to the control terminal of the second discharge transistor 2032. The second control unit 2022 controls the path between the monitoring unit 201 and the second discharge transistor 2032. When the second control unit 2022 enables the second discharge transistor 2032 to receive a trigger signal, the second discharge transistor 2032 operates in the discharge mode. When the second control unit 2022 enables the second discharge transistor 2032 not to receive a trigger signal, the second discharge transistor 2032 operates in the bypass mode.

[0071] The third control unit 2023 is connected to the monitoring unit 201, and the third control unit 2023 is also connected to the control terminal of the third discharge transistor 2033. The third control unit 2023 controls the path between the monitoring unit 201 and the third discharge transistor 2033. When the third control unit 2023 enables the third discharge transistor 2033 to receive a trigger signal, the third discharge transistor 2033 operates in the discharge mode. When the third control unit 2023 enables the third discharge transistor 2033 not to receive a trigger signal, the third discharge transistor 2033 operates in the bypass mode.

[0072] In one embodiment, the electrostatic protection circuit may further include a fourth discharge transistor, ……, an Nth discharge transistor, and further includes a fourth control unit, ……, an Nth control unit. The fourth control unit is connected to the monitoring unit 201, and the fourth control unit is further connected to the control terminal of the fourth discharge transistor. ……. The Nth control unit is connected to the monitoring unit 201, and the Nth control unit is further connected to the control terminal of the Nth discharge transistor. By setting the operating state of the signal setting control unit, the number of discharge transistors in the electrostatic protection circuit in the discharge mode is set to achieve adaptation to a wider range of discharge capabilities.

[0073] In one embodiment, the first control unit 2021 includes a first switch and a second switch. Both the first switch and the second switch are provided with a first end and a second end. The first end of the first switch is connected to the control terminal of the first discharge transistor 2031, and the second end of the first switch is connected to the monitoring unit 201. The first end of the second switch is connected to the control terminal of the first discharge transistor 2031, and the second end of the second switch is connected to the monitoring unit 201. By setting the signals, the states of the first switch and the second switch are set to achieve switching of the operating mode of the first discharge transistor 2031.

[0074] In the above technical solution, the electrostatic protection circuit includes a plurality of discharge transistors and a plurality of control units. After manufacturing a plurality of chips in one chip fabrication, the number of discharge transistors in the electrostatic protection circuit in the discharge mode can be set, so as to obtain an electrostatic protection circuit with different electrostatic protection capabilities, and then use the set electrostatic protection circuit for testing to obtain the structure of the optimal electrostatic protection circuit and reduce the testing cost.

[0075] As Figure 3 shown, an embodiment of the present application provides an electrostatic protection circuit for a chip. The electrostatic protection circuit includes a monitoring unit 201, a first discharge transistor P1, a second discharge transistor P2, a third discharge transistor P3, a first control unit 2021, a second control unit 2022, and a third control unit 2023.

[0076] The monitoring unit 201 includes a monitoring resistor R1 and a monitoring capacitor C1. Both the monitoring resistor R1 and the monitoring capacitor C1 are provided with a first end and a second end. The first end of the monitoring resistor R1 is connected to the power supply pad VDD, and the second end of the monitoring resistor R1 and the first end of the monitoring capacitor C1 are connected and used as the output terminal of the monitoring unit 201. The second end of the monitoring capacitor C1 is connected to the ground pad VSS.

[0077] The first control unit 2021 includes a first switch K1 and a second switch K2. Both the first switch K1 and the second switch K2 are provided with a first end and a second end. The first end of the first switch K1 is connected to the control end of the first discharge transistor P1, and the second end of the first switch K1 is connected to the second end of the monitoring resistor R1. The first end of the second switch K2 is connected to the control end of the first discharge transistor P1, and the second end of the second switch K2 is connected to the power supply pad VDD.

[0078] The second control unit 2022 includes a third switch K3 and a fourth switch K4. Both the third switch K3 and the fourth switch K4 are provided with a first end and a second end. The first end of the third switch K3 is connected to the control end of the second discharge transistor P2, and the second end of the third switch K3 is connected to the second end of the monitoring resistor R1. The first end of the fourth switch K4 is connected to the control end of the second discharge transistor P2, and the second end of the fourth switch K4 is connected to the power supply pad VDD.

[0079] The third control unit 2023 includes a fifth switch K5 and a sixth switch K6. Both the fifth switch K5 and the sixth switch K6 are provided with a first end and a second end. The first end of the fifth switch K5 is connected to the control end of the third discharge transistor P3, and the second end of the fifth switch K5 is connected to the second end of the monitoring resistor R1. The first end of the sixth switch K6 is connected to the control end of the third discharge transistor P3, and the second end of the sixth switch K6 is connected to the power supply pad VDD.

[0080] The first discharge transistor P1, the second discharge transistor P2, and the third discharge transistor P3 are all P-type transistors.

[0081] The first switch K1 is in a non-fused state, the second switch K2 is in a fused state, and the first discharge transistor P1 is in a discharge mode. The first switch K1 is in a fused state, the second switch K2 is in a non-fused state, and the first discharge transistor P1 is in a bypass mode.

[0082] The connection state between the first discharge transistor P1 and the monitoring unit 201 is set by the first switch K1, and the connection relationship between the first discharge transistor P1 and the power supply pad VDD is set by the second switch K2. When the first switch K1 is fused and the second switch K2 is non-fused, the first discharge transistor P1 is in a cut-off state, and the second switch K2 connects the control end of the first discharge transistor P1 to the power supply pad to prevent the control end of the first discharge transistor P1 from being floating and introducing interference.

[0083] The third switch K3 is in a non-fused state, the fourth switch K4 is in a fused state, and the first discharge transistor P1 is in a discharge mode. The third switch K3 is in a fused state, the fourth switch K4 is in a non-fused state, and the first discharge transistor P1 is in a bypass mode.

[0084] The fifth switch K5 is in a non-fused state, the sixth switch K6 is in a fused state, and the first discharge transistor P1 is in a discharge mode. The fifth switch K5 is in a fused state, the sixth switch K6 is in a non-fused state, and the first discharge transistor P1 is in a bypass mode.

[0085] In one embodiment, the first switch K1 to the sixth switch K6 are one-time programmable memories.

[0086] In one embodiment, the first switch K1 to the sixth switch K6 are laser fuse devices.

[0087] By performing fuse processing on the corresponding switches, the operating modes of the first discharge transistor P1, the second discharge transistor P2, and the third discharge transistor P3 are set.

[0088] For example: Fusing the first switch K1, the fourth switch K4, and the sixth switch K6 means that the control terminal of the first discharge transistor P1 is connected to the power supply pad VDD, the first discharge transistor P1 is in the cut-off state, the control terminals of the second discharge transistor P2 and the third discharge transistor P3 are connected to the second end of the monitoring resistor R1. When there is static charge on the power supply pad VDD, the equivalent impedance of the monitoring capacitor C1 drops sharply, the control terminals of the second discharge transistor P2 and the third discharge transistor P3 are pulled to a low level, and the second discharge transistor P2 and the third discharge transistor P3 conduct to discharge the static charge in a timely manner.

[0089] In the above technical solution, the electrostatic protection circuit includes a plurality of discharge transistors and a plurality of control units, and each control unit includes two laser fuse devices. After manufacturing multiple chips in one chip fabrication run, fuse processing is performed on the corresponding laser fuse devices to set the number of discharge transistors in the electrostatic protection circuit in the discharge mode, so as to obtain electrostatic protection circuits with different electrostatic protection capabilities. Then, the set electrostatic protection circuits are used for testing to obtain the optimal structure of the electrostatic protection circuit and reduce the testing cost.

[0090] As Figure 4 shown, an embodiment of the present application provides an electrostatic protection circuit for a chip. The electrostatic protection circuit includes a monitoring unit 201, a first discharge transistor N1, a second discharge transistor N2, a third discharge transistor N3, a first control unit 2021, a second control unit 2022, and a third control unit 2023.

[0091] The monitoring unit 201 includes a monitoring capacitor C1 and a monitoring resistor R1. Both the monitoring capacitor C1 and the monitoring resistor R1 are provided with a first end and a second end. The first end of the monitoring capacitor C1 is connected to the power supply pad, and the second end of the monitoring capacitor C1 and the first end of the monitoring resistor R1 are connected as the output end of the monitoring unit 201. The second end of the monitoring resistor R1 is connected to the ground pad.

[0092] The first control unit 2021 includes a first switch K1 and a second switch K2. Both the first switch K1 and the second switch K2 are provided with a first end and a second end. The first end of the first switch K1 is connected to the control end of the first discharge transistor N1, and the second end of the first switch K1 is connected to the first end of the monitoring resistor R1. The first end of the second switch K2 is connected to the control end of the first discharge transistor N1, and the second end of the second switch K2 is connected to the ground pad.

[0093] The second control unit 2022 includes a third switch K3 and a fourth switch K4. Both the third switch K3 and the fourth switch K4 are provided with a first end and a second end. The first end of the third switch K3 is connected to the control end of the second discharge transistor N2, and the second end of the third switch K3 is connected to the first end of the monitoring resistor R1. The first end of the fourth switch K4 is connected to the control end of the second discharge transistor N2, and the second end of the fourth switch K4 is connected to the ground pad.

[0094] The third control unit 2023 includes a fifth switch K5 and a sixth switch K6. Both the fifth switch K5 and the sixth switch K6 are provided with a first end and a second end. The first end of the fifth switch K5 is connected to the control end of the third discharge transistor N3, and the second end of the fifth switch K5 is connected to the first end of the monitoring resistor R1. The first end of the sixth switch K6 is connected to the control end of the third discharge transistor N3, and the second end of the sixth switch K6 is connected to the ground pad.

[0095] The first discharge transistor N1, the second discharge transistor N2, and the third discharge transistor N3 are all N-type transistors.

[0096] When the first switch K1 is in the non-fused state, the second switch K2 is in the fused state, and the first discharge transistor N1 is in the discharge mode. When the first switch K1 is in the fused state, the second switch K2 is in the non-fused state, and the first discharge transistor N1 is in the bypass mode.

[0097] When the third switch K3 is in the non-fused state, the fourth switch K4 is in the fused state, and the first discharge transistor N1 is in the discharge mode. When the third switch K3 is in the fused state, the fourth switch K4 is in the non-fused state, and the first discharge transistor N1 is in the bypass mode.

[0098] When the fifth switch K5 is in the non-fused state, the sixth switch K6 is in the fused state, and the first discharge transistor N1 is in the discharge mode. When the fifth switch K5 is in the fused state, the sixth switch K6 is in the non-fused state, and the first discharge transistor N1 is in the bypass mode.

[0099] In one embodiment, the first switch K1 to the sixth switch K6 are one-time programmable memories.

[0100] In one embodiment, the first switch K1 to the sixth switch K6 are laser fuse devices.

[0101] By performing fuse processing on the corresponding switches, the operating modes of the first discharge transistor N1, the second discharge transistor N2, and the third discharge transistor N3 are set.

[0102] For example: Fuse the second switch K2, the third switch K3, and the sixth switch K6. That is, the control terminal of the second discharge transistor N2 is connected to the ground pad, and the second discharge transistor N2 is in the cut-off state. The control terminals of the first discharge transistor N1 and the third discharge transistor N3 are connected to the first end of the monitoring resistor R1. When there is static charge on the ground pad, the equivalent impedance of the monitoring capacitor C1 drops sharply, and the control terminals of the first discharge transistor N1 and the third discharge transistor N3 are pulled to a high level, and the first discharge transistor N1 and the third discharge transistor N3 are turned on to discharge the static charge in time.

[0103] In the above technical solution, the electrostatic protection circuit includes a plurality of discharge transistors and a plurality of control units, and each control unit includes two laser fuse devices. After manufacturing multiple chips in one chip fabrication run, perform fuse processing on the corresponding laser fuse devices to set the number of discharge transistors in the electrostatic protection circuit in the discharge mode, so as to obtain electrostatic protection circuits with different electrostatic protection capabilities, and then use the set electrostatic protection circuits for testing to obtain the structure of the optimal electrostatic protection circuit and reduce the test cost.

[0104] The present application also provides a method for testing the electrostatic protection ability of a chip, and the testing method includes the following steps:

[0105] S301. Obtain the setting modes of each discharge transistor of each chip in several groups of chips.

[0106] In this step, after manufacturing several chips including the electrostatic protection circuit described in the above embodiment in one chip fabrication run, divide the several chips into several groups, and determine the setting modes of each discharge transistor in each group of chips according to the test requirements to determine the structure of the electrostatic protection circuit of each chip.

[0107] In one embodiment, the structures of the electrostatic protection circuits between any two groups of chips are different, and the structures of the electrostatic protection circuits of each chip in the same group of chips are the same. By statistically analyzing the test results of the chips in the same group, the test performance of the electrostatic protection circuit in the group of chips can be obtained.

[0108] S302. Generate setting signals for each chip in several groups of chips according to the setting modes of each discharge transistor of each chip in several groups of chips.

[0109] In this step, the setting signal is used to switch the operating mode of the discharge transistor.

[0110] S303. Send a setting signal to each chip in several groups of chips to set the setting mode of each discharge transistor in each chip.

[0111] In this step, when each switch in the chip is a one-time programmable device, send a setting signal to the corresponding one-time programmable device to set the operating mode of each discharge transistor in each chip.

[0112] In one embodiment, if the one-time programmable device is a laser fuse device, emit laser light to the corresponding laser fuse device to set the operating mode of each discharge transistor in each chip.

[0113] S304. Perform an electrostatic test on several groups of chips and determine the structure of the optimal electrostatic protection circuit according to the test results.

[0114] In this step, when evaluating the test results, the various test performance parameters of the chip can be classified, the level where each performance parameter of the chip is located can be determined, and a weighted average of the levels where each performance parameter of the chip is located can be obtained to obtain the performance level of the chip. The electrostatic protection circuit in the chip with the highest performance level is used as the optimal electrostatic protection circuit.

[0115] In the above technical solution, multiple chips are fabricated through one-time chip fabrication, and the operating mode of the discharge transistor is set for each group of chips to ensure that the structures of the electrostatic protection circuits in each group of chips are different, so as to obtain chips with different electrostatic protection performances. Then, an electrostatic test is performed on the chips, and the optimal electrostatic protection circuit is obtained according to the test results. Compared with the method of updating the electrostatic protection ability of the chip by using multiple chip fabrications, this solution only requires one-time chip fabrication, reducing the test cost and simplifying the test process.

[0116] It should be understood that the present application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An electrostatic protection circuit for a chip, characterized in that, The chip includes a power pad and a ground pad, and the electrostatic protection circuit includes: A monitoring unit for generating a trigger signal when there is an electrostatic pulse on the power pad; A first discharge transistor located between the power pad and the ground pad, and configured to conduct under the control of the trigger signal when operating in the discharge mode to discharge electrostatic charges to the ground pad; A first control unit connected to the first discharge transistor for switching the operating mode of the first discharge transistor; wherein the operating mode includes the discharge mode; A second discharge transistor located between the power pad and the ground pad, and configured to conduct under the control of the trigger signal when operating in the discharge mode to discharge electrostatic charges to the ground pad; A second control unit connected to the second discharge transistor for switching the operating mode of the second discharge transistor; wherein the operating mode includes the discharge mode; The first control unit is connected to the monitoring unit and also to the control terminal of the first discharge transistor; The second control unit is connected to the monitoring unit and also to the control terminal of the second discharge transistor; The first control unit includes: A first switch, whose first end is connected to the control terminal of the corresponding discharge transistor and whose second end is connected to the monitoring unit; A second switch, whose first end is connected to the control terminal of the corresponding discharge transistor and whose second end is connected to the monitoring unit; The first switch and the second switch are one-time programmable memories.

2. The circuit according to claim 1, characterized in that, The electrostatic protection circuit further includes: A third discharge transistor located between the power pad and the ground pad, and configured to conduct under the control of the trigger signal when operating in the discharge mode to discharge electrostatic charges to the ground pad; A third control unit connected to the third discharge transistor for switching the operating mode of the third discharge transistor; wherein the operating mode includes the discharge mode.

3. The circuit according to claim 2, wherein The first discharge transistor is further configured to be in a cut-off state when operating in the bypass mode; The second discharge transistor is further configured to be in a cut-off state when operating in the bypass mode; The third discharge transistor is further configured to be in a cut-off state when operating in the bypass mode.

4. The circuit according to claim 2, wherein The sizes of the first discharge transistor, the second discharge transistor, and the third discharge transistor form an arithmetic sequence, a geometric sequence, or are equal.

5. The circuit according to claim 4, characterized in that, The aspect ratios of the first discharge transistor, the second discharge transistor, and the third discharge transistor form an arithmetic sequence, a geometric sequence, or are equal.

6. The circuit according to claim 4, characterized in that, The first discharge transistor, the second discharge transistor, and the third discharge transistor are of the same type.

7. The circuit according to claim 1, characterized in that The first switch and the second switch are laser fuse devices.

8. The circuit according to claim 7, wherein The monitoring unit includes: A monitoring resistor, whose first end is connected to the power pad and whose first end is also connected to the second end of the second switch; A monitoring capacitor, whose first end is connected to the second end of the monitoring resistor and then connected to the second end of the first switch, and whose second end is connected to the ground pad.

9. The circuit according to claim 8, wherein If the first discharge transistor is a P-type transistor, the first switch is in a non-fused state, the second switch is in a fused state, and the first discharge transistor is in a discharge mode; If the first discharge transistor is a P-type transistor, the first switch is in a fused state, the second switch is in a non-fused state, and the first discharge transistor is in a bypass mode.

10. The circuit according to claim 7, characterized in that, The monitoring unit includes: A monitoring capacitor, whose first terminal is connected to the power supply pad; A monitoring resistor, whose first terminal is connected to the second terminal of the monitoring capacitor and then to the second terminal of the first switch, and whose second terminal is connected to the ground pad and also to the second terminal of the second switch.

11. The circuit according to claim 10, wherein If the first discharge transistor is an N-type transistor, the first switch is in a non-fused state, the second switch is in a fused state, and the first discharge transistor is in a discharge mode; If the first discharge transistor is an N-type transistor, the first switch is in a fused state, the second switch is in a non-fused state, and the first discharge transistor is in a bypass mode.

12. The circuit according to claim 2, wherein The third control unit is connected to the monitoring unit and is also connected to the control terminal of the third discharge transistor.

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