Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: forming an initial isolation layer on top of a substrate; forming a protective layer on the sidewalls of a first fin and a first channel fin exposed by the initial isolation layer; removing a portion of the initial isolation layer to expose a portion of the sidewalls of the first fin, with the remaining initial isolation layer serving as a first isolation layer; converting the first fin exposed by the first isolation layer and the protective layer into a second fin, with the remaining first fin located on top of the second fin serving as a second channel fin in a second device region; forming a second isolation layer on top of the first isolation layer in the first device region, with the second isolation layer and the first isolation layer constituting an isolation layer; removing the protective layer; removing the second fin in the second device region and the first fin in the first device region; and forming a gate structure on top of the isolation layer that spans the first channel fin and the second channel fin. The gate structure satisfies the carrier mobility requirements of first-type transistors and second-type transistors, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently widely used. Therefore, as the component density and integration of semiconductor transistors increase, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

[0003] To better adapt to the requirement of scaling down transistor size, semiconductor processes have gradually begun to transition from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. Among them, GAA transistors include vertical GAA transistors and horizontal GAA transistors. In GAA transistors, the gate surrounds the channel area on all sides. Compared with planar transistors, the gate of GAA transistors has stronger control over the channel and can better suppress short channel effects.

[0004] As device sizes continue to shrink, improving the carrier mobility of the conductive channels of both NMOS devices with a fully encircling gate structure and PMOS devices with a fully encircling gate structure becomes increasingly difficult and challenging. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor; a first fin protruding from the top of the substrate, the top of the first fin in the first device region being lower than the top of the first fin in the second device region; a second fin located on the top of the first fin in the first device region, the top of the second fin being flush with the top of the first fin in the second device region, and the second fin and the first fin being made of different materials; an isolation layer located on the substrate where the first fin and the second fin are exposed, the isolation layer covering the sidewalls of the first fin and the second fin; a first channel fin located on the substrate The top of the second fin in the first device region is arranged spaced apart from the second fin in the longitudinal direction; the second channel fin is located on the top of the first fin in the second device region and spaced apart from the first fin in the longitudinal direction, and the materials of the second channel fin and the first channel fin are different; the gate structure is located on the top of the isolation layer and spans the first channel fin and the second channel fin, and the gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer, wherein, in the first device region, the gate dielectric layer surrounds and covers a portion of the top, a portion of the sidewall and a portion of the bottom of the first channel fin, and in the second device region, the gate dielectric layer surrounds and covers a portion of the top, a portion of the sidewall and a portion of the bottom of the second channel fin.

[0007] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, a protruding first fin being formed on the top of the substrate, a first channel fin being formed on the top of the first fin in the first device region, the first channel fin and the first fin being made of different materials, the top of the first channel fin being flush with the top of the first fin in the second device region; forming an initial isolation layer on the top of the substrate, the initial isolation layer covering a portion of the sidewalls of the first fin, the top of the initial isolation layer in the second device region being higher than the top of the initial isolation layer in the first device region; forming a protective layer on the sidewalls of the first fin and the first channel fin exposed by the initial isolation layer; after forming the protective layer, removing a portion of the initial isolation layer to expose a portion of the sidewalls of the first fin, and the remaining initial isolation layer serving as the first isolation layer; performing a modification treatment on the first fin exposed by the first isolation layer and the protective layer. The first fin exposed by the first isolation layer and the protective layer is converted into a second fin, and in the second device area, the remaining first fin located on the top of the second fin serves as a second channel fin; a second isolation layer is formed on the top of the first isolation layer in the first device area, the second isolation layer covers the sidewalls of the second fin, and the top of the second isolation layer is flush with the top of the first isolation layer in the second device area, and the second isolation layer and the first isolation layer constitute an isolation layer; the protective layer is removed; after removing the protective layer, the second fin in the second device area and the first fin in the first device area are removed; after removing the second fin in the second device area and the first fin in the first device area, a gate structure spanning the first channel fin and the second channel fin is formed on the top of the isolation layer, in the first device area, the gate structure surrounds and covers part of the top, part of the sidewall and part of the bottom of the first channel fin, and in the second device area, the gate structure surrounds and covers part of the top, part of the sidewall and part of the bottom of the second channel fin.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a method for forming a semiconductor structure. In the process of forming an initial isolation layer on the top of a substrate, the initial isolation layer covers part of the sidewalls of the first fin, and the top of the initial isolation layer located in the second device region is higher than the top of the initial isolation layer in the first device region, that is, there is a height difference between the initial isolation layers in the first device region and the second device region. Then, a protective layer is formed on the sidewalls of the first fin and the first channel fin exposed by the initial isolation layer, and then a portion of the thickness of the initial isolation layer is removed to form a first isolation layer exposing part of the sidewalls of the first fin. The first fin exposed by the first isolation layer and the protective layer is modified to convert the first fin exposed by the first isolation layer and the protective layer into a second fin, so that the remaining first fin located on the top of the second fin serves as the second channel fin. Therefore, after removing the first fin in the first device region and the second fin in the second device region, the first channel fin in the first device region and the second channel fin in the second device region respectively meet the carrier mobility requirements of the first-type transistor and the second-type transistor, so as to meet the respective performance requirements of the first-type transistor and the second-type transistor, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural diagram of a semiconductor structure;

[0011] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 3 to 25 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0014] Figure 1 It is a structural diagram of a semiconductor structure.

[0015] refer to Figure 1The semiconductor structure includes: a base, the base including a substrate 10, and a bottom fin 11 protruding from the substrate 10, the base including a first device region 10A for forming a first-type transistor and a second device region 10B for forming a second-type transistor; a channel fin 12, located on the top of the bottom fin 11 and spaced apart from the bottom fin 11 in the longitudinal direction; an isolation layer 20, located on the substrate 10 where the bottom fin 11 is exposed, and the top of the isolation layer 20 is flush with the top of the bottom fin 11; a gate structure 21, located on the top of the isolation layer 20 and spanning the channel fin 12, the gate structure 21 surrounding and covering a portion of the top, a portion of the sidewall and a portion of the bottom of the channel fin 12.

[0016] The first device region 10A is used to form a PMOS transistor, and the second device region 10B is used to form an NMOS transistor.

[0017] like Figure 1 As shown, the channel fins 12 of the first device region 10A and the second device region 10B are made of the same material, that is, the first-type transistor and the second-type transistor can only use the same channel fin material. When the first-type transistor and the second-type transistor need to use channel fins 12 of different materials (for example, different channel fins are needed to meet the requirements of carrier mobility), the semiconductor structure cannot meet the requirements of retaining the required channel fins 12 in the first device region 10A and the second device region 10B, making it difficult to meet the performance requirements of the second-type transistor and the first-type transistor respectively.

[0018] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, a protruding first fin being formed on the top of the substrate, a first channel fin being formed on the top of the first fin in the first device region, the first channel fin and the first fin being made of different materials, and the top of the first channel fin being flush with the top of the first fin in the second device region; forming an initial isolation layer on the top of the substrate, the initial isolation layer covering a portion of the sidewall of the first fin, the top of the initial isolation layer in the second device region being higher than the top of the initial isolation layer in the first device region; forming a protective layer on the sidewalls of the first fin and the first channel fin exposed by the initial isolation layer; after forming the protective layer, removing a portion of the initial isolation layer to expose a portion of the sidewall of the first fin, and the remaining initial isolation layer serving as the first isolation layer; and performing a modification treatment on the first fin exposed by the first isolation layer and the protective layer. , converting the first fin exposed by the first isolation layer and the protective layer into a second fin, and in the second device area, the remaining first fin located on the top of the second fin serves as a second channel fin; forming a second isolation layer on the top of the first isolation layer in the first device area, the second isolation layer covers the sidewalls of the second fin, and the top of the second isolation layer is flush with the top of the first isolation layer in the second device area, and the second isolation layer and the first isolation layer constitute an isolation layer; removing the protective layer; after removing the protective layer, removing the second fin in the second device area and the first fin in the first device area; after removing the second fin in the second device area and the first fin in the first device area, forming a gate structure spanning the first channel fin and the second channel fin on the top of the isolation layer, in the first device area, the gate structure surrounds and covers part of the top, part of the sidewall and part of the bottom of the first channel fin, and in the second device area, the gate structure surrounds and covers part of the top, part of the sidewall and part of the bottom of the second channel fin.

[0019] In an embodiment of the present invention, during the process of forming an initial isolation layer on the top of the substrate, the initial isolation layer covers part of the side walls of the first fin, and the top of the initial isolation layer located in the second device region is higher than the top of the initial isolation layer in the first device region, that is, there is a height difference between the initial isolation layers of the first device region and the second device region. Then, a protective layer is formed on the side walls of the first fin and the first channel fin exposed by the initial isolation layer, and then a portion of the thickness of the initial isolation layer is removed to form a first isolation layer exposing part of the side walls of the first fin. The first fin exposed by the first isolation layer and the protective layer is modified to convert the first fin exposed by the first isolation layer and the protective layer into a second fin, so that the remaining first fin located on the top of the second fin serves as the second channel fin. Therefore, after removing the first fin in the first device region and the second fin in the second device region, the first channel fin in the first device region and the second channel fin in the second device region respectively meet the carrier mobility requirements of the first-type transistor and the second-type transistor, so as to meet the respective performance requirements of the first-type transistor and the second-type transistor, thereby improving the performance of the semiconductor structure.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] Figure 2 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0022] The semiconductor structure includes: a substrate 200, wherein the substrate 200 includes a first device region 200A for forming a first-type transistor and a second device region 200B for forming a second-type transistor; a first fin 201 protruding from the top of the substrate 200, wherein the top of the first fin 201 in the first device region 200A is lower than the top of the first fin 201 in the second device region 200B; a second fin 212 located at the top of the first fin 201 in the first device region 200A, wherein the top of the second fin 212 is flush with the top of the first fin 201 in the second device region 200B, and the second fin 212 and the first fin 201 are made of different materials; an isolation layer 260 located on the substrate 200 where the first fin 201 and the second fin 212 are exposed, wherein the isolation layer 260 covers the sidewalls of the first fin 201 and the second fin 212; a first channel fin 202 located at The top of the second fin 212 of the first device region 200A is arranged spaced apart from the second fin 212 in the longitudinal direction; the second channel fin 216 is located at the top of the first fin 201 of the second device region 200B and spaced apart from the first fin 201 in the longitudinal direction, and the second channel fin 216 and the first channel fin 202 are made of different materials; the gate structure 228 is located at the top of the isolation layer 260 and spans the first channel fin 202 and the second channel fin 216, and the gate structure 228 includes a gate dielectric layer (not marked) and a gate electrode layer (not marked) covering the gate dielectric layer, wherein in the first device region 200A, the gate dielectric layer surrounds and covers a portion of the top, a portion of the sidewall and a portion of the bottom of the first channel fin 202, and in the second device region 200B, the gate dielectric layer surrounds and covers a portion of the top, a portion of the sidewall and a portion of the bottom of the second channel fin 216.

[0023] In this embodiment, the first channel fin 202 is located on the top of the second fin 212 of the first device region 200A and is spaced apart from the second fin 212 in the longitudinal direction. The second channel fin 216 is located on the top of the first fin 201 of the second device region 200B and is spaced apart from the first fin 201 in the longitudinal direction. The second channel fin 216 and the first channel fin 202 are made of different materials. The first channel fin 202 and the second channel fin 216 can respectively meet the carrier mobility requirements of the first-type transistor and the second-type transistor, so as to respectively meet the performance requirements of the first-type transistor and the second-type transistor, thereby improving the performance of the semiconductor structure.

[0024] The longitudinal direction refers to the normal direction of the surface of the substrate 200 .

[0025] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate may be one or more of a silicon-germanium combination, germanium, and a silicon / silicon oxide combination (SOC).

[0026] In this embodiment, the substrate 200 and the first fin 201 form an integrated structure. Therefore, the material of the first fin 201 is the same as that of the substrate 200, that is, silicon. In other embodiments, the first fin is made of the same material as the topmost semiconductor layer in the substrate.

[0027] The first channel fin 202 is used as a conductive channel of the first device region 200A.

[0028] In this embodiment, the first-type transistor is a gate-all-around transistor, and therefore, the first channel fin 202 is spaced apart from the second fin 212 in the vertical direction.

[0029] The material of the first channel fin 202 includes SiGe, Ge, or a Group III-V semiconductor material, and there is an etching selectivity ratio between the materials of the first channel fin 202 and the first fin 201 .

[0030] In this embodiment, the first-type transistor is used to form a PMOS transistor, so the material of the first channel fin 202 is SiGe. Using SiGe channel technology for PMOS transistors is beneficial to improving the carrier mobility of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0031] The second channel fin 216 is used to serve as a conductive channel of the second device region 200B.

[0032] In this embodiment, the second-type transistor is a fully enclosed gate transistor, and therefore, the second channel fin 216 is spaced apart from the first fin 201 in the vertical direction.

[0033] The material of the second channel fin 216 includes one or both of Si and SiC.

[0034] In this embodiment, the material of the second channel fin 216 is Si.

[0035] In this embodiment, the second channel fin 216 and the first channel fin 202 are made of different materials, thereby respectively meeting the carrier mobility requirements of the first-type transistor and the second-type transistor, thereby respectively meeting the performance requirements of the first-type transistor and the second-type transistor.

[0036] In this embodiment, the first channel fin 202 and the second channel fin 216 have the same height, and the bottom surface of the first channel fin 202 is flush with the bottom surface of the second channel fin 216, so that the top surface heights of the first channel fin 202 and the second channel fin 216 are consistent, so that the top surface flatness of the semiconductor structure is higher, thereby improving the performance of the semiconductor structure.

[0037] In this embodiment, the second fin 212 is located on the top of the first fin 201 in the first device region 200A, and the top of the second fin 212 is flush with the top of the first fin 201 located in the first device region 200A, so that the top surfaces of the first channel fin 202 and the second channel fin 216 have higher flatness, thereby improving the performance of the semiconductor structure.

[0038] In this embodiment, the second fin 212 and the first fin 201 are made of different materials.

[0039] Therefore, there is an etching selectivity ratio between the materials of the second fin 212 and the first fin 201 .

[0040] During the formation of the semiconductor structure, the first channel fin 202 and the second fin 212 form a first fin 201, and a second fin 212 is formed between the second channel fin 216 and the first fin 201, and the second fin 212 is formed by modifying the first fin 201. Therefore, by making the materials of the second fin 212 and the first fin 201 different, the damage to the second fin 212 can be reduced during the removal of the first fin 201 in the first device area 200A, so that the second fin 212 in the first device area 200A is retained, and the first channel fin 202 can be suspended above the top of the second fin 212; similarly, in the process of removing the second fin 212 in the second device area 200B, the damage to the first fin 201 is reduced, so that the first fin 201 in the second device area 200B is retained, and the second channel fin 216 can be suspended above the top of the first fin 201.

[0041] Specifically, the material of the second fin 212 includes one or more of SiGe, Ge, or Group III-V semiconductor materials.

[0042] In this embodiment, the material of the second fin 212 is SiGe. SiGe has a high etching selectivity compared to Si, thereby reducing damage to the SiGe material when etching the Si material. Similarly, reducing damage to the Si material when etching the SiGe material.

[0043] In other embodiments, depending on the material of the first fin, the material of the second fin may also be SiP or SiC.

[0044] The isolation layer 260 is used to isolate adjacent transistors.

[0045] In this embodiment, the isolation layer 260 covers the sidewalls of the first fin 201 and the second fin 212 , so that the first transistor only uses the first channel fin 202 as a conductive channel and the second transistor only uses the second channel fin 216 as a conductive channel.

[0046] The isolation layer 260 is made of silicon oxide.

[0047] In this embodiment, the isolation layer 260 includes: a first isolation layer 210, located on the substrate 200 of the first device area 200A and the second device area 200B, the first isolation layer 210 covering the side walls of the first fin 201 and exposing the side walls of the second fin 212; a second isolation layer 218, located on the top of the first isolation layer 210 in the first device area 200A, the second isolation layer 218 covering the side walls of the second fin 212, and the top of the second isolation layer 218 is flush with the top of the first isolation layer 210 located in the second device area 200B.

[0048] To ensure that the first channel fin 202 in the first device region 200A and the second channel fin 216 in the second device region 200B are of equal height and flush with each other, and to ensure that the effective capacitances of the semiconductor devices in the first device region 200A and the semiconductor devices in the second device region 200B match or maintain a specific difference, during the formation process of the second fin 212, the height of the second fin 212 in the first device region 200A is lower than that of the second fin 212 in the second device region 200B. From the above analysis, it can be seen that during the formation process of the semiconductor structure, the first channel fin 202 and the second fin 212 form a first fin 201, and a second fin 212 is formed between the second channel fin 216 and the first fin 201, and the second fin 212 is formed by modifying the first fin 201. Therefore, by making the top of the first isolation layer 210 of the first device area 200A lower than the top of the first isolation layer 210 of the second device area 200B, it is convenient to convert the first fin 201 of a part of the height in the first device area 200A into the second fin 212.

[0049] Furthermore, by forming the second isolation layer 218 on top of the first isolation layer 210 in the first device region 200A, the probability of parasitic capacitance generated between the gate structure 228 and the second fin 212 in the first device region 200A is reduced.

[0050] It should be noted that, in order to ensure uniform insulation between the semiconductor structures in the first device region 200A and the second device region 200B and to improve the material compatibility between the second isolation layer 218 and the first isolation layer 210, the material of the second isolation layer 218 is the same as that of the first isolation layer 210. To this end, as an example, the materials of the second isolation layer 218 and the first isolation layer 210 are both silicon oxide.

[0051] When the device is in operation, the gate structure 228 is used to control the opening or closing of the conductive channels of the first-type transistor in the first device region 200A and the second-type transistor in the second device region 200B.

[0052] In this embodiment, the gate structure 228 includes a gate dielectric layer (not labeled) and a gate electrode layer (not labeled) covering the gate dielectric layer.

[0053] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0054] Specifically, in the first device region 200A, the gate dielectric layer surrounds and covers part of the top, part of the sidewall and part of the bottom of the first channel fin 202, and in the second device region 200B, the gate dielectric layer surrounds and covers part of the top, part of the sidewall and part of the bottom of the second channel fin.

[0055] In this embodiment, the gate electrode layer spans the first channel fin 202 and the second channel fin 216 , and the gate electrode layer surrounds and covers the gate dielectric layer.

[0056] The gate electrode layer is used for subsequent electrical connection to external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.

[0057] In this embodiment, the semiconductor structure further includes a sidewall spacer 220 located on a sidewall of the gate structure 228 .

[0058] The sidewall spacer 220 is used to define the formation area of ​​the gate structure 228 and is also used to protect the sidewalls of the gate structure. The sidewall spacer 220 can be a single-layer structure or a stacked structure. The material of the sidewall spacer 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 220 is a single-layer structure and is made of silicon nitride.

[0059] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 222 , which is located on the gate structure 228 and the isolation layer 260 exposed by the spacer 220 , and covers the sidewalls of the spacer 220 .

[0060] The interlayer dielectric layer 222 is used to isolate adjacent devices. The material of the interlayer dielectric layer 222 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 222 is silicon oxide.

[0061] Figures 3 to 25 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0062] refer to Figure 3 , providing a substrate 100, wherein the substrate 100 includes a first device region 100A for forming a first-type transistor and a second device region 100B for forming a second-type transistor, a protruding first fin 101 is formed on the top of the substrate 100, a first channel fin 102 is formed on the top of the first fin 101 in the first device region 100A, the first channel fin 102 and the first fin 101 are made of different materials, and the top of the first channel fin 102 is flush with the top of the first fin 101 in the second device region 100B.

[0063] The substrate 100 is used to provide a process platform for subsequent process steps.

[0064] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be one or more of a silicon-germanium combination, germanium, and a silicon / silicon oxide combination (SOC).

[0065] The substrate 100 includes a first device region 100A for forming a first-type transistor and a second device region 100B for forming a second-type transistor. In this embodiment, the first-type transistor is used to form a PMOS transistor, and the second-type transistor is used to form an NMOS transistor. In other embodiments, the first-type transistor is an NMOS transistor and the second-type transistor is a PMOS transistor.

[0066] The first fin 101 is used to form a second channel fin located in the second device region 100B, wherein the second channel fin is used to provide a conductive channel of a second-type transistor.

[0067] In this embodiment, the material of the first fin 101 includes one or both of Si and SiC.

[0068] Specifically, the substrate 100 and the first fin 101 form an integrated structure. The substrate 100 is a silicon substrate. Therefore, the material of the first fin 101 is the same as that of the substrate 100 , that is, the material of the first fin 101 is silicon (Si).

[0069] The first channel fin 102 is used to serve as a conductive channel of the first-type transistor.

[0070] The material of the first channel fin 102 includes SiGe (silicon germanium), Ge (germanium) or a Group III-V semiconductor material, and an etching selectivity ratio exists between the first channel fin 102 and the first fin 101 .

[0071] In this embodiment, the material of the first channel fin 102 is SiGe.

[0072] It should be noted that the material of the first fin 101 of the second device area 100B is silicon, and the Si channel technology is used for the NMOS transistor, which is beneficial to improving the performance of the NMOS transistor, that is, improving the carrier mobility of the NMOS transistor; the material of the first channel fin 102 of the first device area 100A is silicon germanium, and the SiGe channel technology is used for the PMOS transistor, which is beneficial to improving the performance of the PMOS transistor, that is, improving the carrier mobility of the PMOS transistor.

[0073] In this embodiment, the steps of forming the substrate 100, the first fin 101 and the first channel fin 102 include: providing a base (not marked); in the first device area, removing part of the thickness of the base and forming a groove (not marked) in the base; forming a first channel fin material layer (not marked) in the groove, the top surface of the first channel fin material layer being flush with the top surface of the base in the second device area; forming a separate fin mask layer 103 on top of the first channel fin material layer and the base; using the fin mask layer 103 as a mask, patterning the base and the first channel fin material layer, patterning a part of the height of the base into the first fin 101, patterning the first channel fin material layer into the first channel fin 102, the top of the first channel fin 102 being flush with the top of the first fin 101 in the second device area 100, and the remaining base after the patterning process serves as the substrate 100.

[0074] In this embodiment, the material of the fin mask layer 103 is SiO 2 .

[0075] In this embodiment, an etch stop layer 104 is formed on the top of the first channel fin 102 of the first device region and the top of the first fin 101 of the second device region. The etch stop layer 104 is located between the first channel fin 102 and the fin mask layer 103, and between the first fin 101 and the fin mask layer 103.

[0076] During the process of forming the separate fin mask layer 103 , the etch stop layer 104 functions as an etch stop, thereby reducing the probability of causing damage to the materials corresponding to the first channel fin 102 and the first fin 101 .

[0077] In this embodiment, the material of the etch stop layer 104 is SiN.

[0078] The top of the first channel fin 102 is flush with the top of the first fin 101 in the second device area 100B, providing a process basis for the subsequent formation of various film layers with higher top surface flatness. Moreover, the top surface flatness of the first channel fin 202 and the second channel fin subsequently formed in the second device area is higher.

[0079] refer to Figures 4 to 7 An initial isolation layer 107 is formed on the top of the substrate 100, and the initial isolation layer 107 covers part of the sidewall of the first fin 101. The top of the initial isolation layer 107 in the second device region 100B is higher than the top of the initial isolation layer 107 in the first device region 100A.

[0080] The initial isolation layer 107 provides a process basis for the subsequent formation of the first isolation layer. Meanwhile, the initial isolation layer 107 also exposes part of the sidewall of the first fin 101 and the sidewall of the first channel fin 102 , providing a process basis for the subsequent formation of the protection layer.

[0081] In order to ensure that the subsequently formed second channel fin has the same height and flush top as the first channel fin 102, and has the same shape and size, in this embodiment, the top of the initial isolation layer 107 located in the second device area 100B is flush with the bottom of the first channel fin 102 located in the first device area 100A, so that the contact area between the gate structure subsequently formed in the first device area 100A and the first channel fin 102 and the contact area between the gate structure formed in the second device area 100B and the second channel fin are equal, thereby maintaining the effective capacitance generated by the semiconductor device in the first device area 100A and the semiconductor device in the second device area 100B matching.

[0082] It should be noted that the height difference H (eg, Figure 7 The height difference H between the initial isolation layer 107 of the second device region 100B and the initial isolation layer 107 of the first device region 100A is too large, and the filling difficulty of each film layer of the gate structure is increased in the subsequent process of forming the gate structure, and the probability of generating a gap between the gate structure and the first channel fin 102 and the second channel fin is increased, thereby affecting the performance of the semiconductor structure; if the height difference H between the initial isolation layer 107 of the second device region 100B and the initial isolation layer 107 of the first device region 100A is too small, then in the subsequent process of removing the second fin in the second device region 100B and the first fin 101 in the first device region 100A, the difficulty of the etching process is increased due to the excessively small process window, which easily leads to the second fin in the second device region 100B and the first fin 101 in the first device region 100A being not removed cleanly, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, a height difference H between the tops of the initial isolation layer 107 of the second device region 100B and the initial isolation layer 107 of the first device region 100A is 50 angstroms to 200 angstroms.

[0083] Combined with reference Figures 4 to 7 , the step of forming the initial isolation layer 107 on the top of the substrate 100 is described in detail.

[0084] refer to Figures 4 and 5 An isolation material layer 105 is formed on the substrate 100 where the first fin 101 and the first channel fin 102 are exposed, and the isolation material layer 105 covers the sidewalls of the first fin 101 and the first channel fin 102 .

[0085] The isolation material layer 105 provides a process basis for forming the initial isolation layer 107 .

[0086] In this embodiment, the process of forming the isolation material layer 107 includes a chemical vapor deposition process.

[0087] The isolation material layer 105 is an insulating material. In this embodiment, the isolation material layer 105 is made of silicon oxide.

[0088] In this embodiment, the steps of forming the isolation material layer 105 include: Figure 4 As shown, an initial isolation material layer 180 is formed on the substrate 100 where the first fin 101 and the first channel fin 102 are exposed; Figure 5As shown, the top of the etch stop layer 104 is used as the stop position, and the fin mask layer 103 and the initial isolation material layer 180 higher than the etch stop layer 104 are planarized, and the remaining initial isolation material layer 180 is used as the isolation material layer 105.

[0089] refer to Figure 6 , a doping treatment is performed on a portion of the thickness of the isolation material layer 105 in the second device region 100B, and the doping treatment is used to improve the etching resistance of the isolation material layer 105.

[0090] Subsequently, an initial isolation layer 107 is formed by back-etching the isolation material layer 105. Since a portion of the thickness of the isolation material layer 105 in the second device area 100B is doped, in the step of forming the initial isolation layer 107, the etching rate of the isolation material layer 105 in the second device area 100B is less than the etching rate of the isolation material layer 105 in the first device area 100A, thereby providing a process basis for forming the initial isolation layer 107 with a height difference.

[0091] In this embodiment, the step of doping the isolation material layer 105 with a partial thickness in the second device area 100B includes: in the first device area 100A, forming a mask layer 106 on the top of the isolation material layer 105 and the first channel fin 102; using the mask layer 106 as a mask, doping the isolation material layer 105 of the second device area 100B.

[0092] It should be noted that in the second device region 100B, an etch stop layer 104 is formed on the top of the first fin 101 . The etch stop layer 104 protects the first fin 101 . Therefore, the doping process has little effect on the first fin 101 .

[0093] In this embodiment, the process of performing doping treatment on a portion of the thickness of the isolation material layer 105 in the second device region 100B includes an ion implantation process.

[0094] The ion implantation process is a process of implanting ions accelerated to a certain high energy into the surface layer of a solid material to change the physical and chemical properties of the surface layer. It has the characteristics of high efficiency and strong firmness of the modified layer. The isolation material layer 105 of the second device area 100B is doped, thereby changing the etching rate of the isolation material layer 105 of the second device area 100B.

[0095] In this embodiment, the implanted ions in the ion implantation process include one or more of Si, N, Cl, P and B ions.

[0096] Si, N, Cl, P and B ions are inert ions. After the isolation material layer 105 of the second device region 100B is doped, the etching rate of the isolation material layer 105 doped with ions is reduced, and the isolation performance of the isolation material layer 105 is less affected.

[0097] It should be noted that the ion implantation energy of the ion implantation process should not be too large or too small. If the ion implantation energy is too large, the process is difficult to control, and accordingly, the depth of the ion-doped isolation material layer 105 is too large, making the thickness of the isolation material layer 105 with higher etching resistance in the second device area 100B too large, increasing the difficulty of removing the isolation material layer 105 in the second device area 100B, and making the height difference between the initial isolation layer 107 in the first device area 100A and the initial isolation layer 107 in the second device area 100B unable to meet the process requirements, thereby affecting the performance of the semiconductor structure; if the ion implantation energy is too small, the ion implantation reaction time is too long, the efficiency of the process is reduced, the depth of the ion-doped isolation material layer 105 is affected, and it is easy to cause the etching rates of the isolation material layer 105 in the first device area 100A and the isolation material layer 105 in the second device area 100B to be close, so that the height difference between the initial isolation layer 107 in the first device area 100A and the initial isolation layer 107 in the second device area 100B cannot meet the process requirements. To this end, in this embodiment, the ion implantation energy ranges from 1.0 keV to 6.0 keV.

[0098] It should be noted that the ion implantation dose of the ion implantation process should not be too large or too small. If the ion implantation dose is too large, the process will be difficult to control, and accordingly, the depth of the ion-doped isolation material layer 105 will be too large, making the etching selectivity between the isolation material layer 105 in the first device area 100A and the isolation material layer 105 in the second device area 100B too large, increasing the difficulty of removing the isolation material layer 105 in the second device area 100B, and making the height difference between the initial isolation layer 107 in the first device area 100A and the initial isolation layer 107 in the second device area 100B unable to meet the process requirements. The process requirements are met, thereby affecting the performance of the semiconductor structure; if the ion implantation dose is too small, the reaction time of the ion implantation is too long, the efficiency of the process is reduced, the depth of the ion-doped isolation material layer 105 is affected, and it is easy to cause the isolation material layer 105 in the first device area 100A and the isolation material layer 105 in the second device area 100B to be etched at similar rates, so that the height difference between the initial isolation layer 107 in the first device area 100A and the initial isolation layer 107 in the second device area 100B cannot meet the process requirements. Therefore, in this embodiment, the ion implantation dose range is 1.0E15atom / cm 3 to 2.0E16atom / cm 3 .

[0099] In this embodiment, after the isolation material layer 105 in the second device region 100B is doped, the method further includes: removing the mask layer 106 .

[0100] refer to Figure 7 After the doping treatment, the isolation material layer 105 of the first device region 100A and the second device region 100B is etched back to expose part of the sidewalls of the first fin 101 in the first device region 100A and the second device region 100B, and the remaining isolation material layer 105 serves as the initial isolation layer 107.

[0101] The isolation material layer 105 in the first device region 100A and the second device region 100B is etched back to provide space for the subsequent formation of a protection layer.

[0102] In this embodiment, the process of etching back the isolation material layer 105 in the first device region 100A and the second device region 100B includes a plasma dry etching process.

[0103] refer to Figures 8 and 9 A protection layer 109 is formed on the sidewalls of the first fin 101 and the first channel fin 102 exposed from the initial isolation layer 107 .

[0104] The protective layer 109 is used to define the position of the second fin to be formed subsequently. At the same time, during the subsequent formation of the first isolation layer, it provides protection for the side walls of the first fin 101 and the first channel fin 102 exposed by the initial isolation layer 107, thereby reducing the probability of damage to the first fin 101 and the first channel fin 102 by the related etching process.

[0105] In this embodiment, the step of forming a protective layer 109 on the sidewalls of the first fin 101 and the first channel fin 102 exposed from the initial isolation layer 107 includes: Figure 8 As shown, a protective material layer 108 is formed on the top of the substrate 100 to cover the sidewalls of the first fin 101, the sidewalls of the first channel fin 102, the top and sidewalls of the etch stop layer 104, and the top of the initial isolation layer 107; Figure 9 As shown, the protective material layer 108 on the top of the initial isolation layer 107 and the top of the etch stop layer 104 is removed, and the remaining protective material layer serves as the protective layer 109 .

[0106] In this embodiment, the process of forming the protective material layer 108 includes an atomic layer deposition process.

[0107] The atomic layer deposition process includes multiple atomic layer deposition cycles, which has good step coverage characteristics, is conducive to improving the thickness uniformity of the protective material layer 108, and enables the protective material layer 108 to cover the side walls of the first fin 101 and the first channel fin 102 exposed in the initial isolation layer 107.

[0108] In this embodiment, the process of removing the protective material layer 108 on the top of the initial isolation layer 107 includes a dry etching process.

[0109] refer to Figure 10 After forming the protective layer 109, a portion of the initial isolation layer 107 (eg Figure 9 As shown), a portion of the sidewall of the first fin 101 is exposed, and the remaining initial isolation layer 107 serves as the first isolation layer 110.

[0110] To facilitate the subsequent conversion of the first fin 101 at a portion of the height of the bottom of the protective layer 109 into the second fin in the first device area 100A and the second device area 100B, the initial isolation layer 107 is partially etched back to expose part of the sidewall of the first fin 101.

[0111] The first isolation layer 110 is used to isolate adjacent first fins 101 and the substrate 100 from a subsequently formed gate structure. Since the material of the first isolation layer 110 is the same as that of the initial isolation layer 107, the material of the first isolation layer 110 is silicon oxide.

[0112] In this embodiment, the thickness removal amount D of the initial isolation layer 107 is equal to the height difference H between the initial isolation layer 107 of the second device region 100B and the top of the initial isolation layer 107 of the first device region 100A. Accordingly, the distance between the bottom of the first channel fin 102 and the top of the substrate is equal to the distance between the subsequently formed second channel fin and the top of the substrate. Therefore, in the process of subsequently forming the gate structure, the film materials filled in the first device region 100A and the second device region 100B are equal, which is beneficial to the threshold voltage (V T ) regulation, thereby improving the performance of the semiconductor structure.

[0113] In this embodiment, the process of removing a portion of the initial isolation layer 107 includes a dry etching process.

[0114] refer to Figures 11 to 12 , the first fin 101 exposed by the first isolation layer 110 and the protective layer 109 is modified to convert the first fin 101 exposed by the first isolation layer 110 and the protective layer 109 into a second fin 112, and in the second device area 100B, the remaining first fin 101 located on the top of the second fin 112 serves as the second channel fin 116.

[0115] The first fin 101 is converted into the second fin 112, so that an etching selectivity ratio is generated between the first fin 101 and the second fin 112, which facilitates the subsequent removal of the first fin 101 in the first device area 100A and the second fin 112 in the second device area 100B, so that the first channel fin 102 and the second channel fin 116 are respectively spaced apart from the second fin 112 and the first fin 101 in the longitudinal direction, thereby providing a process basis for the subsequent formation of a gate structure surrounding the first channel fin 102 and the second channel fin 116.

[0116] In this embodiment, the step of modifying the first fin 101 exposed by the first isolation layer 110 and the protective layer 109 includes: forming a diffusion layer 111 on the sidewall of the first fin 101 exposed by the first isolation layer 110 and the protective layer 109; performing an annealing process on the diffusion layer 111 and the first fin 101 to allow ions in the diffusion layer 111 to diffuse laterally into the first fin 101, thereby converting the first fin 101 exposed by the first isolation layer 110 and the protective layer 109 into a second fin 112.

[0117] In this embodiment, the process of forming the diffusion layer 111 on the sidewalls of the first fin 101 exposed by the first isolation layer 110 and the protection layer 109 includes an epitaxial process.

[0118] The epitaxial process has the characteristics of low cost and simple process. It can grow in a specific area and has regional selectivity, so that the diffusion layer 111 is selectively formed on the side wall of the first fin 101 exposed by the protective layer 109 and the first isolation layer 110. The process is simple and the formation quality of the formed diffusion layer 111 is high.

[0119] In this embodiment, the material of the diffusion layer 111 includes SiGe or Ge.

[0120] It should be noted that the annealing process mainly utilizes the fact that the melting point of Ge is lower than that of Si. By controlling the annealing temperature, the Si ions in the first fin 101 material are replaced by the Ge ions in the diffusion layer 111, thereby converting the first fin 101 exposed by the first isolation layer 110 and the protective layer 109 into the second fin 112.

[0121] Therefore, in this embodiment, the material of the second fin 112 includes SiGe. In other embodiments, depending on the material of the first fin, the material of the second fin may also be one or more of germanium and Group III-V semiconductor materials.

[0122] To facilitate the subsequent removal of the second fin 112 in the second device region 100B and the first fin 101 in the first device region 100A, the higher the Ge content in the SiGe material of the second fin 112 , the greater the etching selectivity between the second fin 112 and the first fin 101 .

[0123] In this embodiment, the annealing process performed on the diffusion layer 111 and the first fin 101 includes a rapid thermal annealing process.

[0124] The rapid thermal annealing (RTA) process involves rapidly heating the device to a target temperature and then annealing the device in a short period of time. Rapid thermal annealing minimizes diffusion effects and effectively controls the size of the ion implantation diffusion region, ensuring that the second fin 112 formation region meets process requirements.

[0125] It should be noted that the process temperature of the annealing process should not be too high or too low. If the process temperature is too high, the diffusion range of the Ge ions in the diffusion layer 111 in the first fin 101 will be too large, and accordingly, the formation area of ​​the second fin 112 will be too large, which will not meet the process requirements and further affect the performance of the semiconductor structure. If the process temperature is too low, the diffusion range of the Ge ions in the diffusion layer 111 in the first fin 101 will be too small, and the first fin 101 exposed by the first isolation layer 110 will not be completely converted into the second fin 112, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the process temperature is 600°C to 1200°C.

[0126] It should be noted that the annealing process time should not be too long or too short. If the process time is too long, the diffusion range of the Ge ions in the diffusion layer 111 in the first fin 101 is likely to be too large, and accordingly, the formation area of ​​the second fin 112 is too large. This increases the probability of the second channel fin 116 being completely removed during the subsequent removal of the second fin 112 in the second device region 100B, thereby affecting the performance of the semiconductor structure. If the process time is too short, the diffusion range of the Ge ions in the diffusion layer 111 in the first fin 101 is likely to be too small, and the first fin 101 exposed by the first isolation layer 110 cannot be completely converted into the second fin 112, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the process time is 1 minute to 120 minutes.

[0127] refer to Figures 13 to 15 A second isolation layer 118 is formed on top of the first isolation layer 101 in the first device region 100A. The second isolation layer 118 covers the sidewalls of the second fin 112, and the top of the second isolation layer 118 is flush with the top of the first isolation layer 110 in the second device region 100B. The second isolation layer 118 and the first isolation layer 110 constitute an isolation layer (not marked).

[0128] In the first device region 100A, the second isolation layer 118 covers the sidewalls of the second fin 112 , facilitating the subsequent removal of the first fin 101 in the first device region 100A and the second fin 112 in the second device region 100B.

[0129] In this embodiment, the step of forming the second isolation layer 118 on top of the first isolation layer 110 in the first device region 100A includes: Figure 13As shown, a second isolation material layer 117 is formed on the top of the first isolation layer 110, and the second isolation material layer 117 covers the sidewalls of the second fin 112 and the top and sidewalls of the protection layer 109; Figure 14 As shown, the top of the protective layer 109 is used as the stop position to planarize the second isolation material layer 117; Figure 15 As shown, after the planarization treatment, the second isolation material layer 117 is etched back so that the top of the remaining second isolation material layer 117 is flush with the top of the second fin 112 of the first device area 100A, and the remaining second isolation material layer 117 located in the first device area 100A serves as the second isolation layer 118.

[0130] It should be noted that in order to ensure uniform insulation between the semiconductor structures in the first device area 100A and the second device area 100B, the material of the second isolation layer 118 is the same as that of the first isolation layer 110. For this purpose, as an example, the material of the second isolation layer 118 is silicon oxide.

[0131] refer to Figure 16 , remove the protective layer 109.

[0132] Removing the protection layer 109 provides space for the subsequent formation of a gate structure.

[0133] In this embodiment, after the second isolation material layer 117 is etched back, the protection layer 109 is removed, thereby protecting the first channel fin 102 and the second channel fin 116 during the process of etching back the second isolation material layer 117 .

[0134] In this embodiment, the process of removing the protective layer 109 is a wet etching process.

[0135] The wet etching process has the characteristics of strong etching target, high etching efficiency, strong lateral etching ability, and little damage to the channel. In the step of removing the protective layer 109, the probability of damage to the first channel fin 102, the second channel fin 116 and the first fin 101 can be reduced.

[0136] It should be noted that the process of removing the protection layer 109 also includes: removing the etch stop layer 104 .

[0137] refer to Figures 17 and 18After removing the protective layer 109, it also includes: forming a dummy gate structure 121 across the first channel fin 102 and the second channel fin 116 in the first device area 100A and the second device area 100B, in the first device area 100A, the dummy gate structure 121 covers part of the top, part of the sidewall and part of the bottom of the first channel fin 102, and in the second device area 100B, the dummy gate structure 121 covers part of the top, part of the sidewall and part of the bottom of the second channel fin 116.

[0138] The dummy gate structure 121 occupies a space for a gate structure to be formed subsequently.

[0139] In this embodiment, the dummy gate structure 121 is a polysilicon gate structure, that is, the dummy gate structure 103 includes a dummy gate layer, and the material of the dummy gate layer is polysilicon.

[0140] In other embodiments, the material of the dummy gate layer may also be other materials such as amorphous carbon, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon carbon oxynitride.

[0141] In this embodiment, after forming the dummy gate structure 121 , the method further includes forming a spacer 120 on the sidewall of the dummy gate structure 121 .

[0142] The sidewall spacer 120 is used to define the formation area of ​​the length of the subsequently formed gate structure (not shown). The sidewall spacer 120 is also used to protect the sidewalls of the subsequently formed gate structure. The sidewall spacer 120 can be a single-layer structure or a stacked structure. The material of the sidewall spacer 120 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 120 is a single-layer structure and is made of silicon nitride.

[0143] In this embodiment, after forming the spacer 120 , the method further includes forming an interlayer dielectric layer 122 on the isolation layer exposed by the spacer 120 and the dummy gate structure 121 .

[0144] The interlayer dielectric layer 122 is used to isolate adjacent devices. The material of the interlayer dielectric layer 122 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 122 is silicon oxide.

[0145] Continue to refer Figure 17It should be noted that before forming the dummy gate structure 121, it also includes: forming a gate oxide layer 119 on the sidewalls of the first fin 101, the top and sidewalls of the first channel fin 102, the sidewalls of the second channel fin 112, the top and sidewalls of the second channel fin 116, and the top of the isolation layer.

[0146] During the subsequent removal of the dummy gate structure 121 , the gate oxide layer 119 protects the first channel fin 102 and the first fin 101 exposed by the second isolation layer 118 in the first device region, and the second channel fin 116 and the second fin 112 exposed by the first isolation layer 110 in the second device region.

[0147] refer to Figures 19 to 20 , the dummy gate structure 121 and the gate oxide layer 119 are removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 122 .

[0148] Specifically, the dummy gate structure 121 and the gate oxide layer 119 are removed to provide space for the subsequent formation of the gate structure.

[0149] In this embodiment, the gate oxide layer 119 is first used as an etching stop position to remove the dummy gate structure 121 , and then the gate oxide layer 119 is removed.

[0150] In this embodiment, the dummy gate structure 121 and the gate oxide layer 119 are removed by a dry etching process.

[0151] refer to Figures 21 to 24 , the second fin 112 in the second device region 100B and the first fin 101 in the first device region 100A are removed.

[0152] Specifically, the second fin 112 in the second device area 100B and the first fin 101 in the first device area 100A are removed, so that the first channel fin 102 in the first device area 100A and the second channel fin 116 in the second device area 100B respectively meet the carrier mobility requirements of the first-type transistor and the second-type transistor, so as to respectively meet the performance requirements of the first-type transistor and the second-type transistor, thereby improving the performance of the semiconductor structure.

[0153] In this embodiment, the second fins 112 in the second device region 100B are removed first, and then the first fins 101 in the first device region 100A are removed. In other embodiments, the first fins 101 in the first device region 100A may be removed first, and then the second fins 112 in the second device region 100B are removed.

[0154] The mask layer 106 used in the aforementioned doping treatment of the isolation material layer 105 of the second device region 100B is used as the first mask layer 106. In this embodiment, the step of removing the second fin 112 in the second device region 100B includes: Figure 21 As shown, a second mask layer 126 is formed in the first device region 100A to cover the top and sidewalls of the first channel fin 102 and the first fin 101; Figure 22 As shown, after the second mask layer 126 is formed, the second fin 112 in the second device region 100B is removed.

[0155] In this embodiment, the process of removing the second fin 112 in the second device region 100B includes a wet etching process.

[0156] It should be noted that a wet etching process is used to remove the second fin 112. The wet etching process is an isotropic process that has a high etching rate, is simple to operate, and has low process costs. The material of the second fin 112 is SiGe, and accordingly, the etching solution used in the wet etching process is a hydrogen chloride solution.

[0157] In this embodiment, after the second fin 112 of the second device region 100B is removed, the second mask layer 126 is removed.

[0158] In this embodiment, the step of removing the first fin 101 in the first device region 100A includes: Figure 23 As shown, a third mask layer 127 surrounding the second channel fin 116 is formed in the second device region 100B; Figure 24 As shown, after the third mask layer 127 is formed, the second fin 112 in the first device region 100A is removed.

[0159] In this embodiment, the process of removing the first fin 101 in the first device region 100A includes a wet etching process.

[0160] It should be noted that a wet etching process is used to remove the first fin 101. The wet etching process is an isotropic process that has a high etching rate, is simple to operate, and has low process costs. The material of the first fin 101 is Si, and accordingly, the etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution.

[0161] In this embodiment, after removing the second fin 112 in the first device region 100A, the method further includes: removing the third mask layer 127 .

[0162] Specifically, the process of removing the third mask layer 127 includes an ashing process.

[0163] refer to Figure 25 After removing the second fin 112 in the second device region 100B and the first fin 101 in the first device region 100A, a gate structure 128 is formed on top of the isolation layer, spanning the first channel fin 102 and the second channel fin 116. In the first device region 100A, the gate structure 128 surrounds and covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the first channel fin 102. In the second device region 100B, the gate structure 128 surrounds and covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the second channel fin 116.

[0164] Specifically, when the device is operating, the gate structure 128 is used to control the opening or closing of the conductive channels of the first-type transistor in the first device region 100A and the second-type transistor in the second device region 100B.

[0165] In this embodiment, the gate structure 128 includes a gate dielectric layer (not labeled) and a gate electrode layer (not labeled) covering the gate dielectric layer.

[0166] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0167] Specifically, in the first device region 100A, the gate dielectric layer surrounds and covers part of the top, part of the sidewall and part of the bottom of the first channel fin 102, and in the second device region, the gate dielectric layer surrounds and covers part of the top, part of the sidewall and part of the bottom of the second channel fin.

[0168] In this embodiment, a gate electrode layer is formed on top of the isolation layer, spanning the first channel fin 102 and the second channel fin 116 . The gate electrode layer surrounds and covers the gate dielectric layer.

[0169] The gate electrode layer is used for subsequent electrical connection to external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.

[0170] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor; a first fin protruding from the top of the substrate, wherein a top of the first fin in the first device region is lower than a top of the first fin in the second device region; A second fin portion is located on top of the first fin portion in the first device region, the top of the second fin portion is flush with the top of the first fin portion in the second device region, and the second fin portion and the first fin portion are made of different materials; an isolation layer, located on the substrate where the first and second fins are exposed, the isolation layer covering sidewalls of the first and second fins; a first channel fin portion, located on top of the second fin portion in the first device region and spaced apart from the second fin portion in a longitudinal direction; a second channel fin portion, located on top of the first fin portion in the second device region and spaced apart from the first fin portion in a longitudinal direction, wherein the second channel fin portion and the first channel fin portion are made of different materials; A gate structure is located on top of the isolation layer and spans the first channel fin and the second channel fin, the gate structure including a gate dielectric layer and a gate electrode layer covering the gate dielectric layer, wherein in the first device region, the gate dielectric layer surrounds and covers a portion of the top, a portion of the sidewall and a portion of the bottom of the first channel fin, and in the second device region, the gate dielectric layer surrounds and covers a portion of the top, a portion of the sidewall and a portion of the bottom of the second channel fin.

2. The semiconductor structure according to claim 1, wherein The isolation layer includes: a first isolation layer located on the substrate of the first device region and the second device region, the first isolation layer covering the sidewall of the first fin and exposing the sidewall of the second fin; The second isolation layer is located on top of the first isolation layer in the first device region, the second isolation layer covers the sidewalls of the second fin, and the top of the second isolation layer is flush with the top of the first isolation layer in the second device region.

3. The semiconductor structure according to claim 1, wherein: A bottom surface of the first channel fin is flush with a bottom surface of the second channel fin.

4. The semiconductor structure according to claim 1, wherein: The material of the first fin includes one or both of Si and SiC; The material of the second fin includes one or more of SiGe, Ge or III-V semiconductor materials; the material of the first channel fin includes one or more of SiGe, Ge or III-V semiconductor materials; the material of the second channel fin includes one or both of Si and SiC.

5. The semiconductor structure according to claim 1, wherein The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

6. The semiconductor structure according to claim 1, wherein The first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, a protruding first fin formed on a top of the substrate, a first channel fin formed on a top of the first fin in the first device region, the first channel fin and the first fin being made of different materials, and a top of the first channel fin being flush with a top of the first fin in the second device region; forming an initial isolation layer on top of the substrate, wherein the initial isolation layer covers a portion of the sidewall of the first fin, and a top of the initial isolation layer in the second device region is higher than a top of the initial isolation layer in the first device region; forming a protective layer on sidewalls of the first fin and the first channel fin exposed by the initial isolation layer; After forming the protection layer, removing a portion of the initial isolation layer to expose a portion of the sidewall of the first fin, and the remaining initial isolation layer serves as the first isolation layer; performing a modification process on the first fin portion exposed by the first isolation layer and the protective layer to convert the first fin portion exposed by the first isolation layer and the protective layer into a second fin portion, and in the second device region, the remaining first fin portion located on top of the second fin portion serves as a second channel fin portion; forming a second isolation layer on top of the first isolation layer in the first device region, wherein the second isolation layer covers the sidewalls of the second fin, and a top of the second isolation layer is flush with a top of the first isolation layer in the second device region, wherein the second isolation layer and the first isolation layer constitute an isolation layer; removing the protective layer; After removing the protective layer, removing the second fin in the second device region and the first fin in the first device region; After removing the second fin in the second device region and the first fin in the first device region, a gate structure spanning the first channel fin and the second channel fin is formed on top of the isolation layer. In the first device region, the gate structure surrounds and covers part of the top, part of the sidewall and part of the bottom of the first channel fin. In the second device region, the gate structure surrounds and covers part of the top, part of the sidewall and part of the bottom of the second channel fin.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming an initial isolation layer on top of the substrate includes: forming an isolation material layer on the substrate where the first fin and the first channel fin are exposed, wherein the isolation material layer covers the sidewalls of the first fin and the first channel fin; performing a doping treatment on a portion of the thickness of the isolation material layer in the second device region, wherein the doping treatment is used to improve the etching resistance of the isolation material layer; After the doping process, the isolation material layer in the first device region and the second device region is etched back to expose part of the sidewall of the first fin in the first device region and the second device region, and the remaining isolation material layer serves as the initial isolation layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of doping a partial thickness isolation material layer in the second device region includes: forming a mask layer on top of the isolation material layer and the first channel fin in the first device region; using the mask layer as a mask, doping the isolation material layer in the second device region; and removing the mask layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: The process of performing doping treatment on a partial thickness of the isolation material layer in the second device region includes an ion implantation process.

11. The method for forming a semiconductor structure according to claim 10, wherein: The parameters of the ion implantation process include: the implanted ions include one or more of Si, N, Cl, P and B ions; the ion implantation energy range is 1.0kev to 6.0kev; the ion implantation dose range is 1.0E15atom / cm 2 to 2.0E16atom / cm 2 .

12. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming an initial isolation layer on the top of the substrate, a top of the initial isolation layer in the second device region is flush with a bottom of the first channel fin in the first device region.

13. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming an initial isolation layer on the top of the substrate, a height difference between the tops of the initial isolation layer in the second device region and the initial isolation layer in the first device region is 20 angstroms to 200 angstroms.

14. The method for forming a semiconductor structure according to claim 7, wherein: In the step of removing a portion of the thickness of the initial isolation layer, the amount of thickness of the initial isolation layer removed is equal to the height difference between the top of the initial isolation layer in the second device region and the top of the initial isolation layer in the first device region.

15. The method for forming a semiconductor structure according to claim 7, wherein: The step of modifying the first fin portion exposed by the first isolation layer and the protective layer includes: forming a diffusion layer on the sidewall of the first fin portion exposed by the first isolation layer and the protective layer; An annealing process is performed on the diffusion layer and the first fin to allow ions in the diffusion layer to diffuse laterally into the first fin, and to transform the first fin exposed by the first isolation layer and the protection layer into a second fin.

16. The method for forming a semiconductor structure according to claim 15, wherein: The process of forming the diffusion layer on the sidewall of the first fin exposed by the first isolation layer and the protection layer includes an epitaxial process.

17. The method for forming a semiconductor structure according to claim 15, wherein: The annealing process performed on the diffusion layer and the first fin includes a rapid thermal annealing process.

18. The method for forming a semiconductor structure according to claim 15, wherein: The parameters of the annealing process include: a process temperature of 600° C. to 1200° C.; and a process time of 1 minute to 120 minutes.

19. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming a second isolation layer on top of the first isolation layer in the first device region includes: forming a second isolation material layer on top of the first isolation layer, wherein the second isolation material layer covers the sidewalls of the second fin and the top and sidewalls of the protection layer; performing a planarization process on the second isolation material layer with the top of the protective layer as a stop position; After the planarization process, the second isolation material layer is etched back so that the top of the remaining second isolation material layer is flush with the top of the second fin in the first device region, and the remaining second isolation material layer in the first device region serves as the second isolation layer.

20. The method for forming a semiconductor structure according to claim 7, wherein: The process of removing the second fin in the second device region includes a wet etching process; The process of removing the first fin in the first device region includes a wet etching process.

21. The method for forming a semiconductor structure according to claim 7, wherein: In the step of providing the substrate, the material of the first fin includes one or both of Si and SiC; the material of the first channel fin includes one or more of SiGe, Ge and Group III-V semiconductor materials; In the step of modifying the first fin exposed by the first isolation layer and the protection layer, the material of the second fin includes one or more of SiGe, Ge and Group III-V semiconductor materials.

22. The method for forming a semiconductor structure according to claim 7, wherein: In the step of providing a substrate, the first-type transistor is used to form a PMOS transistor, and the second-type transistor is used to form an NMOS transistor.

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