Micro-stepping control circuit, control method and stepping motor system

Abstract

The present invention relates to a micro-stepping control circuit, a control method, and a stepping motor system. A device according to the present invention includes: a current generator having a current output; a transistor coupled between the current output and a ground terminal, the transistor having a control terminal and a first current terminal coupled to the current output; an offset generation circuit having an offset control input, a voltage input, and an offset voltage output, the voltage input being coupled to the first current terminal; a comparator having a comparator output and first and second comparator inputs, the first comparator input being coupled to the voltage sensing terminal, and the second comparator input being coupled to the offset voltage output; and a pulse width modulation (PWM) circuit having a control input and a PWM output, the control input being coupled to the comparator output, and the PWM output being coupled to the control terminal.

Description

[0001] This application is a divisional application of the invention patent application with the application date of October 17, 2017, application number "201780064171.2", and invention name "Micro-stepping control circuit, control method and stepping motor system". Background Art

[0002] Controllers (including processors) are increasingly used to control the movement of physical devices such as motors and robots. Controllers control the movement of such physical devices, for example, by controlling stepper motors. Various applications for stepper motors increasingly require greater precision and control of stepper motors. Stepper motors are controlled by regulating the amount of current applied to the stepper motor. However, there are many sources of current regulation inaccuracy, and not all of these sources can be compensated for when manufacturing control circuits for controlling stepper motors. Summary of the Invention

[0003] In the described example, a stepper motor error reduction control system includes first and second power switches that energize and de-energize a stepper motor coil, respectively, during each cycle for pulse width modulating (PWM) the coil current. During a cycle including zero-crossing microstepping, a calibrator detects a type of body diode effect occurring in the second power switch when the second switch stops de-energizing the coil. A selected bias is adjusted in response to the detected type of body diode effect of the second power switch. By adjusting the selected bias, a triggering time for comparing a bias reference voltage with a motor voltage generated in response to the coil current is controlled. By incrementally adjusting the selected bias over successive cycles (which adjusts the voltage of the bias reference), component delays in the PWM control loop are compensated for and errors, such as those caused by process, voltage, and temperature variations, are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An illustrative computing device 100 is shown in accordance with an example embodiment.

[0005] Figure 2 is a schematic diagram of a circuit for peak current regulation in stepper motor error reduction according to an example embodiment.

[0006] Figure 3 is a waveform diagram of a stepper motor control current for stepper motor error reduction according to an example embodiment.

[0007] Figure 4 is a waveform graph 400 illustrating the peak current error percentage for each peak current in a conventional stepper motor controller.

[0008] Figure 5is a waveform diagram 500 of a single cycle of a relatively high stepper motor control current for stepper motor error reduction according to an example embodiment.

[0009] Figure 6 is a waveform diagram 600 of a single cycle of a relatively low stepper motor control current for stepper motor error reduction according to an example embodiment.

[0010] Figure 7 is a waveform graph 700 illustrating the effects of stepper motor inductance and output voltage variables on the slew rate of motor control current for stepper motor error reduction, according to an example embodiment.

[0011] Figure 8 is a waveform diagram 800 illustrating loop delay timing information extraction for stepper motor error reduction according to an example embodiment.

[0012] Figure 9 is a waveform diagram 900 of loop delay timing information illustrating an overshoot condition according to an example embodiment.

[0013] Figure 10 is a waveform diagram 1000 illustrating loop delay timing information for an undershoot condition according to an example embodiment.

[0014] Figure 11 is a waveform diagram 1100 illustrating loop delay timing information extraction for stepper motor error reduction according to an example embodiment.

[0015] Figure 12 is a waveform graph 1200 illustrating error reduction during a zero-crossing calibration routine for stepper motor error reduction according to an example embodiment.

[0016] Figure 13 is a waveform graph 1300 illustrating a comparison of the degree of current error between a simulation of a stepper motor without calibration and a simulation of a stepper motor using stepper motor error reduction, according to an example embodiment.

[0017] FIG. 14 is a waveform graph 1400 illustrating the relative extent of voltage error in a simulation of a stepper motor without calibration at various levels of coil inductance.

[0018] Figure 15 is a waveform graph 1500 illustrating a comparison of the extent of current error for a stepper motor at different coil inductances and using a simulation of stepper motor error reduction, according to an example embodiment. DETAILED DESCRIPTION

[0019] In this specification, a system can be a subsystem of another system. Furthermore, the terms "coupled to" and "coupled with..." (and similar terms) describe either an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, that connection can be through a direct electrical connection or through an indirect electrical connection via other devices and connections. The term "portion" can mean the entire portion or a portion of the entire portion.

[0020] Figure 1 An illustrative computing device 100 is shown in accordance with an example embodiment. For example, computing device 100 is or is incorporated into an electronic system 129, such as a computer, an electronics control "box" or module, robotic equipment (including stationary or mobile), an automobile, or any other type of system in which a computer controls a physical device.

[0021] In some embodiments, computing device 100 comprises a mainframe or system-on-a-chip (SoC) that includes logic control components such as a CPU 112 (central processing unit), storage 114 (e.g., random access memory (RAM)), and a power supply 110. For example, CPU 112 may be a CISC-type (complex instruction set computer) CPU, a RISC-type CPU (reduced instruction set computer), an MCU-type (microcontroller unit), or a digital signal processor (DSP). CPU 112 includes functionality provided by discrete logic components and / or arranged to execute application-specific instructions (e.g., software or firmware) that, when executed by CPU 112, transform CPU 112 into a special-purpose machine. The imaginary "divide" between hardware and software is a design choice that varies (e.g., selectively) depending on various trade-offs including cost, power dissipation, reliability, time to market, and the like. Accordingly, any software functionality used to control one or more CPUs 112 of computing system 100 may be fully implemented in hardware (e.g., given sufficient time and resources for design and production).

[0022] The CPU 112 includes memory and logic to store information frequently accessed from (e.g., written to and / or read from) a storage device 114. The computing device 100 is typically user-controlled using a UI (user interface) 116, which provides output to the user and receives input from the user during execution of software applications 130. Output is provided using a display 118, which includes indicators (e.g., indicator lights, speakers, vibrators, and the like) and controls. Input is received using audio and / or video input (e.g., using voice or image recognition) and electrical and / or mechanical devices (e.g., keypads, switches, proximity detectors, gyroscopes, accelerometers, parsers, and the like).

[0023] CPU 112 is coupled to I / O (input-output) port 128, which provides an interface configured to receive input from (and / or provide output to) a network connection device 131. Network connection device 131 may include any device capable of point-to-point and / or network-connected communication with computing device 100 (including a "Bluetooth" unit electronically paired with computing device 100). Computing device 100 is optionally coupled to peripheral devices and / or computing devices, including tangible, non-transitory media (e.g., flash memory) and / or cable or wireless media. These and other input and output devices are selectively coupled to computing device 100 via external devices using wireless or cable connections. Storage device 114 may be accessed, for example, via network connection device 131. CPU 112, storage device 114, and power supply 110 may be coupled to an external power source (not shown) or to a local power source (e.g., a battery, solar cell, alternator, induction field, fuel cell, capacitor, and the like).

[0024] The storage device 114 (which may be a memory such as an on-processor cache, an off-processor cache, RAM, flash memory, data registers, flip-flops, disk storage, and the like) stores one or more software applications 130 (e.g., embedded applications) that, when executed by the CPU 112, transform the computing device 100 into a special-purpose machine suitable for performing one or more target functions, such as stepper motor error correction.

[0025] The computing system 100 includes a microstepping controller (microstepper) 138 configured to control a stepper motor (e.g., motor 204, described below). The microstepper 138 is configured to control stepper motors, as various applications for stepper motors increasingly require greater precision and control of stepper motors, requiring finer and more precise motor movement. Controlling finer and more precise motor movement results in higher levels of microstepping, where the smaller the microstep (e.g., the offset between microsteps), the higher the resolution of stepper positioning. As described herein, a zero-crossing calibrator 140 is configured to calibrate portions of the microstepper 138 at selected times, for example, so that the microstepper 138 achieves smaller microsteps with higher precision for current regulation and positioning of the motor in real space.

[0026] Stepper motor drive circuits typically perform peak current regulation for driving and / or controlling the current of a stepper motor. However, the drive circuits used to perform peak current regulation are often manufactured with circuit device variations, wherein these variations often result in reduced accuracy (e.g., errors) in controlling the stepper motor. Sources of factory "trimming" errors in peak current include bias errors in the reference voltage and the comparator used to compare the reference voltage between the drive FET and the sense FET, FET (field effect transistor) variations (e.g., mismatches), and errors in the circuits used to generate the reference voltage and reference current.

[0027] However, peak current regulation errors also arise from differences in the electrical characteristics of components supplied by the end user and / or selected by the customer (collectively referred to as user-supplied components). User-supplied components typically have variations in motor inductance and variations in the voltage of the motor voltage output (which are typically unknown to the factory that manufactures the motor drive circuit) and, accordingly, are typically not factory-trimmed. Variations in motor inductance and voltage output affect the accuracy of the drive current (e.g., as described below with reference to equation (2)).

[0028] Peak current regulation circuitry is typically arranged as a feedback loop. Accordingly, errors in the end-user system caused by motor-related variations (e.g., in motor inductance and motor voltage supply) contribute substantially to regulation errors, as the peak current consumed by the motor is used to control the motor itself in the feedback loop. Delays in the feedback loop slow the speed at which control errors can be corrected (and / or regulated). Control loop delays include current sensing voltage amplifier and comparator bias delays, deglitching periods (e.g., time allowed to help voltage transients settle), digital control logic delays, and switching periods of the FET power drivers.

[0029] Figure 2 is a schematic diagram of a circuit for peak current regulation in stepper motor error reduction according to an example embodiment. The zero-crossing calibration microstepper 200 is a microstepper such as the microstepper 138 described above. The zero-crossing calibration microstepper 200 includes an "H-bridge" (e.g., so named based on its generally depicted schematic shape) 210, a first direction (e.g., forward) microstepper control circuit 220, and a second direction (e.g., reverse) microstepper control circuit 260. The H-bridge 210 is selectively driven under the control of a switch controller 206 (which, in turn, is controlled in response to the microstepper control circuits 220 and 260).

[0030] In operation, the zero-crossing calibration microstepper 200 is arranged to controllably drive (e.g., step) the coil 202 via an "H-bridge" 210. The microstepper control circuit 220 is arranged to controllably drive the coil 202 (and, in turn, the motor 204) in a first direction by alternately driving a first pair of NMOS (N-type metal oxide semiconductor) FETs (field effect transistors) 214 and 218. The source of the upper FET 214 is coupled to the drain of the lower FET 218 and to a first terminal of the (e.g., motor) coil 202, wherein a second terminal of the coil 202 is switchably coupled to ground via an opposing (e.g., opposite side of the H-bridge 210) lower FET 216. When the motor 204 is driven in the first direction, the opposing lower FET 216 is driven (e.g., to switchably turn off the opposing lower FET 216) to couple the second terminal of the coil 202 to ground. The coil 202 is selectively energized by turning off the upper FET 214 for a first selected time (where the selected time is selected based on the inductance of the coil 202, the voltage generated across the coil 202, and the desired degree of rotation of the motor 204). At the end of the first selected time, the upper FET 214 is turned on (e.g., by reducing the gate voltage of the upper FET 214) and the lower FET 218 is selectively turned off (e.g., de-energizing the coil 202 so that the motor 204 is no longer inductively driven). The lower FET 218 is selectively turned off in response to a first PWM (pulse width modulation) signal generated by the microstepper control circuit 220.

[0031] Accordingly, in response to asserting the first control signal, the first power switch 214 is operable to selectively couple the coil current to energize the stepper motor coil 202, and in response to asserting the second control signal, the second power switch 218 is operable to selectively couple the coil current to de-energize the stepper motor coil 202, wherein the second control signal is one of asserted and de-asserted in response to comparing the bias reference voltage to the motor voltage.

[0032] In a similar manner, the microstepper control circuit 260 is arranged to controllably drive the coil 202 in a second direction (opposite to the first direction) by alternately driving a second pair of FETs 212 and 218. The source of the upper FET 212 is coupled to the drain of the lower FET 216 and to the second terminal of the (e.g., motor) coil 202, wherein the first terminal of the coil 202 is switchably coupled to ground via the opposing lower FET 218 (e.g., on the opposite side of the H-bridge 210). When driving the motor 204 in the second direction, the opposing lower FET 216 is turned off to couple the first terminal of the coil 202 to ground. By turning off the upper FET 212 for selected times, the coil 202 is selectively energized. At the end of the selected time, the upper FET 212 is turned on and the lower FET 216 is selectively turned off (e.g., de-energizing the coil 202 so that the motor 204 is no longer inductively driven). In response to a second PWM signal generated by the microstepper control circuit 260 , the lower FET 216 is selectively turned off.

[0033] The switch controller 206 is arranged to selectively drive (e.g., logic level to drive level) the buffers of the H-bridge so that current flows through the coil 202 in a selected direction. For example, in response to a first PWM signal (e.g., for driving the gate of the FET 218), the microstepper control circuit 220 drives the coil 202 in a first direction by driving the buffer 278 (e.g., to ground the second terminal of the coil 202), driving the buffer 240 (e.g., to energize the coil 202), and selectively driving the buffer 238 (e.g., to de-energize the coil). Similarly, in response to a second PWM signal (e.g., for driving the gate of the FET 216), the microstepper control circuit 260 drives the coil 202 in a second direction (e.g., opposite to the first direction) by driving the buffer 238 (e.g., to ground the second terminal of the coil 202), driving the buffer 280 (e.g., to energize the coil 202), and selectively driving the buffer 278 (e.g., to de-energize the coil).

[0034] The microstepper control circuit 220 can controllably drive the coil 202 in a first direction by generating and asserting a first PWM signal (e.g., applied to the buffer 238). The first PWM signal is a feedback control signal of a feedback loop, such that the microstepper control circuit 220 measures the output of the motor 204 (e.g., the current from the coil 202 that converts the voltage across the drain-to-source voltage of the emulation FET 224) to generate the first PWM signal for controlling the motor 204.

[0035] The comparator 230 is arranged to generate a first PWM signal, for example, in response to comparing the coil 202 output voltage (e.g., sense voltage VSNS) with a first selected emulated voltage. For example, the sense voltage VSNS signal is a drain-to-source voltage generated at the drain of the FET 218 in response to the coil 202 controlling current to flow through the FET 218. The first selected emulated voltage is generated, for example, by programming (e.g., in response to a processor, such as the CPU 112, which is arranged to control programmable components of the zero-crossing calibrated microstepper 200) the sine DAC (digital-to-analog converter) current generator 222 to generate a programmably selected output current. The programmably selected output current is associated with the microstepping position, for example, with respect to the microstepping position hereinafter. Figure 8 The programmably selected output current is converted to a first selected emulated voltage by generating a drain-to-source voltage (VDS) across the emulation FET 224 in response to the programmably selected output current.

[0036] Accordingly, the first selected reference current is applied to the drain of reference transistor 224 such that when buffer 236 is driven (e.g., controlled in response to the first PWM signal), a first emulated voltage is generated at the drain of FET 224. FET 224 is formed in a manner that is structurally and chemically similar to FET 218 (which forms emulation circuit 226) such that PVT variations of FET 224 are similar to PVT variations of FET 218 (such that operational fluctuations caused by PVT are removed by the operation of common-mode subtraction of comparator 230) and emulates the functionality of FET 218 (e.g., without affecting the operation of FET 218 itself in performing measurements).

[0037] The bias DAC 228 is configured to selectively bias the first emulated voltage in response to a code (e.g., indicating an amount of bias) received from a digital calibrator (DIG CAL) 234. As described herein, the digital calibrator 234 determines an optimized bias for the first emulated voltage by determining whether overshoot and / or undershoot occur, e.g., in response to a series of selectively adjusted biased emulated voltages. For example, a search (e.g., linear or binary) for determining a zero crossing of the coil 202 control current is performed by progressively and selectively adjusting a control loop delay (e.g., by programmatically adjusting the amount of bias of the first emulated voltage) for successive coil 202 cycles so as to determine a narrower and narrower time window in which the coil 202 control current zero crossing occurs. The use of a specific bias that causes an overshoot condition, rather than (e.g., closest to) an undershoot condition, minimizes the length of time during which undershoot or overshoot occurs in successive cycles and / or steps (e.g., microstepping) of the motor 204.

[0038] The digital calibrator 234 is arranged to determine whether overshoot or undershoot occurs in a particular cycle (e.g., during a narrow window around the search zero crossing) by examining the body diode effect of the lower FET 218. Figure 9 and Figure 10 As described, sensing the voltage signal implements a positive body diode (218a or 216a) when coil 202 controls current overshoot or implements a negative body diode when coil 202 controls current undershoot (e.g., where coil 202 controls current change direction at zero crossing).

[0039] In response to determining whether an overshoot or undershoot has occurred (e.g., during a calibration routine for finding an optimized offset), the digital calibrator 234 generates code indicating a control loop delay for compensating for the control loop to generate a voltage offset for the first PWM signal. The digital calibrator 234 operates in response to control circuitry (e.g., a processor and / or other programmable components of the zero-crossing calibrated microstepper 200). For example, under such control, the digital calibrator 234 can be used to effectively measure the timing of the result of the comparator 230 (as described below) by continuously adjusting the selected offset in response to the undershoot / overshoot determination. In response to the undershoot / overshoot determination, the offset DAC 228 generates (e.g., a selectively adjusted) offset emulation voltage that adjusts the timing of the first PWM signal to compensate for the control loop delay. Accordingly, the calibrator 234 is operable to detect a body diode (e.g., 218a) effect of the second power switch 218 occurring in response to deasserting the second power switch 218 and to adjust the selected bias (e.g., Figure 12 1202).

[0040] Comparator 230 is arranged to compare a first bias emulation (e.g., reference) voltage with a motor voltage VSNS generated in response to the coil current (e.g., FET 218 VDS generated in response to the coil 202 current output) to generate an "ITRIP" current control signal for controlling PWM generator 232. As described herein, a change in the bias of the first bias emulation voltage determines a corresponding change in the timing (e.g., earlier or later) of the assertion of the ITRIP signal. Digital calibrator 234 is arranged to measure (e.g., via comparator 230) the behavior of the coil 202 output current relative to the amount of peak current generated in response to the zero crossing. In response to the measured behavior, digital calibrator 234 is arranged to determine a bias code for changing the timing of the ITRIP trigger level. For example, the bias code is determined to selectively control loop delay (which typically causes overshoot of current that results in motor positioning errors) to help minimize the extent and occurrence of undershoot and overshoot of the coil 202 output current, which typically cause inaccuracies in the controlled (e.g., stepping) coil 202.

[0041] In a manner similar to microstepper control circuit 220, microstepper control circuit 260 controllably drives coil 202 in a second direction (e.g., opposite the first direction). Accordingly, microstepper control circuit 260 is arranged to generate and assert a second PWM signal (e.g., applied to buffer 278). The second PWM signal is generated, for example, in response to comparing the VDS of FET 216 (generated in response to coil 202 output current) with a second bias emulated voltage. The second bias emulated voltage is generated, for example, by programming a sinusoidal DAC reference current generator to output a second selected reference current. The second selected reference current is applied to the drain of reference transistor 264, such that when buffer 276 is driven (e.g., under control of the second PWM signal), a second emulated voltage is generated at the drain of FET 264. FET 264 is formed in a manner structurally and chemically similar to FET 216 (e.g., such that the PVT variations of FET 264 are similar to those of FET 216), and emulates the functionality of FET 216.

[0042] The second emulated voltage is applied to the input of the bias DAC 268, such that the second bias emulated voltage is generated in response to the second emulated voltage and a selected (e.g., programmably adjustable) bias. The second bias emulated voltage is selectively biased, for example, in response to the selected microstepping and the measured behavior of the coil 202 output current.

[0043] The second bias emulation voltage is compared to the VDS of the FET 216 (generated in response to the coil 202 output current) to generate an "Itrip" current control signal for controlling the PWM generator 272. The digital calibrator 274 is arranged to measure (e.g., via the comparator 270) the behavior of the coil 202 output current (e.g., the amount of peak current generated in response to zero crossings). In response to the measured behavior, the digital calibrator 274 is arranged to determine a bias (e.g., a compensation trigger point) for changing the timing of the Itrip level. By controlling the voltage (and timing) of the compensation trigger point, it controls the loop delay (e.g., of the microstepper control circuit 260) to help avoid undershoot and overshoot of the coil 202 output current.

[0044] Figure 3 3 is a waveform diagram of a stepper motor control current for stepper motor error reduction according to an example embodiment. Current waveform 300 is shown with waveform portions 310 and 312 of a rising stepper motor control current (e.g., flowing through coil 202). As waveform portion 312 rises (and the coil 202 is energized with a first polarity), the level of the stepper motor control current rises above a target threshold 322 (e.g., a selected peak level of current associated with a selected microstepping level). Ideally, the FET driver transistor (e.g., lower FET 218) will turn on (e.g., switch to a conductive state) immediately when waveform portion 312 reaches the target threshold 322 (e.g., causing the forward stepper motor control current to decrease).

[0045] However, a delay period 326 (e.g., as described above) of the control loop, resulting from a time delay in the control loop before the lower FET (e.g., FET 218), is activated. For example, during the delay period 326, the stepper motor control current continues to increase, as indicated by the waveform portion 310. After the delay period 326 (e.g., during which the result of the comparison has propagated through the circuitry used to control the lower FET), the lower FET turns on at point 324 (e.g., representing the peak current). When the lower FET turns on, the stepper motor control current begins to decrease (e.g., fall) in response to the de-energization of the coil 202, as illustrated by the waveform portion 314. The peak current overshoot of the stepper motor control current above the target threshold 322 is treated as an error having a magnitude illustrated as error 338 (e.g., because the overshoot causes inaccuracies in positioning the coil 202).

[0046] When the waveform portion 314 is below a lower threshold (e.g., a zero reference level, such as the reference level hereinafter) Figure 5 and Figure 8322 ) , the comparator detects the presence of a stepper motor current across the coil 202 and turns off the lower FET transistor. In response to the lower FET transistor being turned off, the waveform portion 316 (e.g., the stepper motor control current flowing through the coil 202) rises, and the level of the stepper motor control current rises above the target threshold 322. The waveform portion 316 has a slope 328 (e.g., instantaneous rate, slew rate, first derivative, and the like) according to the following equation:

[0047]

[0048] Where i is the stepper motor control current, t is time, V is the stepper motor control voltage, and L is the inductance of the stepper motor. Accordingly, the slope 328 is determined in response to the inductance and resulting voltage of the motor selected by the customer.

[0049] The delay period 326 of the control loop also contributes to the overshoot of the motor control current. As described herein, the delay 326 can be shortened according to equation (1). For example, by adding a (e.g., voltage) offset (via the offset DAC 228) to the comparison voltage at the inverting input of the comparator (e.g., comparator 230), the comparator is forced to switch (e.g., causing the falling segment 318) at an earlier time than otherwise. As described below with reference to Figure 9 As described, the voltage generated by the motor control current is inversely related to the motor control current, for example, during waveform portions 312, 310, and 316, such that a higher bias compensates for loop delay (e.g., causes a reduction in loop delay). The shortened loop delay causes less overshoot, as illustrated by error 336 (which is less than error 338). From equation (1), the peak current overshoot (I) of the stepper motor control current can be determined according to the following equation: err ):

[0050]

[0051] Accordingly, reducing loop delay also reduces current errors (eg, peak current overshoot).

[0052] Figure 4 FIG4 is a waveform graph 400 illustrating the peak current error percentage for each peak current in a conventional stepper motor controller. For example, a peak current of approximately one ampere has an associated peak current error of approximately 2%. Similarly, a peak current of approximately 400 milliamperes has an associated peak current error of approximately 5%. However, a peak current of approximately 150 milliamperes has an associated peak current error of greater than 13%. Accordingly, as motors tend to be made smaller and use smaller drive and / or control currents, the resulting peak current errors in conventional circuits adjust at an even higher rate.

[0053] Figure 5 5 is a waveform diagram of a single cycle of a relatively high stepper motor control current for stepper motor error reduction according to an example embodiment. Waveform diagram 500 includes current 510, for example, rising from a zero reference level 502 to a peak level 514 (at which point current 510 reaches a peak current level).

[0054] In response to the rise of the low-side FET gate voltage 540 (which is illustrated as being substantially contemporaneous with the peak level segment 514), the current 510 drops from the peak level 514. For example, the low-side FET gate voltage 540 is asserted in response to the comparator comparing the bias emulation voltage with the voltage generated at the drain of the voltage low-side FET (e.g., as described above with respect to FET 216 and comparator 230). For example, the current 510 drops from the peak level 514 and crosses the zero reference level 502, such that the region 516 represents the sum of the errors of the positive regulation current.

[0055] When the current 510 falls below the zero reference level 502 (and becomes negative at point 520), the comparator detects the crossing and negates (e.g., deasserts) the low-side FET gate voltage 540, which turns off the lower FET transistor at point 522. However, delays in the comparator and pre-driver (e.g., PWM 232 and buffer 238) delay the deassertion (e.g., falling edge) of the low-side FET gate voltage 540 by a delay 524. Accordingly, the delay causes an error in the timing of the zero crossing.

[0056] When the lower FET transistor turns off, current 510 begins to rise from negative peak level 522 to the zero reference 502 level, such that region 526 represents the sum of the errors in the negative regulation current. When the (e.g., negative) current 510 once again reaches the zero reference 502 level, current 510 oscillates (e.g., ringing in response to both the upper and lower FETs turning off).

[0057] Figure 6 FIG6 is a waveform diagram 600 of a single cycle of a relatively low stepper motor control current for stepper motor error reduction according to an example embodiment. The waveform diagram 600 includes a current 610, for example, rising from a zero reference level 602 to a peak level 614 (at which point the current 610 reaches a peak current level). Compared to the current 510, the current 610 has a relatively low peak current, which results in a substantially larger error.

[0058] In response to the rise in the low-side FET gate voltage, current 610 decreases from peak level 614. Current 610 decreases from peak level 614 and crosses zero reference level 602, such that region 616 represents the sum of the errors in the positive regulation current. For example, region 616 is substantially smaller than region 516 due to the lower peak current.

[0059] When current 610 falls below zero reference level 602 (and becomes negative at point 620), the comparator detects the crossing and negates (e.g., deasserts) the low-side FET gate voltage, turning off the lower FET transistor at point 622. When the lower FET transistor turns off, current 610 begins to rise from negative peak level 622 to the zero reference 602 level, such that region 626 represents the sum of the errors in the negative regulation current. Because the negative bias of current 610 (e.g., from point 620 to point 622) is essentially entirely due to the regulation loop, region 626 is proportionally larger (e.g., relative to region 616). Accordingly, at low current levels, zero-crossing detection inaccuracies can cause a zero average current or even a negative average current to be achieved. When the (e.g., negative) current 610 once again reaches the zero reference 602 level, current 610 oscillates (e.g., rings).

[0060] Figure 7 FIG7 is a waveform diagram 700 illustrating the effect of stepper motor inductance and output voltage variables on the slew rate of motor control current for stepper motor error reduction according to an example embodiment. The waveform diagram 700 includes a first inductor current 720 and a second inductor current 730 (e.g., of a motor coil). The first inductor current 720 and the second inductor current 730 are illustrated as having positive slopes such that the first inductor current 720 and the second inductor current 730 are superimposed relative to when the first inductor current 720 and the second inductor current 730 cross (e.g., cross zero) a reference point.

[0061] For example, a first inductor current 720 is generated by a motor having a relatively high motor output voltage (Vm) and a relatively low motor inductance, but a second inductor current 730 is generated by a motor having a relatively low motor output voltage and a relatively high motor inductance. The effect of the stepper motor inductance and output voltage variables on the slew rates of the first and second inductor currents includes the first and second inductor currents reaching the peak current threshold Itrip level 714 at different times.

[0062] For example, the first inductor current 720 reaches the Itrip level 714 at point 724, whereas the second inductor current 730 reaches the Itrip level 714 at point 734. According to an example embodiment, different motor voltages and motor inductors require different trigger point compensations. The trigger point compensation is arranged to control the timing of the FET's shutdown at a point (e.g., a compensation trigger point) at an earlier (and lower) time (and voltage) than the Itrip level, such that the FET is ideally turned off when (e.g., any) inductor current reaches the Itrip level. Accordingly, the first inductor current 720 is associated with a first compensation trigger point 722, which is different from a second compensation trigger point 732 associated with the second inductor current 724. The compensation trigger point varies according to PVT variations and is determined based on zero-crossing timing measurements as described herein (e.g., a run-time calibration routine).

[0063] Figure 8 FIG8 is a waveform diagram 800 illustrating loop delay timing information extraction for stepper motor error reduction, according to an example embodiment. Waveform diagram 800 includes a (e.g., conceptual) sine wave 802 indicating an ideal current for driving a (e.g., ideal) stepper motor through a complete rotation. A complete rotation is divided into various microsteps, each with an associated time delta 812 and current delta 814. As the stepper motor "steps" through a complete rotation, a target peak current (Ipeak) level is selected for each such microstep based on the currently specified degree of rotation. Accordingly, a target Ipeak level waveform 810 includes discrete steps determined based on (e.g., substantially encapsulating) sine wave 802. The described error reduction microstepper (e.g., microstepper 138) controls the stepper motor current to an actual regulated level 820, which is regulated relative to the different current levels between adjacent steps.

[0064] The reduced-error microstepper described in accordance with an example embodiment is calibrated at zero crossings by a zero-crossing calibrator 140 and is used to adjust (e.g., "fine-tune") the compensation trigger point for continuous stepping (including microstepping). Accordingly, the microstepper 138 achieves smaller microsteps with higher precision in current regulation and motor positioning in real space.

[0065] For example, the actual regulation level 820 of the coil control current reaches a (e.g., erroneously high) level 824 that exceeds the Ipeak current level 830 associated with the step associated with the current zero crossing level (0 mA). When the actual regulation level 820 exceeds the Ipeak current level 830, the result of the comparison is propagated to the (e.g., lower) FET, driving the actual regulation level 820 at approximately time 824. In response to the FET driver being turned off, the actual regulation level 820 is below the zero crossing level at approximately time period 804.

[0066] As described herein, loop delay timing information can be extracted based on the switching node voltage behavior after the FET driver is turned off at the zero crossing (e.g., as described below with reference to FIG. Figure 9 and Figure 10 The compensation trigger point is selected in response to the measured loop delay timing according to equation (2) described above and translated into a DAC voltage (e.g., used to bias the comparison voltage). The DAC voltage is used to bias the reference voltage (to produce the compensation trigger point voltage) to compare the motor voltage against the reference voltage at each subsequent step (e.g., to minimize the effects of loop delay errors at subsequent IPEAK detection levels).

[0067] For example, the actual regulation level 820 (in response to the turning on of the FET driver) rises from the zero-crossing level to a level 834 at approximately time period 804. Level 834 is lower than level 824 because the loop delay is effectively shortened by compensating for the trip point to cause the comparator to switch earlier (e.g., earlier than switching from an uncompensated comparison of the Itrip level and the motor output level Vm).

[0068] Figure 9 FIG9 is a waveform diagram 900 illustrating loop delay timing information for an overshoot condition according to an example embodiment. Waveform diagram 900 includes coil current (I_coil) 910, low-side gate voltage 940, and sense voltage (VSNS) signal 950. For example, in response to the upper FET (e.g., 214) turning on, coil current 910 rises from a zero reference level 902 to a peak level 914. Accordingly, voltage 950 (generated in response to coil current 910) decreases over a time period 952.

[0069] A first comparison is performed during time period 952 to determine when to turn off the upper FET and when to turn on the lower FET (e.g., 218). Voltage 950 is compared against a first selected bias emulation voltage (e.g., generated by bias DAC 228, where the first selected energizing bias is used to compensate for loop delay of the control loop as coil current 910 increases). As described above with reference to Figure 8As described above, a first selected bias emulation voltage is determined in a calibration search routine. In an embodiment of the calibration search routine, the selected bias is gradually increased over successive cycles (e.g., including coil current zero crossings) to determine the closest (e.g., last) energized bias that caused an overshoot condition (but not an undershoot condition). The selected bias is adjusted by incrementally increasing the previously selected bias to compensate for a time delay in the control loop caused by at least one of the modulator, the second switch, and the comparator circuit.

[0070] When voltage 950 is below the level of the selected emulation voltage, the upper FET turns off and the lower FET turns on in response to low-side FET gate voltage 940. Accordingly, coil current 910 begins to switch from peak level 914 and voltage 950 to a negative voltage by decreasing (e.g., rapidly) and beginning to increase (e.g., gradually) over time period 954.

[0071] A second comparison is performed at time period 954 to determine when to turn off the lower FET (e.g., 218). Voltage 950 is compared to a second selected bias emulation voltage (e.g., generated by bias DAC 228, where the second selected bias is used to compensate for loop delay of the control loop as coil current 910 decreases). A de-energized bias of the second selected bias emulation voltage is determined in response to the energized bias of the first selected bias emulation voltage determined by a calibration search routine (e.g., for the same cycle of coil energization / de-energization). In one embodiment, the de-energized bias of the second selected bias emulation voltage is determined in response to a time period associated with the energized bias of the first selected bias emulation voltage (used to offset the loop delay) and in response to an estimated slope of coil current 910 (and / or voltage 950) at time period 954. In one embodiment, a single comparator (e.g., 230) and bias DAC (e.g., 228) are used to perform the first and second comparisons, where the output of the comparator is gated so that the comparison is performed (e.g., only) during the active portion of time periods 952 and 954 and the appropriate bias (e.g., one of energized / de-energized) has been programmed into the bias DAC for generating the respective first and second selected bias emulation voltages.

[0072] As voltage 950 rises to a level above the second selected bias emulation voltage, low-side gate voltage 940 is driven lower (e.g., deasserted), causing the lower FET to turn off. When the lower FET is off, the coil current is blocked in response to the deassertion of the second control signal (when the first control signal for the upper FET is in the deasserted state). Accordingly, coil current 910 begins to rise from a negative level 922, causing the current coil 910 to oscillate like ringing 932 after the coil current 910 rises above the zero reference 902 level. Also, when the lower FET turns off (and the upper FET remains off), reverse recovery charge flows through the body diode (e.g., 218a) of the lower FET, causing voltage 950 to rise sharply and peak at an overshoot peak voltage level 956. Overshoot peak voltage level 956 is "clamped" at (e.g., limited to) a Vd (body diode breakdown voltage) level higher than the highest voltage previously reached by waveform portion 952 of the VSNS signal. Accordingly, a body diode effect occurs during a portion of a coil current cycle in which the second control signal is deasserted, the first control signal is in (e.g., remains in) a deasserted state, and zero crossings of the coil current occur in response to the selected microstepping for controlling the degree of rotation of the stepper motor coil.

[0073] The digital calibrator 234 detects overshoot and / or undershoot conditions relatively quickly, for example, by using a fast, low-gain comparator, a polarity detector, a diode bridge, and the like to determine the polarity of the VSNS signal when the body diode of the lower FET is conducting (e.g., shortly after and / or in response to a drop in the low-side gate voltage 940). For example, in an overshoot condition, the VSNS signal is positive (e.g., reaches a positive overshoot peak voltage level 956, which is above the forward breakdown voltage of the maximum VSNS without a body diode effect). When the VSNS signal is negative, the VSNS signal decreases to -Vd (below the negative forward body diode voltage of the minimum VSNS without a body diode effect), which is described below with reference to FIG. Figure 10 During the depicted undershoot condition, a negative voltage undershoot peak voltage level 1056 is reached. Accordingly, the digital calibrator 234 is operable to determine whether an overshoot or undershoot condition has occurred in response to the selected bias (and / or the determined time delay).

[0074] In an embodiment where a linear search is performed (e.g., by progressively making the bias larger and / or the associated time period longer), if an undershoot is not detected, the bias (energizing and de-energizing) for the next (e.g., test) cycle of the first selected bias emulation voltage is incrementally increased over the most recent (e.g., previously tested) cycle. Accordingly, the time period 924 continuously becomes less and less, and the degree of overshoot decreases with each test cycle. Successive cycles (involving zero crossings) are continuously tested until an undershoot is detected. When an undershoot is detected, the non-temporary energizing and de-energizing bias for successive (e.g., non-zero crossing) microstepping steps is selected (and / or determined) in response to the most recent (e.g., last) energizing and de-energizing bias (and / or the time delay associated therewith) in which the undershoot condition was detected.

[0075] Figure 10 FIG1 is a waveform diagram 1000 illustrating loop delay timing information for an undershoot condition according to an example embodiment. Waveform diagram 1000 includes coil current (I_coil) 1010, low-side gate voltage 1040, and sense voltage (VSNS) signal 1050. For example, in response to the upper FET (e.g., 214) turning on, coil current 1010 rises from a zero reference level 1002 to a peak level 1014. Accordingly, voltage 1050 (generated in response to coil current 1010) decreases over time period 1052.

[0076] A first comparison is performed during time period 1052 to determine when to turn off the upper FET and when to turn on the lower FET (e.g., 218). Voltage 1010 is compared against a first selected bias emulation voltage (e.g., generated by bias DAC 228, where the first selected energizing bias is used to compensate for loop delay of the control loop as coil current 1010 increases).

[0077] When voltage 1010 is below the selected emulation voltage level, the upper FET turns off and the lower FET turns on in response to low-side FET gate voltage 1040. Accordingly, coil current 1010 begins to switch from peak level 1014 and voltage 1010 decreases (e.g., rapidly) to a negative voltage and begins to increase (e.g., gradually) over time period 1054.

[0078] A second comparison is performed at time period 1054 to determine when to turn off the lower FET (e.g., 218). Voltage 1010 is compared to a second selected bias emulation voltage. A de-energized bias of the second selected bias emulation voltage is determined in response to the energized bias of the first selected bias emulation voltage determined by a calibration search routine (e.g., for the same cycle of coil energization / de-energization). In one embodiment, the de-energized bias of the second selected bias emulation voltage is determined in response to a time period associated with the energized bias of the first selected bias emulation voltage (for biasing the loop delay) and in response to an estimated slope of the coil current 1010 (and / or voltage 1050) during time period 1054.

[0079] As voltage 1050 rises to a level above the second selected bias emulation voltage, low-side gate voltage 1040 is driven lower (e.g., deasserted), causing the lower FET to turn off. When the lower FET turns off, coil current 1010 begins to rise from negative level 1022, causing the current coil 1010 to oscillate like ringing 1032 after the coil current 1010 rises above the zero reference 1002 level. Similarly, when the lower FET turns off, the VSNS signal is negative during an overshoot condition (e.g., reaching a negative voltage undershoot peak voltage level 1054). During the undershoot condition, the VSNS signal decreases to a voltage of -Vd (negative forward body diode voltage), reaching a negative voltage undershoot peak voltage level 1056 during the undershoot condition.

[0080] Figure 11 FIG1 is a waveform diagram 1100 illustrating loop delay timing information extraction for stepper motor error reduction according to an example embodiment. Waveform diagram 1100 includes an ideal (e.g., conceptual) sine wave 1102 indicating an ideal current for driving a (e.g., ideal) stepper motor through a complete rotation. The complete rotation is divided into various microsteps, e.g., microsteps 1120. For each microstep, the current used to drive (and / or control) the stepper motor is adjusted over a time period (e.g., 1120). During each such time period, the adjusted current has a sawtooth appearance, with the adjusted current rising and falling according to the associated microstep and error in the stepper motor's positioning, as determined by a control loop for adjusting the stepper motor's drive current.

[0081] The sine wave 1102 has a positive phase and a negative phase such that the sine wave 1102 crosses a zero current level (e.g., a zero crossing) between adjacent positive and negative phases. Accordingly, the zero crossing windows 1130, 1132, 1134, 1136, and 1138 are time windows in which at least one step can be programmed such that each of a plurality of cycles (e.g., one of the cycles in Figure 81142, 1143, 1144, 1145, and 1146 microsteps. Accordingly, higher accuracy current regulation is achieved when calibration is performed at each half wave (e.g., at each zero crossing of the sine wave 1102).

[0082] Figure 12 1 is a waveform diagram 1200 illustrating error reduction during a zero-crossing calibration routine for stepper motor error reduction according to an example embodiment. The waveform diagram 1200 includes a DAC (eg, 228) output voltage 1202 and a stepper motor control current 1204.

[0083] DAC output voltage 1202 is the output voltage of a bias DAC, e.g., bias DAC 228. DAC output voltage 1202 is the output voltage generated in response to the selected energized bias. The output voltage generated in response to the selected de-energized bias is not shown, but the output voltage generated in response to the selected de-energized bias is similar (albeit with a different polarity) to the illustrated DAC output voltage 1202. During the calibration search routine, the selected bias is gradually increased over successive cycles (e.g., including coil current zero crossings) to determine the closest (e.g., last) energized bias that caused an overshoot condition. Accordingly, DAC output voltage 1202 is switched to regulate at each of switching times 1211, 1212, 1213, 1214, 1215, 1216, and 1217 (except during switching times).

[0084] The stepper motor control current 1204 is a circuit 220 of the microstepper 200 that is calibrated for zero crossings in response to the coil current generated by the control loop. Each cycle includes a positive current peak (e.g., 1221, 1222, 1223, 1224, 1225, 1226, and 1227, respectively) and a negative current peak (e.g., 1231, 1232, 1234, 1235, 1236, and 1237, respectively). The degree of deviation from a positive current peak to a subsequent current peak is an indication of the error (e.g., errors 1241, 1242, 1243, 1244, 1245, 1246, and 1247, respectively) caused by the loop delay of the control loop used to regulate the coil current.

[0085] As each successive iteration of the calibration search routine is performed, the error associated with the loop delay progressively decreases, as shown by the illustrated amplified (at the same scale) portion of the simulated coil current of the calibration search routine. For example, the DAC offset value prior to switching time 1211 causes an overshoot condition for the cycle associated with positive current peak 1221 and negative current peak 1231. No overshoot is detected at switching time 1211, so the DAC offset is adjusted upward (e.g., to provide greater compensation to help offset the loop delay). The increased value of the DAC offset changes the trigger point for the next cycle such that error 1242 (associated with positive current peak 1222 and negative current peak 1232) is less than error 1241 (associated with positive current peak 1221 and negative current peak 1231).

[0086] The DAC bias is increased for each of the subsequent cycles until an undershoot condition is detected that is caused by the DAC bias programmed at switch time 1226 (the DAC bias then passes the last DAC bias value programmed at switch time 1227 that does not cause an undershoot condition detected for the cycle). In one embodiment, the calibration routine continues until microstepping values ​​that do not include zero crossings are used (e.g., so that the body diode effect does not reflect an undershoot or overshoot condition).

[0087] In one embodiment, the length of the loop delay is determined, for example, by adjusting the amount of compensation (e.g., to offset) of the loop delay for each cycle, and a determination is made as to whether an undershoot condition is achieved for the corresponding cycle. Whether an undershoot condition is achieved for the corresponding cycle is determined, in one embodiment, by determining the effect of the lower FET body diode on a voltage generated in response to the coil current following (e.g., during and shortly after) the lower FET turning off after the coil is at least partially de-energized.

[0088] Figure 13 FIG1 is a waveform graph 1300 illustrating a comparison of the degree of current error between a simulation of a stepper motor without calibration and a simulation of a stepper motor using stepper motor error reduction, according to an example embodiment. The waveform graph 1300 includes an uncompensated Itrip current error 1302 (in mA), a compensated Itrip current error 1304 (in mA), a compensated zero-crossing error 1306 (e.g., the current error in mA when the coil current becomes negative when the coil is de-energized), and an uncompensated zero-crossing error 1308 (in mA).

[0089] Waveform 1302 illustrates a simulated (uncompensated) Itrip current error for a target Itrip level of 248.9 mA, a coil having an inductance of 0.5 mH, and a (e.g., nominal) motor output voltage of 40 volts for a circuit operating at 25° C. As indicated, the Itrip current error for the simulation is approximately 35 mA over the simulation period.

[0090] Waveform 1304 illustrates a simulated, compensated (e.g., calibrated itself, as described herein) Itrip current error for a target Itrip level of 248.9 mA for a circuit operating at 25° C., a coil having an inductance of 0.5 mH, and a motor output voltage of 40 volts (e.g., nominal). As indicated, the simulated, compensated Itrip current error converges (e.g., at step 1340) to a value of approximately 0 mA. For example, at step 1342, no undershoot is detected and compensation (e.g., energizing bias) is increased such that the lower FET turns on before the energizing current reaches the Itrip level (which results in an approximately negative 6 mA error in step 1342). At step 1344, undershoot is detected and compensation is decreased such that the lower FET turns on at approximately the time the energizing current reaches the Itrip level (which results in an approximately 0 mA error in step 1344). The calibration steps are repeated (eg, until a non-zero-crossing microstep is selected) such that the remaining error mean value alternates between two values ​​after the calibration routine converges around an offset that substantially represents the control loop delay.

[0091] Waveform 1306 illustrates a simulated, compensated (e.g., calibrated as described herein) zero-crossing current error for a circuit operating at 25°C, a coil having an inductance of 0.5 mH, and a motor output voltage of 40 volts (e.g., nominal). As indicated, the simulated, compensated zero-crossing current error converges (e.g., at step 1360) to a value of approximately 0 mA. For example, at step 1362, no undershoot is detected and compensation (e.g., de-energizing bias) is increased such that the lower FET turns off after the de-energizing current crosses 0 mA (e.g., changes direction, resulting in an approximately positive 6 mA error in step 1362). At step 1364, undershoot is detected and compensation is decreased such that the lower FET turns off at approximately the time the de-energizing current reaches zero crossing (which results in an approximately 0 mA error in step 1344). The calibration steps are repeated (e.g., until a non-zero-crossing microstep is selected) such that the remaining error average value alternates between the two values ​​after the calibration routine converges.

[0092] Waveform 1308 illustrates the (uncompensated) zero-crossing error for a circuit operating at 25° C., a coil having an inductance of 0.5 mH, and a (eg, nominal) motor output voltage of 40 volts. As indicated, the zero-crossing current error for the simulation is approximately negative 34 mA over the simulation period.

[0093] 14 is a waveform diagram 1400 illustrating the relative extent of voltage error in a simulation of a stepper motor without calibration at various levels of coil inductance. Waveform diagram 1400 includes uncompensated Itrip voltage error 1402 (in mV), uncompensated Itrip voltage error 1404 (in mV), uncompensated Itrip voltage error 1406 (in mV), uncompensated zero-crossing error 1408 (in mA), uncompensated zero-crossing error 1410 (in mA), and uncompensated zero-crossing error 1412 (in mA).

[0094] Waveforms 1402, 1404, and 1406 illustrate the nonlinear increase in simulated (uncompensated) Itrip voltage error for a target Itrip level of 166.5 mA for a circuit operating at 25° C., where the voltage error increases progressively at lower levels of coil inductance. For example, a coil with an inductance of 0.5 mH causes an Itrip error of approximately 36 mV (per waveform 1402), a coil with an inductance of 1.0 mH causes an Itrip error of approximately 21 mV (per waveform 1404), and a coil with an inductance of 1.5 mH causes an Itrip error of approximately 15 mV (per waveform 1406).

[0095] Waveforms 1408, 1410, and 1412 illustrate the nonlinear increase in simulated (uncompensated) zero-crossing (ZC) current error for a target Itrip level of 166.5 mA for a circuit operating at 25° C., where the current error increases progressively at lower levels of coil inductance. For example, a coil with an inductance of 1.5 mH results in a zero-crossing error of approximately negative 16 mA (per waveform 1408), a coil with an inductance of 1.0 mH results in a zero-crossing error of approximately negative 22 mA (per waveform 1410), and a coil with an inductance of 0.5 mH results in a zero-crossing error of approximately negative 34 mV (per waveform 1412). Accordingly, the accuracy of regulation increases progressively (if not exponentially) when driving increasingly smaller motors with coils of increasingly smaller inductance.

[0096] Figure 15FIG15 is a waveform diagram 1500 illustrating a comparison of the degree of current error for a stepper motor at different coil inductances and using a simulation of stepper motor error reduction according to an example embodiment. The waveform diagram 1500 includes a compensated Itrip current error waveform 1502 (in mA), a compensated Itrip current error waveform 1504 (in mA), a compensated Itrip current error waveform 1506, a compensated zero-crossing error waveform 1508 (in mA), a compensated zero-crossing error waveform 1510 (in mA), and a compensated zero-crossing error waveform 1512 (in mA).

[0097] Waveforms 1502, 1504, and 1506 illustrate the nonlinear reduction of the simulated current error using the described error reduction for a target Itrip level of 166.5 mA for a circuit operating at 25° C. The simulated waveforms indicate that the progressively increasing current error caused by the lower coil inductance is effectively reduced to a level substantially approximately that of the current error caused by the higher coil inductance.

[0098] For example, waveform 1502 shows the described error reduction for a coil having an inductance of 1.5 mH and an average (e.g., converged) Itrip error of approximately 3 mA (where simulation scaling shows that the described error reduction has converged on an optimal bias). Waveform 1504 shows the described error reduction for a coil having an inductance of 1.0 mH, where an earlier Itrip error of approximately negative 8 mA is reduced as the described error reduction converges to an optimal bias that produces an average Itrip error of approximately 0 mA. Waveform 1506 shows the described error reduction for a coil having an inductance of 0.5 mH, where an earlier Itrip error of approximately negative 26 mA is reduced as the described error reduction converges to an optimal bias that produces an average Itrip error of approximately 1 mA.

[0099] Waveforms 1508, 1510, and 1512 illustrate the nonlinear increase in simulated (uncompensated) zero-crossing (ZC) current error for a target Itrip level of 166.5 mA for a circuit operating at 25° C., where the current error increases progressively at lower levels of coil inductance. For example, waveform 1508 shows the described error reduction for a coil with an inductance of 0.5 mH, where an earlier zero-crossing error of approximately -27 mA is reduced as the described error reduction converges to an optimal bias that produces an average zero-crossing error of approximately -2 mA. Waveform 1510 shows the described error reduction for a coil with an inductance of 1.0 mH, where an earlier zero-crossing error of approximately 9 mA is reduced as the described error reduction converges to an optimal bias that produces an average zero-crossing error of approximately -1 mA. Waveform 1512 shows the described error reduction for a coil with an inductance of 1.5 mH and an average zero-crossing of approximately -3 mA (where the simulated scaling shows that the described error reduction has converged on the optimal bias). According to this description, scaling of stepper motors to ever decreasing coil inductances (and higher voltages) need not be limited by increasing nonlinearity of the errors.

[0100] Modifications to the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A device comprising: a current generator having a current output; a transistor coupled between the current output and a ground terminal, the transistor having a control terminal, and the transistor having a first current terminal coupled to the current output; an offset generation circuit having an offset control input, a voltage input, and an offset voltage output, the voltage input being coupled to the first current terminal; a comparator having a comparator output and a first comparator input and a second comparator input, the first comparator input coupled to a voltage sense terminal and the second comparator input coupled to the offset voltage output; and A pulse width modulation (PWM) circuit has a control input and a PWM output, wherein the control input is coupled to the comparator output and the PWM output is coupled to the control terminal.

2. The device according to claim 1, wherein: the current generator being configured to provide a current at the current output; the transistor being configured to provide a first voltage in response to the current and a state of the control terminal; the offset generation circuit being configured to provide a reference voltage at the offset voltage output by adding an offset to the first voltage, the offset being based on a control signal at the offset control input; the comparator being configured to generate a decision signal in response to a second voltage at the first comparator input and the reference voltage at the second comparator input; and The PWM circuit is configured to provide a PWM signal at the PWM output, and a state of the PWM signal is set in response to a state of the decision signal, and a state of the control terminal is set based on the state of the PWM signal.

3. The device of claim 2, wherein the current generator comprises a digital-to-analog converter (DAC).

4. The device of claim 2, wherein the offset generation circuit comprises a DAC configured to generate the reference voltage in response to the control signal representing a code at the offset control input.

5. The apparatus of claim 4 , further comprising a calibration circuit having a calibration output and first and second calibration inputs, the first calibration input coupled to a voltage sense terminal, the second calibration input coupled to the PWM output, and the calibration output coupled to the offset control input, the calibration circuit configured to: determine a state of the second voltage in response to the PWM signal changing from a first state to a second state; adjusting the code based on a state of the second voltage; and The control signal representing the adjusted code is provided at the calibration output. 6 . The device of claim 5 , wherein the calibration circuit is configured to adjust the code based on whether the second voltage becomes positive or negative after the PWM signal changes from the first state to the second state.

7. The device of claim 6, wherein the calibration circuit is configured to adjust the code by stepping up or down.

8. The apparatus according to claim 5, wherein: The transistor is a first transistor; The apparatus further includes an H-bridge including a second transistor and a third transistor, and an inductor coupled between current terminals of the second transistor and the third transistor, the second transistor having a second control terminal and the third transistor having a third control terminal; The inductor is coupled to the voltage sensing terminal; and The second control terminal and the third control terminal are coupled to the PWM output.

9. The device of claim 8, wherein the calibration circuit is configured to determine a state of the second voltage when the third transistor is in a disabled state.

10. The apparatus of claim 2, wherein the control terminal is coupled to the PWM output, and a state of the control terminal is set based on a state of the PWM signal.

11. A method comprising: receiving a first voltage from a first current terminal of a first transistor, the first current terminal coupled to the current generator; enabling a second transistor by providing a control signal having a first state, a second current terminal of the second transistor being coupled to the inductor; receiving a second voltage from the second current terminal; determining an offset to be added to the first voltage; generating a reference voltage by adding the offset to the first voltage; generating a decision by comparing the second voltage with the reference voltage; In response to the determined state change, setting the control signal to a second state; and The first transistor is disabled by providing the control signal having the second state to the first transistor. The method of claim 11 , wherein the reference voltage is generated based on a code.

13. The method according to claim 12, further comprising: determining a state of the second voltage in response to the control signal changing from the first state to the second state; adjusting the code based on a state of the second voltage; and The reference voltage is generated based on the adjusted code. 14 . The method of claim 13 , wherein the code is adjusted based on the second voltage becoming positive or negative after the control signal changes from the first state to the second state.

15. The method of claim 11, further comprising enabling and disabling the first transistor based on a state of the control signal.

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