An interference rejection circuit and digital isolation circuit

Abstract

The application discloses an interference suppression circuit and a digital isolation circuit, wherein the interference suppression circuit is arranged at a receiving end of the digital isolation circuit and is connected between an output end of an isolator and a preamplifier; the interference suppression circuit comprises a pair of NMOS tubes and a pair of PMOS tubes; when the output signal of the isolator comprises a transient pulse higher than a common mode level, the pair of NMOS tubes is closed and the pair of PMOS tubes is opened, so as to reduce a first state of the transient pulse; when the output signal of the isolator comprises a transient pulse lower than the common mode level, the pair of NMOS tubes is opened and the pair of PMOS tubes is closed, so as to improve a second state of the transient pulse; and when the output signal of the isolator is the common mode level, the pair of NMOS tubes and the pair of PMOS tubes are both closed, which is a third state. The circuit in the application can effectively suppress common mode transient interference.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to an interference suppression circuit and a digital isolation circuit. Background Technology

[0002] Isolation refers to the electrical separation between various functional circuits in a system, preventing signal transmission through direct conductive paths. Instead, it physically separates high-voltage and low-voltage domains, minimizing mutual interference between circuits at different potentials. Currently, capacitive coupling is commonly used. A typical capacitive isolation drive circuit includes a transmitter (modulation module on the low-voltage side), a receiver (demodulation module on the high-voltage side), and an isolation capacitor. The transmitter modulates the transmitted signal into a signal that can pass through the isolation capacitor module, while the receiver demodulates the signal from the isolation capacitor module back into the transmitted signal. The isolation capacitor module connects the transmitter and receiver.

[0003] With the increasing intelligence of industrial and communication equipment, the market demand for digital isolators is growing daily, and the performance requirements are becoming increasingly stringent. Therefore, one of the primary problems to be solved in designing and inventing digital isolators is common-mode transient interference. Currently, differential circuits are commonly used to improve the common-mode transient interference of digital isolators. This primarily relies on two resistors in the circuit to reduce common-mode interference; however, its operating range is relatively small, and communication failures can still occur when the common-mode voltage exceeds this range.

[0004] Therefore, how to effectively suppress common-mode transient interference in digital isolation circuits has become an urgent problem to be solved. Summary of the Invention

[0005] Therefore, in order to solve the above-mentioned problems in the prior art, this application provides an interference suppression circuit and a digital isolation circuit.

[0006] According to a first aspect, the present invention provides an interference suppression circuit disposed at the receiving end of a digital isolation circuit and connected between the output end of the isolator and the preamplifier; the interference suppression circuit includes:

[0007] The interference suppression circuit comprises a pair of NMOS transistors and a pair of PMOS transistors. It has a first state where, when the output signal of the isolator includes a transient pulse higher than the common-mode level, the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on to reduce the transient pulse; a second state where, when the output signal of the isolator includes a transient pulse lower than the common-mode level, the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off to increase the transient pulse; and a third state where, when the output signal of the isolator is at the common-mode level, both the pair of NMOS transistors and the pair of PMOS transistors are turned off.

[0008] Furthermore, a pair of NMOS transistors includes NMOS transistor M1 and NMOS transistor M3, and a pair of PMOS transistors includes PMOS transistor M2 and PMOS transistor M4;

[0009] The gates of both NMOS transistor M1 and PMOS transistor M2 are connected to the reference voltage. The drain of NMOS transistor M1 is connected to the high-level output terminal of the drive power supply, and its source is connected to the source of PMOS transistor M2 and connected to the non-inverting input terminal and the non-inverting output terminal. The drain of PMOS transistor M2 is grounded.

[0010] The gates of both NMOS transistor M3 and PMOS transistor M4 are connected to the reference voltage. The drain of NMOS transistor M3 is connected to the high-level output terminal of the drive power supply, and its source is connected to the source of PMOS transistor M4 and connected to the inverting input terminal and the inverting output terminal. The drain of PMOS transistor M4 is grounded.

[0011] Furthermore, a first capacitor is provided between the source and the non-inverting input terminal of NMOS transistor M1, and a second capacitor is provided between the source and the inverting input terminal of NMOS transistor M3.

[0012] According to a second aspect, the present invention also provides a digital isolation circuit, including a transmitting circuit, an isolator, and a receiving circuit. The receiving circuit includes a preamplifier, a demodulation circuit, and an interference suppression circuit as described in any of the embodiments of the first aspect above. The interference suppression circuit, the preamplifier, and the demodulation circuit are connected in sequence.

[0013] Furthermore, the demodulation circuit includes:

[0014] PMOS transistor M13, whose gate is connected to the output terminal V of the first bias voltage. BIAS1 The source is connected to the high-level output terminal V of the drive power supply. DD ;

[0015] The sources of PMOS transistors M14, M15, and M16 are all connected to the drain of PMOS transistor M13, and the gate of PMOS transistor M14 is connected to the inverting input V. IN The gate of PMOS transistor M15 is connected to the non-inverting input V. IP The gate of PMOS transistor M16 is connected to the common-mode voltage V. REF ;

[0016] PMOS transistors M17 and M18 have their gates interconnected, and their sources are both connected to the high-level output terminal V of the drive power supply. DD ;

[0017] PMOS transistors M19 and M20 have their gates interconnected and connected to the output terminal V of the second bias voltage. BIAS2The source of PMOS transistor M19 is connected to the drain of PMOS transistor M17, and the source of PMOS transistor M20 is connected to the drain of PMOS transistor M18.

[0018] NMOS transistors M21 and M22 have their gates interconnected and connected to the output terminal V of the third bias voltage. BIAS3 The drain of NMOS transistor M21 is connected to the drain of PMOS transistor M19 and the gate of PMOS transistor M17, and the drain of NMOS transistor M22 is connected to the drain of PMOS transistor M20.

[0019] NMOS transistors M23 and M24 have their gates interconnected and connected to the output terminal V of the fourth bias voltage. BIAS4 Both sources are connected to the low-level output terminal V of the drive power supply. SS The drain of NMOS transistor M23 is connected to the source of NMOS transistor M21, the drain of PMOS transistor M14, and the drain of PMOS transistor M15. The drain of NMOS transistor M24 is connected to the source of NMOS transistor M22 and the drain of PMOS transistor M16.

[0020] PMOS transistors M25 and M26 have their gates interconnected and connected between the drains of PMOS transistor M20 and NMOS transistor M22. Their drains are also interconnected and output signal DE. MOD The source of PMOS transistor M25 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M26 is connected to the low-level output terminal V of the drive power supply. SS .

[0021] The technical solution provided by this invention has the following advantages:

[0022] 1. The interference suppression circuit provided by the present invention includes a pair of NMOS transistors and a pair of PMOS transistors. When the output signal of the isolator includes a transient pulse higher than the common-mode level, the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on, thereby reducing the pulse amplitude of the transient pulse. When the output signal of the isolator includes a transient pulse lower than the common-mode level, the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off, thereby increasing the pulse amplitude of the transient pulse. Ultimately, this invention achieves effective suppression of common-mode transient interference. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of an interference suppression circuit provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of a digital isolation circuit provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a demodulation circuit provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] Example 1

[0030] Figure 1 This diagram illustrates the structure of an interference suppression circuit in one embodiment of the present invention. Specifically, as shown... Figure 2 As shown, the interference suppression circuit is located at the receiving end of the digital isolation circuit and connected to the output of the isolator and the preamplifier. Figure 2 The preamplifier in the text is between the two, and as follows: Figure 2 As shown, the setting of this interference suppression circuit does not affect the setting of other parts of the digital isolation circuit (such as the transmitting circuit, the receiving demodulation circuit, the receiving amplification circuit, etc.).

[0031] Specifically, the interference suppression circuit includes a pair of NMOS transistors and a pair of PMOS transistors. The interference suppression circuit has a first state in which the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on to reduce the transient pulse when the output signal of the isolator includes a transient pulse higher than the common-mode level; a second state in which the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off to increase the transient pulse when the output signal of the isolator includes a transient pulse lower than the common-mode level; and a third state in which both the pair of NMOS transistors and the pair of PMOS transistors are turned off when the output signal of the isolator is at the common-mode level.

[0032] Specifically, such as Figure 2 As shown, the signal after common-mode transient interference suppression by the interference suppression circuit is transmitted normally to the preamplifier and demodulation circuit for demodulation.

[0033] Taking a pair of NMOS transistors (M1 and M3) and a pair of PMOS transistors (M2 and M4) as an example, the following is a detailed description: Figure 1 As shown, the gates of NMOS transistors M1, M2, M3, and M4 are all connected to the reference voltage V. REF The drain of NMOS transistor M1 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M1 is connected to the source of PMOS transistor M2 and connected to the positive input V. IP Connect the positive phase output V OP The drain of PMOS transistor M2 is grounded; the drain of NMOS transistor M3 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M3 is connected to the source of PMOS transistor M4 and connected to the inverting input V. IN , Connect the inverting output V ON The drain of PMOS transistor M4 is grounded.

[0034] Specifically, set the reference voltage V REF If it is a common-mode level, then at the input signal (V IP and V IN When the normal constant common-mode level is reached, NMOS transistors M1, M2, M3, and M4 are all turned off, and the output signal (V) is... OP and V ONThe input signal is the same as the input signal. When the input signal is a pulse higher than the common-mode level, NMOS transistors M1 and M3 are turned off, and PMOS transistors M2 and M4 are turned on, reducing the pulse amplitude. When the input signal is a pulse lower than the common-mode level, NMOS transistors M1 and M3 are turned on, and PMOS transistors M2 and M4 are turned off, increasing the pulse amplitude. Ultimately, effective suppression of common-mode transient interference is achieved regardless of whether a transient pulse higher or lower than the common-mode level occurs.

[0035] In one specific embodiment of this example, the source of the NMOS transistor M1 and the non-inverting input terminal V can also be connected. IP A first capacitor C1 is set between the source and the inverting input terminal V of the NMOS transistor M3. IN A second capacitor C2 is also installed between them.

[0036] The interference suppression correction circuit in this embodiment includes a pair of NMOS transistors and a pair of PMOS transistors. When the output signal of the isolator includes a transient pulse higher than the common-mode level, the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on, thereby reducing the pulse amplitude of the transient pulse. When the output signal of the isolator includes a transient pulse lower than the common-mode level, the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off, thereby increasing the pulse amplitude of the transient pulse. Ultimately, this achieves effective suppression of common-mode transient interference.

[0037] Example 2

[0038] Figure 2 A schematic diagram of the structure of a digital isolation circuit in one embodiment of this invention is shown, as follows: Figure 1 As shown, the transmitting circuit, isolator, and receiving circuit are included. The receiving circuit includes a preamplifier, a demodulation circuit, and the interference suppression circuit in Embodiment 1 above; and the interference suppression circuit, preamplifier, and demodulation circuit are connected in sequence.

[0039] Figure 3 A schematic diagram of the receiver demodulation circuit in one embodiment of this invention is shown. Figure 3 As shown, the demodulation circuit may include: a PMOS transistor M13, whose gate is connected to the output terminal V of the first bias voltage. BIAS1 The source is connected to the high-level output terminal V of the drive power supply. DD The sources of PMOS transistors M14, M15, and M16 are all connected to the drain of PMOS transistor M13, and the gate of PMOS transistor M14 is connected to the inverting input V. IN The gate of PMOS transistor M15 is connected to the non-inverting input V. IPThe gate of PMOS transistor M16 is connected to the common-mode voltage V. REF PMOS transistors M17 and M18 have their gates interconnected, and their sources are both connected to the high-level output terminal V of the drive power supply. DD PMOS transistors M19 and M20 have their gates interconnected and connected to the output terminal V of the second bias voltage. BIAS2 The source of PMOS transistor M19 is connected to the drain of PMOS transistor M17, and the source of PMOS transistor M20 is connected to the drain of PMOS transistor M18; the gates of NMOS transistors M21 and M22 are interconnected and connected to the output terminal V of the third bias voltage. BIAS3 The drain of NMOS transistor M21 is connected to the drain of PMOS transistor M19 and the gate of PMOS transistor M17; the drain of NMOS transistor M22 is connected to the drain of PMOS transistor M20; the gates of NMOS transistors M23 and M24 are interconnected and connected to the output terminal V of the fourth bias voltage. BIAS4 Both sources are connected to the low-level output terminal V of the drive power supply. SS The drain of NMOS transistor M23 is connected to the source of NMOS transistor M21, the drain of PMOS transistor M14, and the drain of PMOS transistor M15. The drain of NMOS transistor M24 is connected to the source of NMOS transistor M22 and the drain of PMOS transistor M16. The gates of PMOS transistors M25 and M26 are interconnected and connected between the drains of PMOS transistor M20 and NMOS transistor M22. Their drains are interconnected and output signal DE. MOD The source of PMOS transistor M25 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M26 is connected to the low-level output terminal V of the drive power supply. SS .

[0040] The digital isolation circuit in this embodiment effectively suppresses common-mode transient interference through an interference suppression circuit, and has a high common-mode transient immunity capability.

[0041] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An interference rejection circuit, characterized by, The interference suppression circuit is located at the receiving end of the digital isolation circuit and connected between the output of the isolator and the preamplifier; the interference suppression circuit includes: The interference suppression circuit includes a pair of NMOS transistors and a pair of PMOS transistors, and has the following states: a first state in which the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on to reduce the transient pulse when the output signal of the isolator includes a transient pulse higher than the common-mode level; a second state in which the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off to increase the transient pulse when the output signal of the isolator includes a transient pulse lower than the common-mode level; and a third state in which both the pair of NMOS transistors and the pair of PMOS transistors are turned off when the output signal of the isolator is the common-mode level. The pair of NMOS transistors includes NMOS transistor M1 and NMOS transistor M3, and the pair of PMOS transistors includes PMOS transistor M2 and PMOS transistor M4; The gates of both the NMOS transistor M1 and the PMOS transistor M2 are connected to the reference voltage. The drain of the NMOS transistor M1 is connected to the high-level output terminal of the driving power supply, and its source is connected to the source of the PMOS transistor M2 and connected to the non-inverting input terminal and the non-inverting output terminal. The drain of the PMOS transistor M2 is grounded. The gates of both the NMOS transistor M3 and the PMOS transistor M4 are connected to the reference voltage. The drain of the NMOS transistor M3 is connected to the high-level output terminal of the driving power supply, and its source is connected to the source of the PMOS transistor M4 and connected to the inverting input terminal and the inverting output terminal. The drain of the PMOS transistor M4 is grounded. A first capacitor is provided between the source of the NMOS transistor M1 and the non-inverting input terminal, and a second capacitor is provided between the source of the NMOS transistor M3 and the inverting input terminal.

2. A digital isolation circuit, comprising: It includes a transmitting circuit, an isolator, and a receiving circuit. The receiving circuit includes a preamplifier, a demodulation circuit, and the interference suppression circuit as described in claim 1. The interference suppression circuit, the preamplifier, and the demodulation circuit are connected in sequence.

3. The digital isolation circuit of claim 2, wherein, The demodulation circuit includes: PMOS transistor M13, the gate of which is connected to the output end V of the first bias voltage BIAS1 , the source of which is connected to the high level output end V of the driving power supply DD ; PMOS transistor M14, PMOS transistor M15 and PMOS transistor M16, whose sources are all connected to the drain of the PMOS transistor M13, the gate of the PMOS transistor M14 is connected to the inverting input V IN , the gate of the PMOS transistor M15 is connected to the non-inverting input V IP , and the gate of the PMOS transistor M16 is connected to the common mode level V REF ; PMOS transistor M17 and PMOS transistor M18, the gates of both are connected to each other, and the sources of both are connected to the high-level output end V of the driving power supply DD ; PMOS transistor M19 and PMOS transistor M20, whose gates are connected to each other and to the output terminal V of the second bias voltage BIAS2 , the source of the PMOS transistor M19 being connected to the drain of the PMOS transistor M17, and the source of the PMOS transistor M20 being connected to the drain of the PMOS transistor M18; NMOS transistor M21 and NMOS transistor M22, whose gates are connected to each other and to the output terminal V of the third bias voltage BIAS3 , the drain of the NMOS transistor M21 being connected to the drain of the PMOS transistor M19 and to the gate of the PMOS transistor M17, and the drain of the NMOS transistor M22 being connected to the drain of the PMOS transistor M20; NMOS transistor M23 and NMOS transistor M24, whose gates are connected to each other and to the output end V of the fourth bias voltage BIAS4 , whose sources are both connected to the low-level output end V of the driving power supply SS , the drain of the NMOS transistor M23 is connected to the source of the NMOS transistor M21, the drain of the PMOS transistor M14 and the drain of the PMOS transistor M15, and the drain of the NMOS transistor M24 is connected to the source of the NMOS transistor M22 and the drain of the PMOS transistor M16; PMOS transistor M25 and NMOS transistor M26, whose gates are connected to each other and to the drain of the PMOS transistor M20 and the drain of the NMOS transistor M22, whose drains are connected to each other and output the signal DE MOD The source of the PMOS transistor M25 is connected to the high-level output V DD The source of the NMOS transistor M26 is connected to the low-level output V SS .

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