Serializer-based High-precision Signal Delay Method, Electronic Device, and Storage Medium

Abstract

The present invention discloses a high-precision signal delay method, an electronic device and a storage medium based on a serializer. First, the signal is converted into parallelized data, and then the serializer is used to serialize the parallelized data. In this way, analog-to-digital conversion of the signal can be achieved to ensure the original output of the signal after delay. At the same time, on the basis of keeping the write address unchanged, by adjusting the read address in the memory of the existing chip, the interval between the two can be increased or decreased, so as to achieve forward delay or backward delay when reading data. Therefore, the present invention can use the existing chip to realize the signal delay chain, thereby realizing signal delay at the picosecond level without relying on a dedicated time delay chip, which not only reduces the cost, but also greatly improves the design flexibility by using the existing chip to realize the high-precision delay design, and is suitable for wide application and promotion.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal delay, and particularly relates to a high-precision signal delay method, an electronic device and a storage medium based on a serializer. Background Art

[0002] Currently, in the field of signal processing, most signals are subjected to delay processing to achieve synchronization between different signals. Among them, conventional signal delay methods, such as using delay methods with different line lengths, can only achieve nanosecond-level delays. If high-precision picosecond-level delays are to be achieved, dedicated time delay chips must be used, which not only results in high delay costs, but also the delay can only be designed based on commercially available time delay chips, limiting the design flexibility. Therefore, how to provide a high-precision signal delay method with low cost and high design flexibility has become a research hotspot in the field of signal delay. Summary of the Invention

[0003] The purpose of the present invention is to provide a high-precision signal delay method, an electronic device and a storage medium based on a serializer, so as to solve the problems of high cost and limited design flexibility caused by the necessity of using dedicated time delay chips for high-precision signal delay in the prior art.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] In a first aspect, a high-precision signal delay method based on a serializer is provided, including:

[0006] Obtain a signal to be delayed, and under the drive of a parallel clock, perform parallelization processing on the signal to be delayed to output a plurality of parallelized data respectively according to a target period, where the target period is the clock period of the parallel clock;

[0007] Store a plurality of parallelized data in a memory, and each address in the memory corresponds to a parallelized data;

[0008] Obtain a delay time, and based on the delay time and the target period, determine the coarse delay time and the fine delay time of the signal to be delayed;

[0009] Judge whether the fine delay time is greater than 0;

[0010] If so, according to the coarse delay time, determine the actual read address when the signal to be delayed is first read from the memory, and according to the fine delay time, determine the amount of data when the signal to be delayed is first read from the memory;

[0011] When reading data for the first time, starting from the actual read address as the read starting point, read the parallelized data corresponding to the actual read address, and select m-bit data from the parallelized data corresponding to the actual read address as the first data, where m is the bit value corresponding to the data volume, and during the reading process, keep the write address of the memory as the first preset address;

[0012] Based on the serializer, convert the first data into first serial data for output;

[0013] When reading data for the i-th time, read the parallelized data corresponding to the first target address, and select the first n-bit data from the parallelized data corresponding to the first target address to splice with the remaining data in the previous address of the first target address to obtain the second data, where the first target address is the next address corresponding to the address during the (i - 1)-th data reading, the remaining data is the data after removing m-bit data from the parallelized data corresponding to the previous address of the first target address, n is the difference between the data volume of any parallelized data and the data volume corresponding to the remaining data, i starts from 2, and i and n are positive integers;

[0014] Based on the serializer, convert the second data into second serial data for output;

[0015] Increment i by 1 until all the parallelized data in the memory is read, so as to complete the serialized delay output of the to-be-delayed signal after reading is completed.

[0016] Based on the above disclosed content, the present invention first converts the signal to be delayed into several parallelized data for periodic output under the drive of the parallel clock, and then stores the periodically output parallelized data in the memory, so as to achieve delay adjustment by adjusting the read address in the memory without adjusting the write address of the memory; specifically, the present invention uses the period and delay time of the parallel clock to determine the coarse delay time and fine delay time of the adjustment signal delay, wherein the coarse delay time is used to determine the actual read address of the first data read in the memory, and the fine delay time is used to determine the amount of data when the data is first read in the memory, and then, the actual read address can be used as the reading starting point, and data of the same size as the aforementioned data amount can be selected from the corresponding parallelized data, that is, m bits of data are selected from the parallelized data corresponding to the actual read address as the first data, and It is input to the serializer for serialization and then output; when reading data in the next cycle, the address needs to be postponed, that is, the parallelized data corresponding to the next address of the actual read address is read. At the same time, the data size to be selected from the data read in the next cycle is determined based on the data volume of any parallelized data and the remaining data in the parallelized data corresponding to the previous read address. If the data volume of any parallelized data is N, then the data to be selected from the next cycle is the difference between N and the data volume of the remaining data (the difference between the two is n). In this way, the data remaining after removing m bits of data in the previous cycle can be spliced with the n bits of data selected from the data read in the next cycle to obtain the second data. Of course, it will also be input to the serializer for serialization processing. Therefore, the above method can be used to continuously read and splice data, thereby realizing the delayed output of the signal to be delayed.

[0017] Through the above design, the present invention first converts the signal into parallel data, and then uses a serializer to serialize the parallel data. In this way, the analog-to-digital conversion of the signal can be realized to ensure that the signal is output as it is after the delay; at the same time, on the basis of keeping the write address unchanged, by adjusting the read address in the memory in the existing chip, the interval between the two can be increased or decreased, thereby realizing forward delay or backward delay when reading data. Therefore, the present invention can use the existing chip to realize the signal delay chain, thereby realizing picosecond level signal delay without relying on dedicated time delay chip, which not only reduces the cost, but also uses the existing chip to realize high-precision delay design, and its design flexibility has been greatly improved, which is suitable for wide application and promotion.

[0018] In one possible design, determining a coarse delay time and a fine delay time of the signal to be delayed based on the delay time and the target period includes:

[0019] The delay time and the target period are rounded up to obtain a rounded-up result as the coarse delay time, and the delay time and the target period are modulo-operated to obtain a modulo-operated result as the fine delay time.

[0020] Based on the above disclosed content, the present invention discloses a specific calculation method for the coarse delay time and the fine delay time, that is, rounding and modulo operations are performed on the delay time and the target period, wherein the rounding result is used as the coarse delay time, and the modulo result is used as the fine delay time.

[0021] In one possible design, the delay time includes increasing the delay time or decreasing the delay time, wherein, according to the coarse delay time, determining the actual read address of the signal to be delayed when it is first read in the memory includes:

[0022] If the delay time is an increased delay time, the initial read address is used as the delay starting point, and k address bits are extended forward to obtain the actual read address after the extension, wherein k is the coarse delay time;

[0023] If the delay time is a reduced delay time, the initial read address is used as the delay starting point, and the delay is extended backward by k+1 address bits, so as to obtain the actual read address after the extension;

[0024] Accordingly, determining the amount of data of the signal to be delayed when first read from the memory based on the fine delay time includes:

[0025] Based on the target period and the amount of data of any parallelized data, calculate the time corresponding to each bit of data in any parallelized data;

[0026] Determine an intermediate value according to the fine delay time and the time corresponding to each bit of data in any parallelized data;

[0027] If the delay time is an increased delay time, the difference between the data volume of any parallelized data and the intermediate value is used as the data volume of the signal to be delayed when it is first read from the memory;

[0028] If the delay time is a reduced delay time, the intermediate value is used as the data amount when the signal to be delayed is first read from the memory.

[0029] Based on the above disclosed content, the present invention discloses a process for determining the actual read address and the amount of data read for the first time, that is, if the delay time is to increase the delay time, that is, to delay sending, then the initial read address is used as the delay starting point, and k address bits are postponed forward (k is the coarse delay time), and if the delay time is to reduce the delay time, that is, to send in advance, then the initial read address is used as the delay starting point, and k+1 address bits are postponed backward; accordingly, the amount of data read for the first time is first calculated based on the target cycle and the amount of data of any parallelized data for each ratio in the parallelized data. The time corresponding to the special data is obtained, and then the amount of data read for the first time is calculated based on the fine delay time and the time corresponding to each bit of data mentioned above; for example, if the target period is 5000ps, the amount of data of any parallelized data is 50 bits, and the fine delay time is 2500ps, then 5000 is first divided by 50 to obtain the time corresponding to each bit of data as 100ps, and then 2500 is divided by 100, and the result is the intermediate value. Finally, the amount of data read for the first time is calculated based on the intermediate value according to whether it is delayed or sent in advance.

[0030] In one possible design, the size of any parallelized data is N bits, and N is the parallelization factor of the serializer;

[0031] When reading data for the first time, taking the actual read address as the reading starting point, reading the parallelized data corresponding to the actual read address, and selecting m bits of data from the parallelized data corresponding to the actual read address as the first data, including:

[0032] Reading the first m bits of data from the parallelized data corresponding to the actual read address as read data;

[0033] Using the read data as the high bit of the N-bit bit stream data corresponding to the first read, and inserting p-bit data before the read data, so as to obtain the first data after the insertion is completed, wherein the binary numbers corresponding to the p-bit data are all 0, and p is the difference between N and m;

[0034] Accordingly, when reading data for the i-th time, reading the parallelized data corresponding to the first target address, and selecting the first n bits of data from the parallelized data corresponding to the first target address to be spliced with the remaining data in the previous address of the first target address to obtain the second data, including:

[0035] Use the remaining data in the previous address of the first target address as the lower bits in the N-bit bitstream data corresponding to the i-th data reading, and use the previous n-bit data as the upper bits in the N-bit bitstream data corresponding to the i-th data reading. Then, concatenate the remaining data and the previous n-bit data in the order of lower bits first and upper bits second to obtain the second data.

[0036] Based on the above-disclosed content, the present invention discloses the specific process of data reading and concatenation. That is, in the parallelized data corresponding to the actual reading address, m-bit data is selected as the reading data. That is, on the basis of the above example, the first 25-bit data is selected as the reading data. If the amount of data in the parallelized data is 50 bits, then 25 bits of 0 need to be inserted before the 25-bit data to form the first data. Then, when performing the next reading, the parallelized data at the next address of the actual reading address is read. Then, the remaining 25-bit data read for the first time is concatenated with the previous 25-bit data read this time to obtain the second data. By continuously reading and concatenating according to this principle, the delay processing of the signal to be delayed can be completed.

[0037] In a possible design, based on the serializer, convert the first data into a first serial data for output, including:

[0038] Obtain the serialization order of the serializer and determine whether the data format of the first data is the same as the serialization order, where the data format is used to represent the arrangement order of the lower bits and upper bits in the first data;

[0039] If not, based on the serializer, adjust the data format of the first data to serialize the first data according to the adjusted data format to obtain the first serial data.

[0040] In a possible design, if the fine delay time is equal to 0, the method further includes:

[0041] According to the coarse delay time, determine the actual reading address in the memory, and when reading the data for the i-th time, read the parallelized data in the address corresponding to the i-th data reading as the first data, where i starts from 1 and is a positive integer, and the address corresponding to the first data reading is the actual reading address;

[0042] Based on the serializer, convert the first data into a first serial data for output;

[0043] Increment i by 1 until all the parallelized data in the memory is read, so as to complete the serial delay output of the signal to be delayed after reading.

[0044] In a possible design, the amount of data of any parallelized data is N bits, and N is the parallelization factor of the serializer. Wherein, the method further includes:

[0045] Determine the actual write address in the memory according to the coarse delay time, and determine the amount of data written for the first time from the memory by the signal to be delayed according to the fine delay time;

[0046] When writing data for the first time, keep the read address of the memory as the second preset address, use the first h - 1 bit positions of the actual write address as bit 0 positions, and store the first m - bit data in the first parallelized data into the h - th to N - th bit positions of the actual write address, where h is the difference between N and m, and m is the bit value corresponding to the amount of data;

[0047] When writing data for the a - th time, splice the remaining data in the (a - 1)-th parallelized data and the first N - j bit data in the a - th parallelized data to obtain the stored data, where the remaining data in the (a - 1)-th parallelized data is the data after removing m - bit data from the (a - 1)-th parallelized data, j is the amount of data corresponding to the remaining data in the (a - 1)-th parallelized data, a starts from 2 and a is a positive integer;

[0048] Store the stored data in the second target address, where the second target address is the next address corresponding to the address when writing data for the (a - 1)-th time;

[0049] Increment a by 1 until all parallelized data are stored.

[0050] In a second aspect, a high - precision time delay device based on a serializer is provided, including:

[0051] A high - precision time data conversion unit, configured to obtain a signal to be delayed, and under the drive of a parallel clock, perform parallelization processing on the signal to be delayed to output a plurality of parallelized data respectively according to a target period, where the target period is the clock period of the parallel clock;

[0052] A storage unit, configured to store a plurality of parallelized data in a memory, and each address in the memory corresponds to a parallelized data;

[0053] A delay control unit, configured to obtain a delay time, and based on the delay time and the target period, determine the coarse delay time and the fine delay time of the signal to be delayed;

[0054] A delay control unit, configured to determine whether the fine delay time is greater than 0;

[0055] A delay control unit, configured to, when it is determined that the fine delay time is greater than 0, determine an actual read address when the signal to be delayed is first read from a memory according to the coarse delay time, and determine the amount of data when the signal to be delayed is first read from the memory according to the fine delay time;

[0056] A delay control unit, configured to, when first reading data, take the actual read address as a read starting point, read parallelized data corresponding to the actual read address, and select m-bit data from the parallelized data corresponding to the actual read address as first data, where m is a bit value corresponding to the amount of data, and during the reading process, keep the write address of the memory as a first preset address;

[0057] A serial processing unit, configured to convert the first data into first serial data for output based on a serializer;

[0058] A delay control unit, configured to, when reading data for the i-th time, read parallelized data corresponding to a first target address, and select the first n-bit data from the parallelized data corresponding to the first target address to splice with remaining data in the previous address of the first target address to obtain second data, where the first target address is the next address of the address corresponding to the (i - 1)-th data reading, the remaining data is the data obtained by removing m-bit data from the parallelized data corresponding to the previous address of the first target address, n is the difference between the amount of data of any parallelized data and the amount of data corresponding to the remaining data, i starts from 2, and i and n are positive integers;

[0059] A serial processing unit, configured to convert the second data into second serial data for output based on the serializer;

[0060] A delay control unit, configured to increment i by 1 until all the parallelized data in the memory is read, so as to complete the serialized delay output of the signal to be delayed after the reading is completed.

[0061] In a third aspect, another high-precision time delay device based on a serializer is provided. Taking the device as an electronic device as an example, it includes a memory, a processor, and a transceiver that are communicatively connected in sequence, where the memory is configured to store a computer program, the transceiver is configured to send and receive messages, and the processor is configured to read the computer program and execute the high-precision signal delay method based on the serializer as described in the first aspect or any possible design in the first aspect;

[0062] In a fourth aspect, a storage medium is provided, on which instructions are stored, and when the instructions run on a computer, the high-precision signal delay method based on the serializer as described in the first aspect or any possible design in the first aspect is executed.

[0063] In a fifth aspect, there is provided a computer program product comprising instructions which, when run on a computer, cause the computer to execute the serializer-based high-precision signal delay method as described in the first aspect or any one of the possible designs in the first aspect.

[0064] Advantageous effects:

[0065] (1) In the present invention, the signal is first converted into parallelized data, and then the serializer is used to serialize the parallelized data. In this way, the analog-to-digital conversion of the signal can be achieved to ensure the original output of the signal after delay. At the same time, without adjusting the memory write address, by adjusting the read address in the memory of the existing chip, the interval between the two can be increased or decreased, so as to achieve forward delay or backward delay when reading data. Therefore, the present invention can use the existing chip to implement the signal delay chain, thereby achieving picosecond-level signal delay without relying on a dedicated time delay chip, which not only reduces the cost, but also greatly improves the design flexibility by using the existing chip to implement the high-precision delay design, and is suitable for wide application and promotion. Description of the Drawings

[0066] Figure 1 It is a schematic flow chart of the steps of the serializer-based high-precision signal delay method provided by an embodiment of the present invention;

[0067] Figure 2 It is a schematic diagram of forward delay and backward delay provided by an embodiment of the present invention;

[0068] Figure 3 It is a schematic structural diagram of the serializer-based high-precision time delay device provided by an embodiment of the present invention;

[0069] Figure 4 It is a schematic structural diagram of the electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the present invention in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. It should be noted here that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation to the present invention.

[0071] It should be understood that although terms such as first and second may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, the first unit may be referred to as the second unit, and similarly, the second unit may be referred to as the first unit, without departing from the scope of the exemplary embodiments of the present invention.

[0072] It should be understood that for the term "and / or" that may appear herein, it is merely an association relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, B exists alone, and both A and B exist simultaneously; for the term " / and" that may appear herein, it describes another association object relationship, indicating that two relationships may exist. For example, A / and B may represent: A exists alone, and both A and B exist; additionally, for the character " / " that may appear herein, generally it represents that the associated objects before and after are in an "or" relationship.

[0073] Embodiment:

[0074] See Figure 1 As shown, the high-precision signal delay method based on a serializer provided in this embodiment can use an existing chip to implement a signal delay chain, thereby achieving a signal delay at the picosecond level without relying on a dedicated time delay chip, which not only reduces costs but also improves the flexibility of the design; in this embodiment, for example, this method can be but is not limited to being executed on the chip side with a serializer. It can be understood that the foregoing execution subject does not constitute a limitation to the embodiments of the present application. Correspondingly, the running steps of this method can be but are not limited to those shown in the following steps S1 to S10.

[0075] S1. Obtain the signal to be delayed, and under the drive of a parallel clock, perform parallelization processing on the signal to be delayed to output a plurality of parallelized data respectively according to a target period, where the target period is the clock period of the parallel clock; in specific applications, for example, it can be but is not limited to using a high-precision time-to-digital converter to perform parallelization processing on the signal to be delayed. Among them, the conversion accuracy of the high-precision time-to-digital converter can reach the picosecond level. At the same time, under the drive of the parallel clock, it outputs each parallelized data according to the clock period of the parallel clock, that is, one parallelized data is output per clock period; optionally, the data volume of any parallelized data is related to the parallelization factor of the serializer in the chip, that is, the data volume of any parallelized data is N bits, and N is the parallelization factor of the serializer in the chip.

[0076] After the parallelization of the signal to be delayed is completed, each piece of parallelized data can be stored in a memory. Thus, during subsequent reading, the delay of the signal to be delayed can be achieved by adjusting the read address in the memory. Specifically, when no delay is applied, the read address and the write address in the memory are fixed, and the interval between them is also fixed. Therefore, in this embodiment, the write address is kept unchanged, and the interval between the two is adjusted by adjusting the read address. After the interval is adjusted, the corresponding increase or decrease in delay can be achieved. For example, if the interval between the read address and the write address is reduced, it means sending in advance (i.e., reducing the delay), and if the interval between the two is increased, it means sending later (i.e., increasing the delay). In this way, based on the mechanism of the read and write addresses of the memory, the signal delay can be achieved based on the existing chip. Optionally, the delay processing is as shown in the following steps S2 to S10.

[0077] S2. Store a number of parallelized data in the memory, and each address in the memory corresponds to a piece of parallelized data. In specific applications, the storage is performed in the output order, that is, the parallelized data output in the first clock cycle is stored first, and then the parallelized data output in the second clock cycle is stored, and so on until all the parallelized data output in step S1 is stored. Optionally, for example, the memory can be but is not limited to RAM.

[0078] After the storage of the parallelized data is completed, the delay processing of the signal to be delayed can be carried out. In this embodiment, two delay times, namely a coarse delay time and a fine delay time, are used to achieve the delay processing of the aforementioned signal. Further, the coarse delay time is used to adjust the read address in the memory so as to obtain the actual read address for the first read in the memory after adjustment, and the fine delay time is used to determine the amount of data at the first read so as to complete the adjustment of the data read each time based on this amount of data. In this way, the corresponding read delay can be achieved during reading. The calculation process of the coarse and fine delay times is as shown in the following step S3.

[0079] S3. Obtain the delay time, and based on the delay time and the target period, determine the coarse delay time and the fine delay time of the signal to be delayed; in specific applications, it can be but not limited to rounding the delay time and the target period to use the rounding result as the coarse delay time, and performing a remainder operation on the delay time and the target period to use the remainder operation result as the fine delay time; Optionally, the above steps are explained with an example, assuming that the target period is 5ns, the delay time If it is 100.3ns, then divide 100.3 by 5 and round up. The result is the coarse delay time, that is, 20ns is the coarse delay time (if the delay is increased, it is sent after 20 target cycles, and if the delay is reduced, it is sent 20 target cycles in advance), and the remainder is 0.3ns, so the fine delay time is 0.3ns; of course, the calculation principle of the coarse delay time and the fine delay time for different delay times is the same as the aforementioned example principle, which will not be repeated here.

[0080] After the coarse delay time and the fine delay time are obtained, the signal delay adjustment is performed, as shown in the following steps S4 to S10.

[0081] S4. Determine whether the detailed delay time is greater than 0.

[0082] S5. If yes, then determining, based on the coarse delay time, an actual read address of the signal to be delayed when first read from the memory, and determining, based on the fine delay time, the data volume of the signal to be delayed when first read from the memory; in specific applications, as explained above, delays are divided into increasing delays and decreasing delays. Therefore, different delays result in different actual read addresses determined based on the coarse delay time, as shown below:

[0083] S51. If the delay time is an increased delay time, the initial read address is used as the delay starting point, and the delay is extended forward by k address bits to obtain the actual read address after the extension, wherein k is the coarse delay time; in specific applications, the initial read address is a preset address. For example, assuming that the memory has a total of 256 addresses, the initial read address can be, but is not limited to, the 0th address, see Figure 2 As shown, when the delay is increased (i.e., the delay time is the increased delay time), the 0th address is used as the delay starting point, and 20 address bits are extended forward. At this time, the actual read address is the 236th address; of course, the different coarse delay times and different initial read addresses have the same principle for determining the corresponding actual read addresses as the above example, which will not be repeated here.

[0084] Similarly, when the delay needs to be reduced, the corresponding actual read address determination process is shown in the following step S52.

[0085] S52. If the delay time is to reduce the delay time, the initial read address is used as the delay starting point, and the delay is postponed backward by k+1 address bits, so as to obtain the actual read address after the delay; in specific application, it is still explained based on the above example. If the delay is to be adjusted forward, then based on the 0th address, it is postponed backward by 21 address bits. At this time, the actual read address becomes the 21st address.

[0086] After determining the actual read address of the delayed signal when first reading in the memory based on the coarse delay time, the amount of data read in the memory when first reading data can be determined based on the fine delay time, as shown in the following steps S53-S54.

[0087] S53. Based on the target cycle and the data volume of any parallelized data, the time corresponding to each bit of data in any parallelized data is calculated; in specific applications, the time corresponding to each bit of data in any parallelized data can be obtained by, but is not limited to, dividing the target cycle by the data volume of any parallelized data. At the same time, since the accuracy of step S1 reaches the picosecond level when performing data parallelization, the transmission time of each bit of data in any parallelized data is also in picoseconds. Therefore, before calculation, the unit needs to be unified into picoseconds; if the target cycle is 5ns and the parallelization factor of the serializer is 50 (that is, the data volume of any parallelized data is 50 bits), then the time corresponding to each bit of data is: 5000ps / 50=100ps; of course, the principle of calculating the time per bit of data for different target cycles and parallelization factors is the same as the above example, and will not be repeated here.

[0088] After obtaining the time corresponding to each bit of data in any parallelized data, the data amount during the first reading can be calculated in combination with the fine delay time, as shown in the following steps S54 to S56.

[0089] S54. Determine an intermediate value based on the fine delay time and the time corresponding to each bit of data in any parallelized data; in specific application, it is still explained on the basis of the above example, that is, the fine delay time is 0.3ns, then the intermediate value is equal to 0.3ns / 100ps=300ps / 100ps=3. Of course, the calculated intermediate value is different for different fine delay times, and the calculation principle is consistent with the above example, which will not be repeated here.

[0090] After obtaining the intermediate value, the amount of data for the first read can be calculated based on the intermediate value according to the adjustment direction of the delay (ie, increasing the delay or decreasing the delay), as shown in the following steps S55 and S56.

[0091] S55. If the delay time is an increased delay time, then the difference between the data volume of any parallelized data and the intermediate value is used as the data volume when the signal to be delayed is first read from the memory.

[0092] S56. If the delay time is a decreased delay time, then the intermediate value is used as the data volume when the signal to be delayed is first read from the memory; in specific applications, it is still described based on the foregoing example. If the delay needs to be increased, then the data volume read for the first time is: N - 3 = 50 - 3 = 47 bit data; similarly, when the delay needs to be decreased, the data volume read for the first time is 3 bit data; of course, for different fine delay times, the calculation principle of the corresponding data volume read for the first time is the same as that in the foregoing example, and will not be elaborated here.

[0093] After determining the actual read address and data volume when first reading data from the memory, data can be read from the memory, so that during the reading process, the corresponding coarse delay time and fine delay time are delayed. The data reading process is as shown in the following steps S6 to S10.

[0094] S6. When first reading data, starting from the actual read address as the read starting point, read the parallelized data corresponding to the actual read address, and select m bit data from the parallelized data corresponding to the actual read address as the first data, where m is the bit value corresponding to the data volume, and during the reading process, keep the write address of the memory as the first preset address; in specific applications, whether the delay is increased or decreased, only the actual read address for the first reading is different, and during the reading process, the process of reading specific data in the actual read address is the same. Therefore, it can be described uniformly. At the same time, as previously described, each address in the memory corresponds to a parallelized data, and the data volume of each parallelized data is N bit. Therefore, when performing the first reading, the process of reading data is specifically as follows:

[0095] S61. Read the first m bit data from the parallelized data corresponding to the actual read address as the read data.

[0096] S62. Use the read data as the high bits in the N - bit bitstream data corresponding to the first reading, and insert p bit data before the read data, so that after the insertion is completed, the first data is obtained, where the binary numbers corresponding to the p bit data are all 0, and p is the difference between N and m.

[0097] Still based on the foregoing example, the foregoing steps S61 and S62 are elaborated:

[0098] If the delay time is to increase the delay time, then at the first reading, the parallelized data corresponding to the 236th bit address is read first, and then the first m bits of data are read from the parallelized data corresponding to the 236th bit address. As previously described, when the fine delay time is 300 ps, the amount of data read for the first time is calculated to be 47 bits of data. Then, the first 47 bits of data are read from the parallelized data corresponding to the 236th bit address. And since the amount of data of any parallelized data is 50 bits, therefore, its internal data is {b0, b1,..., b49}. Thus, the read data is {b0, b1, b2,..., b46}; at the same time, since the data is read according to the target cycle, the delayed output data should also be 50 bits. So, if the read data is less than 50 bits, data padding is required. In this embodiment, p bits of data are inserted in front of bit0, that is, 50 - 47 bits of 0 (represented by 3’b0) are inserted. Thus, the first data is the concatenation of 3 bits of 0 and the first 47 bits of data in the parallelized data corresponding to the 236th bit address, that is, the first data is {3’b0, b0, b1, b2,..., b46}.

[0099] Similarly, if the delay time is to decrease the delay time, then at the first reading, the parallelized data corresponding to the 21st bit address is read first, and then the first 3 bits of data are read from the parallelized data corresponding to the 21st bit address. At this time, 47 bits of data also need to be inserted in front of these 3 bits of data. Therefore, the first data obtained is {47’b0, b0, b1, b2}.

[0100] Of course, for different fine and coarse delay times, the first data reading process is the same as the previous examples and will not be elaborated here; after obtaining the second data, it can be input into the serializer in the chip for deserialization, so as to realize the serialized output of the address, as shown in step S7 below.

[0101] S7. Based on the serializer, convert the first data into first serial data for output; in specific applications, when performing serialization processing, it is also necessary to determine whether to adjust the high and low bits of the first data according to the serialization order of the serializer to meet the serialization order of the serializer. The adjustment process is shown in step S71 and step S72 below.

[0102] S71. Obtain a serialization sequence of the serializer, and determine whether a data format of the first data is the same as the serialization sequence, wherein the data format is used to characterize the arrangement order of low bits and high bits in the first data. In a specific application, the serialization sequence is serialized from low bits to high bits, or from high bits to low bits, and the data format is the order of high and low bits of the first data. Therefore, it is only necessary to compare whether the two are the same to determine whether to adjust the high and low bits. The adjustment process is shown in the following step S72.

[0103] S72. If not, based on the serializer, adjust the data format of the first data to serialize the first data according to the adjusted data format to obtain the first serial data; in specific application, if the serialization order is high to low, and the data format is low + high, then it is necessary to swap the low and high bits of the first data. After the swap is completed, serialization can be performed to obtain the first serial data.

[0104] When the first data reading is completed, the data reading of the next target cycle can be performed, as shown in the following step S8.

[0105] S8. When reading data for the i-th time, read the parallelized data corresponding to the first target address, and select the first n bits of data from the parallelized data corresponding to the first target address to splice with the remaining data in the previous address of the first target address to obtain second data, wherein the first target address is the next address of the address corresponding to the i-1-th time of reading data, the remaining data is the data after removing m bits of data from the parallelized data corresponding to the previous address of the first target address, n is the difference between the data amount of any parallelized data and the data amount corresponding to the remaining data, i starts from 2, and both i and n are positive integers; in specific application, when performing the second reading, that is, reading the next target cycle, it is necessary to postpone the address, that is, read the parallelized data corresponding to the next address of the actual read address, and then extract some data from the parallelized data read this time and splice it with the remaining data in the data read last time to obtain second data, wherein the specific splicing process is shown in the following step S81.

[0106] S81. Use the remaining data in the previous address of the first target address as the low bit in the N-bit bit stream data corresponding to the i-th reading of the data, and use the first n bits of data as the high bit in the N-bit bit stream data corresponding to the i-th reading of the data, and splice the remaining data and the first n bits of data in the order of low bit first and high bit last to obtain the second data.

[0107] In specific applications, the above delay time is still explained on the basis of increasing the delay time:

[0108] When i = 2, that is, when the second reading is performed, first, the parallelized data corresponding to the first target address is read. The first target address is the next address of the address corresponding to the data read in the (i - 1)-th reading, that is, the next address of the address corresponding to the data read in the first reading. Based on the fact that the address corresponding to the data read in the first reading is the 236-bit address, at this time, the first target address is the 237-bit address. Then, among the parallelized data corresponding to the 236-bit address, in this embodiment, only the first 47 bits of data are selected. Therefore, the remaining data in the parallelized data corresponding to the 236-bit address (i.e., the 47th - 49th bits of data) is used as the low bits of the bitstream data when the second reading is performed, and the first n (n = 50 - the remaining data = 50 - 3 = 47) bits of data in the parallelized data corresponding to the 237-bit address are used as the high bits of the bitstream data for storage. Assuming that the parallelized data corresponding to the 237-bit address is {b50, b51,..., b99}, then the second data is {b47, b48, b49, b50,..., b96}.

[0109] When i = 3, according to the same principle as described above, the remaining data in the parallelized data corresponding to the 237-bit address is used as the low bits, and the first 47 bits of data in the parallelized data corresponding to the 238-bit address are used as the high bits for splicing. The third data obtained is: {b97, b98, b99, b100,..., b146}; of course, each subsequent reading is performed according to the method exemplified above for data splicing. In this way, the reading of all the parallelized data in the memory can be completed.

[0110] In this embodiment, after each data splicing, the spliced data is input into a serializer for serialization processing, and the above steps are continuously looped to complete the reading and splicing of all the data in the memory, as shown in the following steps S9 and S10.

[0111] S9. Based on the serializer, convert the second data into second serial data for output.

[0112] S10. Increment i by 1 until all the parallelized data in the memory is read, so as to complete the serialized delay output of the signal to be delayed after the reading is completed; in specific applications, each time when reading, data is selected from the parallelized data read from the next address to splice with the remaining data in the data read from the previous address. In this way, the delay processing of the signal to be delayed can be realized during the reading.

[0113] In addition, in this embodiment, if the fine delay time is equal to 0, the method further includes:

[0114] S11. Determine the actual read address in the memory based on the coarse delay time, and when reading data for the i-th time, read the parallelized data within the address corresponding to the i-th data reading as the first data, where i starts from 1 and is a positive integer, and the address corresponding to the first data reading is the actual read address.

[0115] S12. Based on the serializer, convert the first data into first serial data for output.

[0116] S13. Increment i by 1 until all parallelized data in the memory are read, so as to complete the serialized delayed output of the signal to be delayed after the reading is completed.

[0117] In this embodiment, when the fine delay time is 0, it means that only the read address in the memory needs to be adjusted without data splicing; for example, assuming that the delay time is 100ns, the coarse delay time is 20, and on the basis of increasing the delay time, it is equivalent to postponing the initial read address forward by 20 address bits, that is, reading the parallelized data corresponding to the 236th address as the first data, and then directly reading the parallelized data corresponding to the 237th address during the second reading, and reading the parallelized data corresponding to the 238th address during the third reading, and so on, to complete the reading of all parallelized data in the memory; of course, the principle of forward delay is the same, and the process will not be repeated.

[0118] Therefore, through the above detailed explanation of the high-precision signal delay method based on the serializer, the present invention can use existing chips to implement the signal delay chain, thereby achieving picosecond-level signal delay without relying on dedicated time delay chips. This not only reduces costs, but also uses existing chips to achieve high-precision delay design, and its design flexibility is greatly improved, making it suitable for wide application and promotion.

[0119] In a possible design, the second aspect of this embodiment is further optimized based on the first aspect of the embodiment, and delay processing of the signal to be delayed is implemented from the data writing level of the memory, as shown in the following steps S14 to S18.

[0120] S14. Determine the actual write address in the memory based on the coarse delay time, and determine the amount of data initially written from the memory by the signal to be delayed based on the fine delay time. In specific applications, when the delay time is increasing, the process for determining the actual write address is the same as the process for determining the actual read address corresponding to the aforementioned decreasing delay time, i.e., starting from the initial write address and extending backward by k address bits; and when the delay time is decreasing, also starting from the initial write address and extending forward by k+1 address bits, as shown in FIG.Figure 2 As shown, assuming that the initial write address is the 128th bit and the coarse delay time is also 20, when reducing the delay, starting from the 128th bit, 21 address bits are sequentially shifted forward, and the actual write address is then the 107th bit; in this embodiment, when adjusting the write address, based on the fine delay time, the amount of data written for the first time is determined by directly using the aforementioned intermediate value as the amount of data written for the first time.

[0121] After determining the actual write address and the amount of data written for the first time, parallelized data can be written. The writing process is as shown in the following steps S15 to S18.

[0122] S15. When writing data for the first time, keep the read address of the memory as the second preset address, and use the first h - 1 bit positions of the actual write address as the bit 0 position, and store the first m - bit data in the first parallelized data into the hth to Nth bit positions of the actual write address, where h is the difference between N and m, and m is the bit value corresponding to the amount of data.

[0123] S16. When writing data for the a-th time, splice the remaining data in the (a - 1)-th parallelized data and the first N - j bit data in the a-th parallelized data to obtain the stored data, where the remaining data in the (a - 1)-th parallelized data is the data in the (a - 1)-th parallelized data after removing m - bit data, j is the data corresponding to the remaining data in the (a - 1)-th parallelized data, a starts from 2, and a is a positive integer.

[0124] S17. Store the stored data at the second target address, where the second target address is the next address corresponding to the address when writing data for the (a - 1)-th time.

[0125] S18. Increment a by 1 until all parallelized data is stored.

[0126] The following uses an example to illustrate the aforementioned steps S15 to S18:

[0127] When the delay time is the increased delay time and the delay time is also 100.3 ns, then the amount of data written for the first time is 3, that is, m = 3, N = 50. Then, the actual write address is: the 148th bit, and the amount of data written for the first time is 3-bit data. Among them, when writing for the first time, the first 3-bit data in the first parallelized data is stored in the hth to Nth bits of the 148th bit address. Among them, h = 50 - 3 = 47, that is, it is stored in the 47th, 48th, and 49th bits of the 148th bit address. At the same time, the amount of data written in one cycle must also meet 50 bits (that is, the amount of data of the parallelizable data is the same). Therefore, padding is required, that is, the first h - 1 bits of the 148th bit address are used as the 0-bit, that is, bits 0 to 46 of the 148th bit address are filled with 0 bits. In this way, the first data writing can be completed; when a = 2, the remaining data in the first parallelized data is concatenated with the first 50 - j bits of data in the second parallelized data. Specifically, the remaining data in the first parallelized data is 50 - 3 = 47, that is, there are 47 bits of remaining data (i.e., b3 - b49). Therefore, it is concatenated with the first 3 bits of data in the second parallel data and then stored in the next address corresponding to the address where the data was written for the first time, that is, written to the 149th bit address; based on this principle, data concatenation is continuously performed and then stored to complete the writing of all parallelized data.

[0128] In this embodiment, when the delay time is a forward delay, its writing process is the same as that of the backward delay process, which will not be elaborated here.

[0129] In addition, in this embodiment, the write address and read address of the memory can also be adjusted simultaneously. Of course, it is also adjusted based on the coarse delay time. If the fine delay time is greater than 0, at this time, to increase the delay (that is, the delay time is the increased delay time) and the coarse delay time is 10, that is, to delay k cycles (that is, 10 cycles). Therefore, when adjusting the address, as long as the distance between the write address and the read address is increased by 10 cycles on the original basis; for example, the write address can be adjusted forward and backward by 2 address bits, and the read address can be adjusted forward by 8 address bits; after the adjustment is completed, data can be written using the adjusted write address, or data can be written using the adjusted read address. The writing processes of the two can refer to the first aspect and the second aspect of the foregoing embodiment; of course, the method for forward delay is the same, which will not be elaborated here.

[0130] As Figure 3 shown, the second aspect of this embodiment provides a hardware device for implementing the high-precision signal delay method based on a serializer described in the first aspect of the embodiment, including:

[0131] A high-precision time data conversion unit is used to obtain a signal to be delayed, and under the drive of a parallel clock, parallelize the signal to be delayed to output a plurality of parallelized data respectively according to a target period, where the target period is the clock period of the parallel clock.

[0132] A storage unit is used to store a plurality of parallelized data into a memory, and each address in the memory corresponds to a parallelized data.

[0133] A delay control unit is used to obtain a delay time, and based on the delay time and the target period, determine the coarse delay time and the fine delay time of the signal to be delayed.

[0134] The delay control unit is used to judge whether the fine delay time is greater than 0.

[0135] When judging that the fine delay time is greater than 0, the delay control unit determines the actual read address when the signal to be delayed is first read from the memory according to the coarse delay time, and determines the data volume when the signal to be delayed is first read from the memory according to the fine delay time.

[0136] When first reading data, the delay control unit takes the actual read address as the read starting point, reads the parallelized data corresponding to the actual read address, and selects m-bit data from the parallelized data corresponding to the actual read address as the first data, where m is the bit value corresponding to the data volume, and during the reading process, keeps the write address of the memory as a first preset address.

[0137] A serial processing unit is used to convert the first data into a first serial data for output based on a serializer.

[0138] When reading data for the i-th time, the delay control unit reads the parallelized data corresponding to a first target address, and selects the first n-bit data from the parallelized data corresponding to the first target address to splice with the remaining data in the previous address of the first target address to obtain a second data, where the first target address is the next address corresponding to the address when reading data for the (i - 1)-th time, the remaining data is the data after removing m-bit data from the parallelized data corresponding to the previous address of the first target address, n is the difference between the data volume of any parallelized data and the data volume corresponding to the remaining data, i starts from 2, and i and n are positive integers.

[0139] A serial processing unit is used to convert the second data into a second serial data for output based on the serializer.

[0140] A delay control unit, which is configured to increment i by 1 until all the parallelized data in the memory is read out, so as to complete the serialized delay output of the to-be-delayed signal after the reading is completed.

[0141] For the working process, working details and technical effects of the device provided in this embodiment, reference can be made to the first aspect and the second aspect of the embodiment, which will not be elaborated here.

[0142] As Figure 4 shown, a third aspect of this embodiment provides another high-precision time delay device based on a serializer. Taking the device as an electronic device as an example, it includes: a memory, a processor, and a transceiver that are communicatively connected in sequence, where the memory is used to store computer programs, the transceiver is used to send and receive messages, and the processor is used to read the computer programs and execute the high-precision signal delay method based on a serializer as described in the first aspect and / or the second aspect of the embodiment.

[0143] Specifically, the memory may include, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a flash memory, a first-in-first-out memory (FIFO), and / or a first-in-last-out memory (FILO), etc.; specifically, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). At the same time, the processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state.

[0144] In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit). The GPU is responsible for rendering and drawing the content to be displayed on the display screen. For example, the processor may not be limited to using a microprocessor of the STM32F105 series, a reduced instruction set computer (RISC) microprocessor, an X86 architecture processor, or a processor integrated with an embedded neural-network processing unit (NPU); the transceiver may be, but is not limited to, a Wi-Fi wireless transceiver, a Bluetooth wireless transceiver, a General Packet Radio Service (GPRS) wireless transceiver, a ZigBee (low-power local area network protocol based on the IEEE 802.15.4 standard) wireless transceiver, a 3G transceiver, a 4G transceiver, and / or a 5G transceiver, etc. In addition, the device may also include, but is not limited to, a power module, a display screen, and other necessary components.

[0145] For the working process, working details, and technical effects of the electronic device provided in this embodiment, reference may be made to the first aspect of the embodiment, which will not be elaborated herein.

[0146] In the fourth aspect of this embodiment, there is provided a storage medium storing instructions including the serializer-based high-precision signal delay method described in the first aspect of the embodiment, that is, instructions are stored on the storage medium. When the instructions are run on a computer, the serializer-based high-precision signal delay method described in the first aspect and / or the second aspect is executed.

[0147] Among them, the storage medium refers to a carrier for storing data, and may include, but is not limited to, a floppy disk, an optical disc, a hard disk, a flash memory, a USB flash drive, and / or a Memory Stick, etc. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0148] For the working process, working details, and technical effects of the storage medium provided in this embodiment, reference may be made to the first aspect of the embodiment, which will not be elaborated herein.

[0149] In the fifth aspect of this embodiment, there is provided a computer program product including instructions. When the instructions are run on a computer, the computer is caused to execute the serializer-based high-precision signal delay method described in the first aspect and / or the second aspect of the embodiment, where the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0150] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A serializer-based high-precision signal delay method, characterized in that include: Acquire a signal to be delayed, and perform parallel processing on the signal to be delayed under the drive of a parallel clock, so as to output a plurality of parallelized data respectively according to a target period, wherein the target period is a clock period of the parallel clock; Storing a plurality of parallelized data in a memory, wherein each address in the memory corresponds to a parallelized data; Obtaining a delay time, and determining a coarse delay time and a fine delay time of the signal to be delayed based on the delay time and the target period; Determine whether the fine delay time is greater than 0; If yes, determining the actual read address of the signal to be delayed when first read from the memory according to the coarse delay time, and determining the data volume of the signal to be delayed when first read from the memory according to the fine delay time; When reading data for the first time, taking the actual read address as a reading starting point, reading the parallelized data corresponding to the actual read address, and selecting m bits of data from the parallelized data corresponding to the actual read address as the first data, where m is a bit value corresponding to the amount of data, and during the reading process, maintaining the write address of the memory at the first preset address; Based on the serializer, convert the first data into first serial data for output; When reading data for the i-th time, read the parallelized data corresponding to the first target address, and select the first n bits of data from the parallelized data corresponding to the first target address to splice with the remaining data in the previous address of the first target address to obtain second data, wherein the first target address is the next address of the address corresponding to the (i-1)-th time of reading data, the remaining data is the data after removing m bits of data from the parallelized data corresponding to the previous address of the first target address, n is the difference between the data amount of any parallelized data and the data amount corresponding to the remaining data, i starts from 2, and i and n are positive integers; Based on the serializer, convert the second data into second serial data for output; Increment i by 1 until all parallelized data in the memory are read, so as to complete the serialized delayed output of the signal to be delayed after the reading is completed; Wherein, based on the delay time and the target period, determining the coarse delay time and the fine delay time of the signal to be delayed includes: The delay time and the target period are rounded up to obtain a rounded-up result as the coarse delay time, and the delay time and the target period are modulo-operated to obtain a modulo-operated result as the fine delay time.

2. The method according to claim 1, wherein The delay time includes increasing the delay time or decreasing the delay time, wherein, according to the coarse delay time, determining the actual read address of the signal to be delayed when it is first read in the memory includes: If the delay time is an increased delay time, the initial read address is used as the delay starting point, and k address bits are extended forward to obtain the actual read address after the extension, wherein k is the coarse delay time; If the delay time is a reduced delay time, the initial read address is used as the delay starting point, and the delay is extended backward by k+1 address bits, so as to obtain the actual read address after the extension; Accordingly, determining the amount of data of the signal to be delayed when first read from the memory based on the fine delay time includes: Based on the target period and the amount of data of any parallelized data, calculate the time corresponding to each bit of data in any parallelized data; Determine an intermediate value according to the fine delay time and the time corresponding to each bit of data in any parallelized data; If the delay time is an increased delay time, the difference between the data volume of any parallelized data and the intermediate value is used as the data volume of the signal to be delayed when it is first read from the memory; If the delay time is a reduced delay time, the intermediate value is used as the data amount when the signal to be delayed is first read from the memory.

3. The method according to claim 1, characterized in that, The data size of any parallelized data is N bits, and N is the parallelization factor of the serializer; When reading data for the first time, taking the actual read address as the reading starting point, reading the parallelized data corresponding to the actual read address, and selecting m bits of data from the parallelized data corresponding to the actual read address as the first data, including: Reading the first m bits of data from the parallelized data corresponding to the actual read address as read data; Using the read data as the high bit of the N-bit bit stream data corresponding to the first read, and inserting p-bit data before the read data, so as to obtain the first data after the insertion is completed, wherein the binary numbers corresponding to the p-bit data are all 0, and p is the difference between N and m; Accordingly, when reading data for the i-th time, reading the parallelized data corresponding to the first target address, and selecting the first n bits of data from the parallelized data corresponding to the first target address to be spliced with the remaining data in the previous address of the first target address to obtain the second data, including: The remaining data in the previous address of the first target address is used as the low bit in the N-bit bit stream data corresponding to the i-th reading of the data, and the first n bits of data are used as the high bit in the N-bit bit stream data corresponding to the i-th reading of the data, and the remaining data and the first n bits of data are spliced in the order of low bit first and high bit last to obtain the second data.

4. The method according to claim 1, wherein The method of converting the first data into first serial data for output based on a serializer includes: Obtaining a serialization sequence of a serializer, and determining whether a data format of the first data is the same as the serialization sequence, wherein the data format is used to represent an arrangement order of low bits and high bits in the first data; If not, adjusting the data format of the first data based on the serializer, so as to perform serialization processing on the first data according to the adjusted data format to obtain the first serial data.

5. The method according to claim 1, characterized in that, If the fine delay time is equal to 0, the method further includes: Based on the coarse delay time, determine the actual read address in the memory, and when reading data for the i-th time, read the parallelized data in the address corresponding to the i-th data reading as the first data, where i starts from 1 and is a positive integer, and the address corresponding to the first data reading is the actual read address; Based on a serializer, convert the first data into first serial data for output; Increment i by 1 until all the parallelized data in the memory is read out, so as to complete the serial delay output of the to-be-delayed signal after reading is completed.

6. The method according to claim 1, wherein The data volume of any parallelized data is N bits, and N is the parallelization factor of the serializer, where the method further includes: Based on the coarse delay time, determine the actual write address in the memory, and based on the fine delay time, determine the data volume of the first write of the to-be-delayed signal from the memory; When writing data for the first time, keep the read address of the memory as the second preset address, and use the first h - 1 bit positions of the actual write address as bit 0 positions, and store the first m-bit data in the first parallelized data into the h-th to N-th bit positions of the actual write address, where h is the difference between N and m, and m is the bit value corresponding to the data volume; When writing data for the a-th time, splice the remaining data in the (a - 1)-th parallelized data and the first N - j bit data in the a-th parallelized data to obtain stored data, where the remaining data in the (a - 1)-th parallelized data is the data in the (a - 1)-th parallelized data after removing m-bit data, j is the data volume corresponding to the remaining data in the (a - 1)-th parallelized data, a starts from 2 and is a positive integer; Store the stored data in the second target address, where the second target address is the next address corresponding to the address when writing data for the (a - 1)-th time; Increment a by 1 until all the parallelized data is stored.

7. A serializer-based high-precision signal delay device, characterized in that It includes: A high-precision time data conversion unit, configured to obtain a to-be-delayed signal, and under the drive of a parallel clock, perform parallelization processing on the to-be-delayed signal to output a plurality of parallelized data respectively according to a target period, where the target period is the clock period of the parallel clock; A storage unit, configured to store a plurality of parallelized data in a memory, and each address in the memory corresponds to a parallelized data; A delay control unit, configured to obtain a delay time, and based on the delay time and the target period, determine the coarse delay time and the fine delay time of the to-be-delayed signal; where, based on the delay time and the target period, determining the coarse delay time and the fine delay time of the to-be-delayed signal includes: performing a rounding operation on the delay time and the target period to use the rounding operation result as the coarse delay time, and performing a remainder operation on the delay time and the target period to use the remainder operation result as the fine delay time; A delay control unit, configured to determine whether the fine delay time is greater than 0; A delay control unit, configured to, when it is determined that the fine delay time is greater than 0, determine an actual read address when the signal to be delayed is first read from a memory according to the coarse delay time, and determine a data amount when the signal to be delayed is first read from the memory according to the fine delay time; The delay control unit is configured to, when reading data for the first time, start reading from the actual read address, read the parallelized data corresponding to the actual read address, and select m-bit data from the parallelized data corresponding to the actual read address as the first data, where m is the bit value corresponding to the data amount, and during the reading process, keep the write address of the memory as a first preset address; A serial processing unit, configured to convert the first data into a first serial data for output based on a serializer; The delay control unit is configured to, when reading data for the i-th time, read the parallelized data corresponding to a first target address, and select the first n-bit data from the parallelized data corresponding to the first target address to splice with the remaining data in the previous address of the first target address to obtain second data, where the first target address is the next address of the address corresponding to the (i-1)-th data reading, the remaining data is the data obtained by removing m-bit data from the parallelized data corresponding to the previous address of the first target address, n is the difference between the data amount of any parallelized data and the data amount corresponding to the remaining data, i starts from 2, and i and n are positive integers; A serial processing unit, configured to convert the second data into a second serial data for output based on the serializer; The delay control unit is configured to increment i by 1 until all the parallelized data in the memory is read, so as to complete the serialized delay output of the signal to be delayed after the reading is completed.

8. An electronic device, characterized in that, Comprising: A memory, a processor, and a transceiver that are communicatively connected in sequence, where the memory is configured to store a computer program, the transceiver is configured to send and receive messages, and the processor is configured to read the computer program and execute the high-precision signal delay method based on a serializer according to any one of claims 1 to 6.

9. A storage medium, characterized in that, Instructions are stored on the storage medium, and when the instructions are run on a computer, the high-precision signal delay method based on a serializer according to any one of claims 1 to 6 is executed.

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