Method and device for reducing crosstalk of earphone, signal processing circuit and chip

Abstract

A method and device for reducing crosstalk of earphone, signal processing circuit and chip, the method comprises the following steps: disconnecting a connection end of a codec module and a second sound channel of an earphone seat, and collecting crosstalk signals of the second sound channel under the condition that a test audio signal is input to a first sound channel of the earphone and a mute signal is input to the second sound channel; determining a signal adjustment gain according to the crosstalk signals; adjusting first sound channel to-be-decoded audio signals and second sound channel to-be-decoded audio signals according to the signal adjustment gain when the earphone is working, and ensuring that the adjusted first sound channel to-be-decoded audio signals and the second sound channel to-be-decoded audio signals are of the same phase, and outputting the adjusted to-be-decoded audio signals to the codec module. By using the application, the crosstalk problem of the earphone sound channel can be effectively solved, and the stereo sound effect of the earphone is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of audio processing, in particular to a method and device for reducing earphone crosstalk, and a signal processing circuit and chip. BACKGROUND

[0002] At present, with the popularization of mobile networks, audio and video multimedia is increasingly favored by consumers. Earphone mode is gradually favored by more and more users because of its delicate sound quality and realistic stereo effect. However, due to the common ground of left and right sound channels of the earphone, the voltage division of the left channel electrical signal on the ground will affect the right channel, and the voltage division of the right channel electrical signal on the ground will affect the left channel, which will form sound crosstalk at the earphone interface, reduce the sound quality, and affect the user experience.

[0003] In order to ensure good stereo effect, a certain degree of isolation is required between left and right channels, that is, the crosstalk between the two channels needs to be less than a certain standard, and how to effectively reduce the crosstalk between the two channels is an important problem to be solved in the industry. SUMMARY

[0004] Embodiments of the present application provide a method and device for reducing earphone crosstalk, which solves the problem of earphone channel crosstalk and improves the stereo effect of the earphone.

[0005] To this end, embodiments of the present application provide the following technical solutions:

[0006] In one aspect, the present application provides a method for reducing earphone crosstalk, the method comprising:

[0007] Collecting crosstalk signals of the second channel when the second channel output end of the codec module is disconnected, and the first channel input of the earphone tests an audio signal and the second channel input is silent;

[0008] Determining a signal adjustment gain according to the crosstalk signals;

[0009] Adjusting the first channel to be decoded audio signal and the second channel to be decoded audio signal according to the signal adjustment gain when the earphone is working, and ensuring that the adjusted first channel to be decoded audio signal and the second channel to be decoded audio signal have the same phase, and outputting the adjusted to be decoded audio signal to the codec module.

[0010] Optionally, the collecting of the crosstalk signals of the second channel comprises:

[0011] Collecting the audio signal of the second channel output end of the codec module, and taking the collected audio signal as the crosstalk signal of the second channel.

[0012] Optionally, the determining of the gain of the to-be-decoded audio signal according to the crosstalk signal comprises:

[0013] convert the crosstalk signal into a digital signal;

[0014] determine the signal adjustment gain according to the digital signal.

[0015] Optionally, the determining the signal adjustment gain according to the crosstalk signal comprises:

[0016] determining the signal adjustment gain according to the following formula:

[0017] X_GAIN = V_ADC x R_Cali;

[0018] wherein X_GAIN is the signal adjustment gain, R_Cali is a calibration coefficient, and V_ADC is the digital signal.

[0019] Optionally, the adjusting the first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal according to the signal adjustment gain and outputting the adjusted to-be-decoded audio signal to the codec module comprises:

[0020] the first channel adjusted audio signal output to the codec module is HPR x X_Gain + HPL x (1-X_Gain);

[0021] the second channel adjusted to-be-decoded audio signal output to the codec module is HPL x X_Gain + HPR x (1-X_Gain);

[0022] wherein HPL is the first channel to-be-decoded audio signal, HPR is the second channel to-be-decoded audio signal, and X_Gain is the signal adjustment gain.

[0023] In another aspect, the embodiment of the present application also provides a device for reducing crosstalk of a headset, the device comprising:

[0024] a crosstalk signal collection module, configured to collect a crosstalk signal of a second channel when a second channel output end of a codec module is disconnected and a first channel of a headset inputs a test audio signal and a second channel inputs a mute signal;

[0025] a gain determination module, configured to determine a signal adjustment gain according to the crosstalk signal;

[0026] a signal processing module, configured to, when the headset is working, adjust a first channel to-be-decoded audio signal and a second channel to-be-decoded audio signal according to the signal adjustment gain, ensure that the adjusted first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal are of the same phase, and output the adjusted to-be-decoded audio signal to the codec module.

[0027] Optionally, the crosstalk signal collecting module comprises:

[0028] a switch unit configured to disconnect the second channel output end of the codec module;

[0029] a collecting unit configured to collect an audio signal of the output end of the second channel of the codec module and take the collected audio signal as a crosstalk signal of the second channel.

[0030] Optionally, the gain determining module comprises:

[0031] an analog-to-digital conversion unit configured to convert the crosstalk signal of the second channel into a digital signal;

[0032] a calculation unit configured to determine the signal adjustment gain according to the digital signal.

[0033] Optionally, the signal processing module is specifically configured to, when the earphone is working, input a first channel to-be-decoded audio signal and a second channel to-be-decoded audio signal, adjust the to-be-decoded audio signal, and output the first channel adjusted audio signal: HPR X Gain+HPL X(1-X Gain) and the second channel adjusted audio signal: HPL X Gain+HPR X(1-X Gain) to the codec module, where HPL is the first channel to-be-decoded adjusted audio signal, HPR is the second channel to-be-decoded audio signal, and X Gain is the signal adjustment gain.

[0034] In another aspect, the embodiment of the present application also provides a signal processing circuit for processing a dual-channel earphone audio signal, the circuit comprising: a digital signal processing circuit and / or a codec circuit;

[0035] The codec circuit comprises a first channel codec unit, a second channel codec unit, a sampling signal conversion unit, and a switching switch arranged at the output end of the second channel codec unit and the connection end of the earphone seat, the switching switch comprising one fixed end and two switching ends, the fixed end being connected with the second channel output end of the codec circuit, the first switching end being connected with the output end of the second channel codec unit, and the second switching end being connected with the input end of the sampling signal conversion unit;

[0036] The digital signal processing circuit comprises a first processing unit, a second processing unit, and a crosstalk calibration unit; the first processing unit inputs a first channel to-be-decoded audio signal and outputs a first calibration signal to the first channel codec unit; the second processing unit inputs a second channel to-be-decoded audio signal and outputs a second calibration signal to the second channel codec unit;

[0037] In the crosstalk calibration, the second switching end of the switch is connected with the fixed end, the first processing unit inputs the first channel audio signal to be decoded as a test audio signal, and the second processing unit inputs the second channel audio signal to be decoded as a mute signal; the sampling signal conversion unit collects the crosstalk signal of the second channel, converts the crosstalk signal into a digital signal, and inputs the digital signal into the crosstalk calibration unit; the crosstalk calibration unit determines the signal adjustment gain according to the crosstalk signal.

[0038] After the crosstalk calibration is completed, the first switching end of the switch is connected with the fixed end; in the earphone working process, the first processing unit and the second processing unit respectively adjust the first channel audio signal to be decoded and the second channel audio signal to be decoded according to the signal adjustment gain, ensure that the adjusted first channel audio signal to be decoded and the second channel audio signal to be decoded are in the same phase, and output the adjusted audio signal to be decoded to the codec circuit.

[0039] Optionally, the first processing unit outputs the first calibration signal to the first channel codec unit as HPR*X_Gain+HPL*(1-X_Gain); and the second processing unit outputs the second calibration signal to the second channel codec unit as HPL*X_Gain+HPR*(1-X_Gain).

[0040] Wherein, HPL is the first channel audio signal to be decoded, HPR is the second channel audio signal to be decoded, and X_Gain is the signal adjustment gain.

[0041] In another aspect, the embodiment of the present application further provides a signal processing chip, which comprises the signal processing circuit as described above.

[0042] The method and device for reducing crosstalk of an earphone, the signal processing circuit and the chip provided by the embodiment of the present application are used in the case that the connection end of the codec module and the second channel of the earphone seat is disconnected, the first channel of the earphone inputs a test audio signal, and the second channel inputs a mute signal, the crosstalk signal of the second channel is collected, the signal adjustment gain is determined according to the collected crosstalk signal, the first channel audio signal to be decoded and the second channel audio signal to be decoded are adjusted according to the signal adjustment gain, and the adjusted audio signal to be decoded is output to the codec module. The present application scheme compensates the crosstalk caused by the signals of different channels of the earphone by using the in-phase gain correction method, effectively improves the anti-crosstalk performance of the earphone, and saves the hardware cost. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a schematic diagram of an existing earphone circuit;

[0044] Figure 2is a flow chart of the method for reducing the crosstalk of earphones according to an embodiment of the present application;

[0045] Figure 3 is a structural schematic diagram of the device for reducing the crosstalk of earphones according to an embodiment of the present application;

[0046] Figure 4 is a structural schematic diagram of the signal processing circuit according to an embodiment of the present application;

[0047] Figure 5 is an application schematic diagram of the signal processing circuit in the earphone circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0049] The voice processing circuit mainly includes two parts: a digital voice processor and a voice codec circuit. When playing audio through earphones, the audio signals of left and right channels are processed by the digital voice processor to obtain pure digital audio signals, such as PCM (Pulse Code Modulation) signals, which are sent to the voice codec circuit through a digital audio interface for digital-to-analog conversion to restore analog audio signals, which are then amplified by an earphone amplifier and finally reach the earphone interface.

[0050] The 3.5mm earphone interface (a coaxial audio jack with a diameter of 3.5mm) is widely used in consumer products due to its long history, unified standard, low cost and stable connection. The implementation scheme of the USB Type-C earphone interface plus an adapter is the same as that of the 3.5mm earphone. Because of the contact impedance of the 3.5mm earphone and the mechanical interface of the Type-C and the impedance of the PCB trace of the electronic product, there is impedance in the ground loop of the left and right channels of the earphone. This impedance generates a voltage division, which is crosstalk to the other channel and affects the stereo sound effect.

[0051] The reasons for the crosstalk will be briefly described below in combination with the existing earphone circuit.

[0052] As shown in Figure 1 , it is a schematic diagram of the existing earphone circuit. The earphone circuit includes an AP (Application Processor) 11, a codec chip 12, a PCB board 13, an earphone seat 14 and an earphone wire 15. The AP 11 is responsible for audio decoding to obtain digital audio signals; the codec chip 12 is responsible for converting the digital audio signals into analog signals, i.e., digital-to-analog conversion, and the left and right channels have their own PAs (Power Amplifiers) to adjust the power of the analog signals.

[0053] Figure 1 In the formula, R1, R2 are the impedance of two earphone receivers on the earphone wire, R1=R2; Rg1-Rg3 are the wire impedance, in which Rg1 is the impedance of the earphone head ground wire, related to the wire length, Rg2 is the contact impedance between the earphone head and the earphone seat, and Rg3 is the impedance between the earphone seat ground end and the PCB board 13 ground end. Rz is the contact impedance between the earphone seat and the PCB board; JACK_PCB represents the ground end, and ①, ②, ③ represent different nodes respectively.

[0054] The reason for crosstalk is as follows:

[0055] Suppose that only the left channel of the earphone plays audio HPL, and the left channel audio signal HPL is divided by the circuit R2, Rg1, Rg2, Rg3, and the voltage V3 at node ③ is the voltage on the earphone ground wire.

[0056] Since the right channel does not play the audio signal, it can be considered that the amplitude of the right channel audio signal HPR is 0, and the current on the right channel earphone wire is 0, so the voltage V23 between the right channel receiver and the left channel receiver (i.e. between node ② and node ③) is equal to V3. Figure 1

[0057] Therefore, the crosstalk formula of the left channel audio signal to the right channel is as follows:

[0058]

[0059]

[0060] Crosstalk (dB) = 20 x log(Rg1+Rg2+Rg3) - 20 x log(2 x Rg1+Rg2+Rg3+R) (3)

[0061] Since the left and right channels are symmetrical, the crosstalk of the right channel to the left channel is similar to the above.

[0062] As can be seen from the above formula, the size of the crosstalk is related to the impedance Rg1, Rg2, Rg3, and reducing the value of (Rg1+Rg2+Rg3) can reduce the earphone crosstalk, but Rg1 is the impedance on the earphone wire, related to the wire length, and cannot be reduced to 0 ohms. Therefore, even if Rg2, Rg3 are reduced to 0 ohms, the earphone crosstalk cannot be completely eliminated.

[0063] ​In view of the existing problem of poor earphone crosstalk effect caused by reducing the values of impedances Rg1, Rg2 and Rg3 and the hardware cost problem, the embodiment of the present application provides a method and device for reducing earphone crosstalk, a signal processing circuit and a chip, which ensure that the voltages V2 and V3 at both ends of the earphone receiver are equal based on the crosstalk principle through the in-phase gain correction mode in the case of keeping the existing impedances Rg1, Rg2 and Rg3 unchanged, so that the voltage difference V23 at both ends of the earphone receiver is 0V, which is equivalent to compensating for the residual voltage caused by the PCB wiring, mechanical contact impedance and the like, so that the earphone achieves the best stereo effect.

[0064] It should be noted that the scheme provided by the embodiment of the present application is not limited to the earphone form of 3.5mm earphone seat, TypeC seat and the like, and can also be applied to other earphone forms based on the same principle.

[0065] As shown in Figure 2 Fig. 1 is a flowchart of the method for reducing earphone crosstalk provided by the embodiment of the present application, which includes the following steps:

[0066] Step 201: In the case of disconnecting the second channel output end of the codec module and inputting a test audio signal to the first channel of the earphone and inputting a mute signal to the second channel of the earphone, the crosstalk signal of the second channel is collected.

[0067] Specifically, the audio signal of the second channel output end of the codec module is collected, and the audio signal of the connection end is taken as the crosstalk signal of the second channel.

[0068] The test audio signal can adopt a full-amplitude audio signal to reduce measurement error.

[0069] Step 202: The signal adjustment gain is determined according to the crosstalk signal.

[0070] Firstly, the crosstalk signal needs to be converted into a digital signal V_ADC, and then the signal adjustment gain X_Gain is determined according to the digital signal V_ADC. The signal adjustment gain X_Gain can be determined according to the following formula:

[0071] X_GAIN=V_ADC×R_Cali (4)

[0072] Wherein, R_Cali is the corresponding relationship coefficient of the analog signal system (i.e. the codec circuit) and the digital signal system (i.e. the digital signal processing circuit).

[0073] Step 203: Adjust the gain of the first channel audio signal to be decoded and the second channel audio signal to be decoded according to the signal adjustment, and ensure that the phase of the adjusted first channel audio signal to be decoded and the phase of the second channel audio signal to be decoded are the same, and output the adjusted audio signal to be decoded to the encoding and decoding module.

[0074] Assuming the audio signal to be decoded in the first channel is HPL, and the audio signal to be decoded by the second channel codec module is HPR, then the output signal after adjusting the gain according to the signals is as follows:

[0075] The first channel adjusted audio signal output to the encoding / decoding module is: HPR×X_Gain+HPL×(1-X_Gain);

[0076] The adjusted audio signal for the second channel output to the encoding / decoding module is: HPL×X_Gain+HPR×(1-X_Gain).

[0077] Accordingly, embodiments of the present invention also provide a device for reducing headphone crosstalk, such as... Figure 3 The diagram shown is a structural schematic of the device.

[0078] In this embodiment, the device includes the following modules:

[0079] The crosstalk signal acquisition module 301 is used to acquire the crosstalk signal of the second channel when the second channel output of the codec module is disconnected and the test audio signal is input to the first channel of the headphones and the mute signal is input to the second channel.

[0080] Gain determination module 302 is used to adjust the gain based on the crosstalk signal determination signal;

[0081] The signal processing module 303 is used to adjust the gain of the first channel audio signal to be decoded and the second channel audio signal to be decoded according to the signal when the headphones are working, and to ensure that the adjusted first channel audio signal to be decoded and the second channel audio signal to be decoded are in phase, and output the adjusted audio signal to be decoded to the encoding and decoding module.

[0082] Specifically, the crosstalk signal acquisition module 301 may include a switching unit and an acquisition unit. The switching unit is used to disconnect the second channel output terminal of the codec module; the acquisition unit is used to acquire the audio signal at the connection terminal and use the audio signal at the connection terminal as the crosstalk signal of the second channel.

[0083] Specifically, the gain determination module 302 may include an analog-to-digital conversion unit and a calculation unit. The analog-to-digital conversion unit is used to convert the crosstalk signal of the second channel into a digital signal; the calculation unit is used to determine the signal adjustment gain based on the digital signal, and the specific calculation formula can be found in the above formula (4).

[0084] Specifically, the signal processing module 303 is used to adjust the audio signal to be decoded when the headphones are working, input the first channel audio signal to be decoded and the second channel audio signal to be decoded, and output the adjusted audio signal of the first channel: HPR×X_Gain+HPL×(1-X_Gain) and the adjusted audio signal of the second channel: HPL×X_Gain+HPR×(1-X_Gain) to the encoding and decoding module, where HPL is the first channel audio signal to be decoded, HPR is the second channel audio signal to be decoded, and X_Gain is the signal adjustment gain.

[0085] Accordingly, embodiments of the present invention also provide a signal processing circuit for processing audio signals from dual-channel headphones, such as... Figure 4 The diagram shown is a schematic of the circuit.

[0086] The signal processing circuit includes: a digital signal processing circuit 401, and / or an encoding / decoding circuit 402;

[0087] The encoding / decoding circuit 402 includes a first channel encoding / decoding unit 421, a second channel encoding / decoding unit 422, a sampling signal conversion unit 423, and a switching switch SW disposed at the output terminal of the second channel encoding / decoding unit 422 and the headphone jack connection terminal. The switching switch SW includes a fixed terminal S0 and two switching terminals. The fixed terminal S0 is connected to the second channel output terminal of the encoding / decoding circuit, the first switching terminal S1 is connected to the output terminal of the second channel encoding / decoding unit 422, and the second switching terminal S2 is connected to the input terminal of the sampling signal conversion unit 423.

[0088] The digital signal processing circuit 401 includes a first processing unit 411, a second processing unit 412, and a crosstalk calibration unit 413; the first processing unit 411 inputs a first channel audio signal to be decoded and outputs a first calibration signal to the first channel encoding / decoding unit; the second processing unit inputs a second channel audio signal to be decoded and outputs a second calibration signal to the second channel encoding / decoding unit.

[0089] When the crosstalk calibration is performed, the second switching end S2 of the switch SW is connected with the fixed end S0, the first channel audio signal to be decoded input by the first processing unit 411 is a test audio signal, and the second channel audio signal to be decoded input by the second processing unit 412 is a mute signal; the sampling signal conversion unit 423 collects the crosstalk signal of the second channel, converts the crosstalk signal into a digital signal, and inputs the digital signal to the crosstalk calibration unit 413; the crosstalk calibration unit 413 determines the signal adjustment gain according to the crosstalk signal.

[0090] After the crosstalk calibration is completed, the first switching end S1 of the switch SW is connected with the fixed end S0. That is, the connection structure in the normal working state of the earphone is switched. Correspondingly, when the earphone works, the first processing unit 411 and the second processing unit 412 respectively adjust the first channel audio signal to be decoded and the second channel audio signal to be decoded according to the signal adjustment gain, and ensure that the adjusted first channel audio signal to be decoded and the second channel audio signal to be decoded are of the same phase, and output the adjusted audio signal to be decoded to the codec circuit, which is specifically as follows:

[0091] The first channel adjusted audio signal output by the first processing unit to the first channel codec unit is HPR*X_Gain+HPL*(1-X_Gain).

[0092] The second channel adjusted audio signal output by the second processing unit to the second channel codec unit is HPL*X_Gain+HPR*(1-X_Gain).

[0093] Wherein, HPL is the first channel audio signal to be decoded, HPR is the second channel audio signal to be decoded, and X_Gain is the signal adjustment gain.

[0094] The adjustment of the first processing unit to the audio signal to be decoded includes two parts: the adjustment of the audio signal of the current channel, that is, HPL*(1-X_Gain), and the correction of the crosstalk signal generated by the other channel, that is, HPR*X_Gain. Wherein, the adjustment of the audio signal of the current channel is to avoid the full amplitude clipping distortion after the current channel signal is directly added with the crosstalk signal, that is, HPR*X_GAIN+HPL.

[0095] It should be noted that the first channel in the above-mentioned embodiments can be a left channel or a right channel, and correspondingly, the second channel is a right channel or a left channel, which is not limited by the embodiments of the present application.

[0096] In order to further better understand the scheme of the present application, Figure 5The application embodiment signal processing circuit is shown in the application diagram of earphone circuit.

[0097] Figure 5 In the shown example, the sampling signal conversion unit 423 is an ADC (analog-digital converter), and the calibration logic for the audio signal to be decoded is shown in the digital signal processing circuit 401. Figure 5 The AP 11 and the PCB 13 in the shown example are the same as the corresponding modules in the prior art, and will not be described here. Figure 1 The structure of the corresponding modules in the shown prior art is the same, and will not be described here.

[0098] The working process of the signal processing circuit provided by the application embodiment will be described in detail below. Figure 5 The working process of the signal processing circuit provided by the application embodiment will be described in detail below.

[0099] Referring to Figure 5 When the crosstalk calibration is performed, the crosstalk test sound source (i.e. the full-amplitude audio signal left channel full-amplitude audio signal, and the right channel mute signal) is played, and the switch SW is switched to the second switch end SW_2.

[0100] At this time, the voltage of the earphone line ground point, i.e. node ③, is:

[0101] V3=V1×(Rg1+Rg2+Rg3) / (R+Rg1+Rg2+Rg3);

[0102] The voltage of the ground point of the PCB 13, i.e. node ④, is:

[0103] V4=V1×Rg3 / (R+Rg1+Rg2+Rg3);

[0104] Because the right channel path is open, the voltage of the switch node Vsw_2=V2=V3.

[0105] The sampling signal conversion unit 423 in the codec circuit 402 converts the voltage Vsw_2 into a digital value V_ADC; and the crosstalk calibration unit 413 in the digital signal processing circuit 401 determines the value of the signal adjustment gain X_Gain according to the calibration coefficient R_Cali. The calibration coefficient R_Cali is the corresponding coefficient of the analog signal and the digital signal.

[0106] After the above calibration process is completed, the switch SW is switched back from the second switch end SW_2 to the first switch end SW_1.

[0107] The voltages V2, V3 and V3 are determined by the impedances Rg1, Rg2 and Rg3, and the three values can be different in different projects, but the three values are fixed values in the same project. Therefore, in practical application, the calibration process only needs to be run once, and can be placed in the production line engineering. Moreover, in practical application, the calibration process can be automatically completed, or the instrument connected with V34 can be used to manually calibrate the calibration coefficient R_Cali or the signal adjustment gain X_Gain, and the embodiments of the present application are not limited in this regard.

[0108] With reference to the accompanying drawings Figure 5 The different nodes of the calibration logic for the to-be-decoded audio signal are marked as a to l for convenience of description, and the corresponding calibration logic is as follows:

[0109] The voltage of the node j is Vj=HPL*X_Gain, the voltage of the node g is Vg=HPR*(1-X_Gain), and the voltage of the to-be-decoded audio signal finally output by the right channel is Vh=Vj+Vg=HPL*X_Gain+HPR*(1-X_Gain).

[0110] The voltage of the node l is Vl=HPR*X_Gain, the voltage of the node c is Vc=HPL*(1-X_Gain), and the voltage of the to-be-decoded audio signal finally output by the left channel is Vh=Vj+Vg=HPL*X_Gain+HPR*(1-X_Gain).

[0111] It should be noted that the signal adjustment gain X_Gain only changes the signal amplitude and cannot change the signal phase, so as to ensure that the phases of the to-be-decoded audio signals processed by the two channels are the same. In addition, the signal of the current channel is subjected to corresponding attenuation processing, thereby effectively avoiding the saturation distortion after mixing. Through the compensation and calibration of the to-be-decoded audio signal, the signal distortion after mixing of the left and right channels is avoided, and the stereo effect of the earphone is improved.

[0112] The scheme of the present application compensates the crosstalk caused by different channel signals of the earphone through the in-phase gain correction mode, effectively improves the anti-crosstalk performance of the earphone, and saves the hardware cost.

[0113] As to each device, product or apparatus described in the embodiments, it can be a product independent of other apparatuses, or a component of another apparatus. By means of example, such component can be a module of another apparatus. By means of example, such device, product or apparatus can be implemented as a chip, which can be a component of another apparatus. By means of example, such chip can be implemented as a module of another apparatus, and the module can be a component of another apparatus. There can be many devices, products, or apparatuses that can represent the various devices, products, or apparatuses described in the embodiments. The whole, or part of the devices, products, or apparatuses can be implemented as a chip. When the whole, or part of the devices, products, or apparatuses are implemented as a chip, the chip can include a processor. The processor can be a component of a computer, and the whole, or part of the computer can also be a chip. The computer can be used in an operating system, and the whole, or part of the operating system can also be a chip.

[0114] The embodiments of the present application further disclose a storage medium, which is a computer readable storage medium, and has a computer program stored thereon. The computer program can execute all or part of the steps of the method shown in the embodiments of the present application when the computer program runs. Figure 1 The storage medium can include a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, etc. The storage medium can also include a non-volatile memory or a non-transitory memory, etc.

[0115] The embodiments of the present application further provide a terminal device, which includes a memory and a processor. The memory has a computer program stored thereon, and the computer program can run on the processor. The processor executes all or part of the steps of the method shown in the embodiments of the present application when the computer program runs. Figure 1 The storage medium can include a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, etc. The storage medium can also include a non-volatile memory or a non-transitory memory, etc.

[0116] It should be noted that “multiple” appearing in the embodiments of the present application means two or two more.

[0117] The first, second, and the like in the embodiments of the present application are only for illustration and distinction of the described objects, and do not have an order, nor represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0118] The above embodiments can be implemented, wholly or partially, by software, hardware, firmware, or any other combination. When implemented by software, the above embodiments can be implemented, wholly or partially, in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server, or data center to another via wired or wireless means.

[0119] It should be understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0120] In several embodiments provided by the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are only illustrative; for example, the division of the units is only a logical function division, and actual implementation can have another division manner; for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0121] The units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0122] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically included separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0123] The integrated unit realized in the form of software functional unit can be stored in a computer readable storage medium. The software functional unit stored in a storage medium includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute part of the steps of the method described in each embodiment of the present application.

[0124] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of reducing crosstalk in a headphone, the method comprising: The method comprises: In the case of disconnecting the second channel output end of the codec module, and inputting a test audio signal into the first channel of the earphone and a mute signal into the second channel, collecting a crosstalk signal of the second channel; Determining a signal adjustment gain according to the crosstalk signal; In the case of earphone working, adjusting the first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal according to the signal adjustment gain, and ensuring that the adjusted first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal are in the same phase, so as to equalize the voltages at both ends of the earphone earpiece through the in-phase gain correction mode; and outputting the adjusted to-be-decoded audio signal to the codec module.

2. The method of claim 1, wherein, The collecting of the crosstalk signal of the second channel comprises: Collecting an audio signal at the second channel output end of the codec module, and taking the collected audio signal as the crosstalk signal of the second channel.

3. The method of claim 2, wherein, The determining of the gain of the to-be-decoded audio signal according to the crosstalk signal comprises: Converting the crosstalk signal into a digital signal; Determining the signal adjustment gain according to the digital signal.

4. The method of claim 3, wherein, The determining of the signal adjustment gain according to the crosstalk signal comprises: Determining the signal adjustment gain according to the following formula: X_GAIN=V_ADC×R_Cali; Wherein, X_GAIN is the signal adjustment gain, R_Cali is a calibration coefficient, and V_ADC is the digital signal.

5. The method of claim 3, wherein, The adjusting of the first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal according to the signal adjustment gain, and the outputting of the adjusted to-be-decoded audio signal to the codec module comprise: The adjusted audio signal output to the codec module in the first channel is: HPR×X_Gain+HPL×(1-X_Gain); The adjusted to-be-decoded audio signal output to the codec module in the second channel is: HPL×X_Gain+HPR×(1-X_Gain); Wherein, HPL is the first channel to-be-decoded audio signal, HPR is the second channel to-be-decoded audio signal, and X_Gain is the signal adjustment gain.

6. An apparatus for reducing crosstalk in a headphone, the apparatus comprising: The device comprises: A crosstalk signal collecting module, configured to collect a crosstalk signal of the second channel in the case of disconnecting the second channel output end of the codec module, and inputting a test audio signal into the first channel of the earphone and a mute signal into the second channel; A gain determining module, configured to determine a signal adjustment gain according to the crosstalk signal; A signal processing module, configured to, in the case of earphone working, adjust the first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal according to the signal adjustment gain, and ensure that the adjusted first channel to-be-decoded audio signal and the second channel to-be-decoded audio signal are in the same phase, so as to equalize the voltages at both ends of the earphone earpiece through the in-phase gain correction mode; and output the adjusted to-be-decoded audio signal to the codec module.

7. The apparatus of claim 6, wherein, The crosstalk signal collecting module comprises: A switch unit, configured to disconnect the second channel output end of the codec module; A collecting unit, configured to collect an audio signal at the second channel output end of the codec module, and take the collected audio signal as the crosstalk signal of the second channel.

8. The apparatus of claim 7, wherein, The gain determining module comprises: an analog-to-digital conversion unit configured to convert the crosstalk signal of the second sound channel into a digital signal; a calculation unit configured to determine the signal adjustment gain according to the digital signal.

9. The apparatus of claim 8, wherein the signal processing module is specifically configured to, when the earphone is in operation, input first sound channel to-be-decoded audio signals and second sound channel to-be-decoded audio signals, adjust the to-be-decoded audio signals, and output first sound channel adjusted audio signals: HPR×X_Gain+HPL×(1-X_Gain) and second sound channel adjusted audio signals: HPL×X_Gain+HPR×(1-X_Gain) to the codec module, where HPL is the first sound channel to-be-decoded adjusted audio signal, HPR is the second sound channel to-be-decoded audio signal, and X_Gain is the signal adjustment gain.

10. A signal processing circuit for processing a binaural headphone audio signal, characterized by the circuit comprises a digital signal processing circuit and / or a codec circuit; the codec circuit comprises a first sound channel codec unit, a second sound channel codec unit, a sampling signal conversion unit, and a switch connected between the output end of the second sound channel codec unit and the earphone seat connection end, the switch comprising a fixed end and two switch ends, the fixed end being connected to the second sound channel output end of the codec circuit, the first switch end being connected to the output end of the second sound channel codec unit, and the second switch end being connected to the input end of the sampling signal conversion unit; the digital signal processing circuit comprises a first processing unit, a second processing unit, and a crosstalk calibration unit, the first processing unit inputting first sound channel to-be-decoded audio signals and outputting first calibration signals to the first sound channel codec unit, and the second processing unit inputting second sound channel to-be-decoded audio signals and outputting second calibration signals to the second sound channel codec unit; when crosstalk calibration is performed, the second switch end of the switch is connected to the fixed end, the first sound channel to-be-decoded audio signals input by the first processing unit are test audio signals, the second sound channel to-be-decoded audio signals input by the second processing unit are mute signals, the sampling signal conversion unit collects crosstalk signals of the second sound channel, converts the crosstalk signals into digital signals, and inputs the digital signals to the crosstalk calibration unit, and the crosstalk calibration unit determines the signal adjustment gain according to the crosstalk signals; after crosstalk calibration is completed, the first switch end of the switch is connected to the fixed end, and when the earphone is in operation, the first processing unit and the second processing unit respectively adjust first sound channel to-be-decoded audio signals and second sound channel to-be-decoded audio signals according to the signal adjustment gain, and ensure that the adjusted first sound channel to-be-decoded audio signals and the second sound channel to-be-decoded audio signals are in the same phase, so as to make the voltages at both ends of the earphone earpiece equal through the in-phase gain correction mode, and output the adjusted to-be-decoded audio signals to the codec circuit.

11. The signal processing circuit of claim 10, wherein The first processing unit outputs a first calibration signal to the first sound channel codec unit as HPR*X_Gain+HPL*(1-X_Gain); The second processing unit outputs a second calibration signal to the second sound channel codec unit as HPL*X_Gain+HPR*(1-X_Gain); Wherein, HPL is the first sound channel to-be-decoded audio signal, HPR is the second sound channel to-be-decoded audio signal, and X_Gain is the signal adjustment gain.

12. A signal processing chip, characterized by The signal processing circuit according to claim 10 or 11.

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