Method for using nand flash sram in solid state drive controller
By using on-chip SRAM to manage the striping storage and garbage collection of NAND flash memory devices in SSDs, the problems of invalid data blocks and SRAM storage limitations are solved, writing efficiency and concurrency capabilities are improved, and SSD performance is optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2020-05-27
- Publication Date
- 2026-07-24
AI Technical Summary
In existing solid-state drives (SSDs), data blocks may become invalid and unusable during the data writing process until they are erased, resulting in inefficiency. Furthermore, during garbage collection, the SRAM storage space limits the number of concurrent write operations.
By employing NAND flash memory devices with on-chip static random access memory (SRAM), the storage of data blocks is managed by creating stripes, limiting the amount of SRAM storage in each NAND flash memory device, and programming the data block into the NAND flash memory when the limit is reached, thus achieving efficient management and garbage collection of data blocks.
It improves the efficiency of data write operations, reduces write latency, enhances the concurrent write capability of SSDs, optimizes the garbage collection process, and improves the overall performance of SSDs.
Smart Images
Figure CN115698961B_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to PCT patent application No. PCT / US2020 / 034644, filed on May 27, 2020, entitled “METHOD FOR USING NAND FLASH MEMORY SRAM IN SOLID STATE DRIVE CONTROLLER”, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This invention generally relates to solid-state drive (SSD) controllers, and more particularly to a method of using Not-AND (NAND) flash static random access memory (SRAM) in an SSD controller. Background Technology
[0004] SSDs store data in solid-state devices, rather than in magnetic or optical media. A typical SSD consists of a controller and a solid-state storage device. The host device performs read and write operations on the SSD. In response, the SSD acknowledges receipt of data, stores the data, and then retrieves the data. During use, data blocks previously written to the solid-state storage device may become invalid and unusable until they are erased. In a process called "garbage collection," blocks that are still valid are collected from the first solid-state device, aggregated, and rewritten to other solid-state devices. The first solid-state device is then partially or entirely erased and reused for writing data. Summary of the Invention
[0005] The first aspect relates to a write operation method implemented by an SSD controller having a plurality of not-AND (NAND) flash memory devices, the plurality of NAND flash memory devices having on-chip static random access memory (SRAM) and NAND flash memory. The method includes receiving data blocks from a stream comprising a plurality of data blocks; determining whether a stripe has been created for the stream; and creating the stripe for the stream based on the determination that the stripe has not yet been created for the stream, the stripe being created by the following steps: allocating a first subset of the plurality of NAND flash memory devices to the stripe; setting a limit on the number of the plurality of data blocks that can be stored for the stripe in the on-chip SRAM of each of the plurality of NAND flash memory devices in the first subset; storing the data blocks for the stripe in the on-chip SRAM of one of the NAND flash memory devices in the first subset; and instructing the one NAND flash memory device to program each data block stored for the stripe in the on-chip SRAM of the one NAND flash memory device into the NAND flash memory of the one NAND flash memory device when storing the data blocks in the on-chip SRAM of the one NAND flash memory device results in the limit being reached.
[0006] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the method further includes: when all NAND flash memory devices in the first subset successfully program the data blocks in the on-chip SRAM of the NAND flash memory devices in the first subset into the NAND flash memory of the NAND flash memory devices in the first subset, marking each NAND flash memory device in the first subset as reusable of the on-chip SRAM of each NAND flash memory device in the first subset.
[0007] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, each data block of the stream is received from a host device, and the method includes: storing the data block in the SRAM of the SSD controller before storing the data block for the stripe in the on-chip SRAM of one of the NAND flash memory devices in the first subset; sending an acknowledgment message to the host device; and marking the SRAM of the SSD controller storing the data block as reusable when the data block is successfully stored in the on-chip SRAM of the one of the NAND flash memory devices.
[0008] Alternatively, according to any of the foregoing aspects, in another implementation of said aspect, the SSD controller includes a plurality of channels, each channel being coupled to a second subset of the plurality of NAND flash memory devices, and each NAND flash memory device in the first subset being coupled to a different channel than the other NAND flash memory devices in the first subset.
[0009] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the step of determining whether the stripe has been created for the stream includes: determining that the stripe has not yet been created for the stream when all data blocks of the previously created stripe are stored in the on-chip SRAM of the NAND flash memory device in the first subset.
[0010] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the stream is a first stream, and each received data block of the first stream includes a stream identifier identifying the first stream, further comprising: receiving a second data block from a second stream comprising a second plurality of data blocks, the second data block including a second stream identifier identifying the second stream; determining whether a second stripe has been created for the second stream; and creating a second stripe for the second stream based on the determination that a second stripe has not yet been created for the second stream, the second stripe being created by the following steps: allocating a third subset of the plurality of NAND flash memory devices to the second stripe, and storing the second plurality of data blocks for the second stripe in the on-chip SRAM of each of the NAND flash memory devices in the third subset. A second limit is set on the number of data blocks; the second data block is stored for the second stripe in the on-chip SRAM of one of the NAND flash memory devices in the third subset; when storing the second data block in the on-chip SRAM of the one NAND flash memory device in the third subset results in the second limit being reached, the one NAND flash memory device in the third subset is instructed to program each data block stored for the second stripe in the on-chip SRAM of the one NAND flash memory device in the third subset into the NAND flash memory of the one NAND flash memory device in the third subset.
[0011] Alternatively, according to any of the foregoing aspects, in another implementation of said aspect, data blocks from the first stream are received, interspersed with data blocks from the second stream.
[0012] Optionally, according to any of the foregoing aspects, another implementation of this aspect further includes: receiving a read request from a host device, the read request specifying a requested data block to be read; determining whether the requested data block is stored in the on-chip SRAM of one or more of the plurality of NAND flash memory devices; based on the determination that the requested data block is stored in the on-chip SRAM of the one or more of the plurality of NAND flash memory devices: reading the requested data block from the on-chip SRAM of the one or more of the plurality of NAND flash memory devices; and sending the requested data block to the host device.
[0013] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the method further includes: storing the requested data block read from the on-chip SRAM of one or more of the plurality of NAND flash memory devices in the SRAM of the SSD controller; and sending the requested data block from the SRAM of the SSD controller to the host device.
[0014] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, it further includes: when a power failure event is detected, causing any of the plurality of NAND flash memory devices having data blocks stored in the on-chip SRAM to program the data blocks into the NAND flash memory of the NAND flash memory device.
[0015] The second aspect relates to a garbage collection method implemented by an SSD controller having a plurality of not-AND (NAND) flash memory devices, the plurality of NAND flash memory devices having on-chip static random access memory (SRAM) and NAND flash memory, the method comprising: selecting a source NAND flash memory device from the plurality of NAND flash memory devices; selecting a destination NAND flash memory device from the plurality of NAND flash memory devices; setting a limit on the number of data blocks that can be written to the destination NAND flash memory device; sending data blocks from the source NAND flash memory device to the destination NAND flash memory device by the following steps: reading the data block from the source NAND flash memory device; storing the data block in the on-chip SRAM of the destination NAND flash memory device; and when storing the data block in the on-chip SRAM of the destination NAND flash memory device results in the limit being reached, causing the destination NAND flash memory device to program the data block in the on-chip SRAM of the destination NAND flash memory device into the NAND flash memory of the destination NAND flash memory device.
[0016] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the SSD includes a flash memory subsystem coupled to the plurality of NAND flash memory devices, the flash memory subsystem including a randomizer and error correction circuitry. The step of reading the data block from the source NAND flash memory device includes: creating an error-corrected data block by correcting the data block; and creating a de-randomized data block by de-randomizing the error-corrected data block. The step of storing the data block in the on-chip SRAM of the destination NAND flash memory device includes: creating a randomized data block by randomizing the de-randomized data block to store the processed data block; and creating the processed data block by adding error correction codes to the randomized data block.
[0017] Optionally, according to any of the foregoing aspects, another implementation of this aspect further includes: decrypting and re-encrypting the data block between the step of reading the data block from the source NAND flash memory device and the step of storing the data block in the on-chip SRAM of the destination NAND flash memory device.
[0018] Alternatively, according to any of the foregoing aspects, in another implementation of said aspect, the SSD controller includes a plurality of channels, each channel being coupled to a subset of the plurality of NAND flash memory devices, and the source NAND flash memory device being coupled to a different channel than the destination NAND flash memory device.
[0019] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the step of selecting a source NAND flash memory device includes selecting a plurality of source NAND flash memory devices; the step of sending the data block from the source NAND flash memory device to the destination NAND flash memory device includes reading subsequent data blocks from a second source NAND flash memory device of the plurality of source NAND flash memory devices when no data block is reserved on a first source NAND flash memory device among the plurality of source NAND flash memory devices.
[0020] Optionally, according to any of the above aspects, in another implementation of this aspect, it further includes: specifying the location of the data block to be read from the source NAND flash memory device in the source NAND flash memory device; and reading the data block from the specified location in the source NAND flash memory device.
[0021] Alternatively, according to any of the foregoing aspects, in another implementation of said aspect, the limitation is set based on the number of data blocks that the destination NAND flash memory device can store.
[0022] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the data block read from the source NAND flash memory device is derandomized using a first randomization key associated with the source NAND flash memory device to generate the derandomized data block; the derandomized data block is randomized using a second randomization key associated with the destination NAND flash memory device to generate the randomized data block.
[0023] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, it further includes: when a power failure event is detected, causing any of the plurality of NAND flash memory devices having data blocks stored in the on-chip SRAM to program the data blocks into the NAND flash memory of the NAND flash memory device.
[0024] The third aspect relates to an SSD controller having a plurality of Not-AND (NAND) flash memory devices, the plurality of NAND flash memory devices having on-chip static random access memory (SRAM) and NAND flash memory, the SSD controller comprising: components for receiving data blocks from a stream comprising a plurality of data blocks; components for receiving data blocks from the stream comprising a plurality of data blocks; components for determining whether a stripe has been created for the stream; and components for creating the stripe for the stream based on the determination that the stripe has not yet been created for the stream, the stripe being created by the steps of: allocating a first subset of the plurality of NAND flash memory devices to the stripe, and setting a limit on the number of the plurality of data blocks that can be stored for the stripe in the on-chip SRAM of each of the plurality of NAND flash memory devices in the first subset. ; a component for storing the data block for the stripe in the on-chip SRAM of one of the NAND flash memory devices in the first subset; a component for instructing the one NAND flash memory device to program each data block stored for the stripe in the on-chip SRAM of the one NAND flash memory device into the NAND flash memory of the one NAND flash memory device when storing the data block in the on-chip SRAM of the one NAND flash memory device results in the limit being reached.
[0025] Optionally, according to any of the foregoing aspects, in another implementation of said aspect, the following are provided: a component for receiving a read request from a host device, the read request specifying a requested data block to be read; a component for determining whether the requested data block is stored in the on-chip SRAM of one or more of the plurality of NAND flash memory devices; and a component for reading the requested data block from the on-chip SRAM of the one or more of the plurality of NAND flash memory devices based on the determination that the requested data block is stored in the on-chip SRAM of the one or more of the plurality of NAND flash memory devices, and sending the requested data block to the host device.
[0026] The fourth aspect relates to an SSD controller having a plurality of Not-AND (NAND) flash memory devices, the plurality of NAND flash memory devices having on-chip static random access memory (SRAM) and NAND flash memory, the SSD controller comprising: means for selecting a source NAND flash memory device from the plurality of NAND flash memory devices and selecting a destination NAND flash memory device from the plurality of NAND flash memory devices; means for setting a limit on the number of data blocks that can be written to the destination NAND flash memory device; means for sending data blocks from the source NAND flash memory device to the destination NAND flash memory device by: reading the data blocks from the source NAND flash memory device and storing the data blocks in the on-chip SRAM of the destination NAND flash memory device; and means for causing the destination NAND flash memory device to program the data blocks in the on-chip SRAM of the destination NAND flash memory device into the NAND flash memory of the destination NAND flash memory device when storing the data blocks in the on-chip SRAM of the destination NAND flash memory device results in the limit being reached.
[0027] For clarity, any of the above implementations can be combined with any other one or more of the above implementations to create new embodiments within the scope of this invention. These embodiments and other features will become clearer from the following detailed description taken in conjunction with the accompanying drawings and claims. Attached Figure Description
[0028] To gain a more complete understanding of the present invention, reference is made to the following brief description in conjunction with the accompanying drawings and specific embodiments, wherein the same reference numerals denote the same parts.
[0029] Figure 1 This is a schematic diagram of a NAND flash SSD.
[0030] Figure 2 yes Figure 1 A schematic diagram of the NAND flash memory device in an SSD.
[0031] Figure 3 yes Figure 1 The data flow diagram of the SSD performing a write operation.
[0032] Figure 4 yes Figure 1 The data flow diagram of the garbage collection process performed by the SSD.
[0033] Figure 5 This is a schematic diagram of a NAND flash memory device for an SSD according to the present invention.
[0034] Figure 6 This is a data flow diagram of the SSD write operation process according to the present invention.
[0035] Figure 7 yes Figure 6 The data flow diagram of the garbage collection (GC) process performed by the SSD.
[0036] Figures 8A to 8D It shows Figure 6 A more detailed view of the write operation process.
[0037] Figures 9A to 9D It shows Figure 7 A more detailed view of the GC process.
[0038] Figure 10 A flowchart of the read operation process according to the present invention is shown.
[0039] Figure 11 This is a schematic diagram of a processor device according to an embodiment of the present invention.
[0040] Figure 12 A means for implementing one or more of the methods described herein is shown.
[0041] Figure 13 A means for implementing one or more of the methods described herein is shown.
[0042] Figure 14 A means for implementing one or more of the methods described herein is shown. Detailed Implementation
[0043] First, it should be understood that although illustrative implementations of one or more embodiments are provided below, the disclosed systems and / or methods can be implemented using any number of techniques, whether currently known or existing. The invention is by no means limited to the illustrative implementations, drawings, and techniques described below, including the exemplary designs and implementations illustrated and described herein, but can be modified within the full scope of the appended claims and their equivalents.
[0044] The newly developed NAND flash memory chip includes SRAM on-chip. Such a chip can be a three-dimensional (3D) NAND chip or a four-dimensional (4D) NAND chip. In this invention, both types will be collectively referred to as "NAND chip with on-chip SRAM". Some of these NAND chips provide 1 megabyte (MB) of on-chip SRAM, while others provide more or less than 1 MB of on-chip SRAM. This invention provides a novel process for performing write operations and garbage collection using the on-chip SRAM of such NAND chips with on-chip SRAM.
[0045] Figure 1 This is a schematic diagram of a NAND flash SSD 100. The SSD 100 includes a main central processing unit (CPU) 102 and a NAND flash interface (NFI) CPU 108. The main CPU 102 includes a front-side CPU 104 and a back-end CPU 106. The front-side CPU 104 implements a processor for handling commands received from the host device 130 via a peripheral component interconnect express (PCIe) bus, a serial attached small computer system interface (SAS SCSI) bus, or other suitable interfaces. The front-side CPU 104 also implements a scheduler for issuing back-end (BE) commands in response to received host commands. The back-end CPU 106 implements back-end firmware (FW), executes the flash translation layer (FTL), performs mapping, and other back-end functions.
[0046] The NFI CPU 108 controls and manages channels 122. Each channel 122 sends data and commands to a subset of the NAND flash memory devices 124 in the NAND flash memory array 150 (see reference). Figure 2(A more detailed description has been provided). In other SSDs, the main CPU 102 and / or NFI CPU 108 can be implemented with other numbers or types of CPUs and / or other functional distributions.
[0047] SSD 100 also includes dynamic random access memory (DRAM) 112, static random access memory (SRAM) 114, hardware (HW) accelerator 116, and other peripherals 118. DRAM 112 is 32 gigabytes (GB) in size, but may be larger or smaller in other SSDs. SRAM 114 is 10 megabytes (MB), but may be larger or smaller in other SSDs.
[0048] HW accelerator 116 includes an exclusive-OR (XOR) engine, a buffer manager, and an HW garbage collection (GC) engine, and may include other HW circuitry designed to independently handle specific, limited functions of the main CPU 102 and NFI CPU 108. Other peripherals 118 may include various circuitry such as serial peripheral interface (SPI) circuitry, general purpose input / output (GPIO) circuitry, inter-integrated circuit (I2C) bus interfaces, universal asynchronous receiver / transmitter (UART) circuitry, and other interface circuitry.
[0049] SSD 100 also includes a flash subsystem 120, which may include low-density parity check (LDPC) or other error correction circuitry, randomizer circuitry, flash signal processing circuitry, and may include other circuitry that provides processing related to writing and reading data to and from NAND flash array 150. The main CPU 102, NFICPU 108, DRAM 112, SRAM 114, HW accelerator 116, other peripherals 118, and flash subsystem 120 include an SSD controller and are communicatively coupled to host device 130 via interconnect network (or bus) 110.
[0050] Figure 2 yes Figure 1This is a schematic diagram of the NAND flash memory array 150 of the SSD 100. Each channel 122 sends data and commands from the flash memory subsystem 120 to a subset of the NAND flash memory chips in the NAND flash memory array 150. Sixteen channels CH0, CH1…CH15 are coupled to subsets 126a, 126b…126p of the NAND flash memory array 150, respectively. Each subset contains 16 NAND flash memory devices 124 (also called logical units, LUNs). Each NAND flash memory device 124 is coupled to one channel 122, and no NAND flash memory device 124 is coupled to more than one channel 122. In other SSDs, fewer or more channels can be used. Similarly, in other SSDs, fewer or more NAND flash memory devices can be provided for each channel.
[0051] Strip 160 includes one NAND flash memory device 124 in each subset 126a, 126b...126p of NAND flash memory array 150. Strip 160 also includes one or more data blocks 162 within each NAND flash memory device 124 of strip 160.
[0052] Figure 3 yes Figure 1 The data flow diagram for the SSD 100 performing the write operation process 300 is as follows: In step 302, the host device 130 sends a stream of data blocks to be written to the NAND flash array 150 to the SSD 100. As blocks in the stream enter the SSD 100, they are temporarily stored in SRAM 114. In some SSDs, the received blocks may also be temporarily stored in DRAM 112, as shown in step 302a. After each block is successfully stored in SRAM 114 or DRAM 112, in step 306, an acknowledgment of the block is sent to the host device 130. After receiving a sufficient number of blocks to form a stripe 160 (see reference...) Figure 2 Following the described steps, in step 304, blocks of strip 160 are written from SRAM 114 to NAND flash array 150 (or from DRAM 112 in step 304a), a process referred to as a "refresh" operation. Strip 160 comprises one or more blocks of NAND flash devices for each of sixteen subsets 126a to 126p of the NAND flash array 150 to be written through each of the sixteen channels 122.
[0053] The host device 130 may have multiple concurrent applications, each writing to and reading its block streams from the SSD 100, requesting multi-streaming functionality from the SSD. Therefore, the block stream received in step 302 may contain blocks from multiple streams, each block including a stream identifier to separate blocks according to the stream. Other reasons for the host to provide similar multi-streaming SSD functionality may include storage of persistent database objects and key:value stores.
[0054] Although the blocks written from host device 130 to SSD 100 are typically smaller compared to the sizes of SRAM 114 and DRAM 112, several factors combined limit the number of individual simultaneous streams that SSD 100 can provide to host device 130. These factors include, but are not limited to, the number of blocks in stripe 160, the time required to write stripe 160 to NAND flash array 150 and receive confirmation that all blocks have been successfully written, and the size of SRAM 114 (and / or DRAM 112).
[0055] Sometimes, host device 130 performs a read operation on SSD 100 to read data written to SSD 100. This read operation can be called an "immediate read" or "read-after-write". If host device 130 performs an immediate read operation before the refresh operation in step 304 is initiated, the main CPU 102 determines that the requested data is still stored in SRAM 114 (or DRAM 112) and sends the stored data to host device 130 to complete the read operation. In this case, the read operation can be completed within tens of microseconds.
[0056] However, if the refresh operation in step 304 has already begun, the requested data is no longer available from SRAM 114 (or DRAM 112), and the read operation cannot be completed after the requested data has been programmed into the NAND flash array 150. In this case, the completion of the read operation may be delayed by 3 to 7 milliseconds.
[0057] Figure 4 yes Figure 1The data flow diagram for the garbage collection (GC) process 400 performed by the SSD 100 is shown below. GC can be initiated by the main CPU 102 and executed by the GC engine in the HW accelerator 116. In step 402, all valid blocks in one or more source NANDs of a subset 126a of the NAND flash array 150 are read through CH0 channel 122 and temporarily stored in SRAM 114. After a sufficient number of valid blocks have been collected, in step 404, these blocks are written to the destination NAND of a subset 126p of the NAND flash array 150 through CH15 channel 122. Although the data flow diagram of the GC process 400 is shown using subsets 126a and 126p, it should be understood that the garbage collection process 400 can be performed using any source NAND and destination NAND of the NAND flash array 150, although typically the source NAND and destination NAND are accessed through different channels in channel 122.
[0058] Although the data flow diagram of GC process 400 only shows a single GC process in progress, in some SSDs, other combinations of channels 122 are used to perform parallel GC processes simultaneously on multiple source NANDs. In some such SSDs, the total number of valid blocks collected in multiple garbage collection processes may be limited by the size of SRAM 114, or DRAM 112 may be required to be used as overflow storage for SRAM 114, where some valid blocks are temporarily stored in step 402a and written to the destination NAND in step 404a.
[0059] Figure 5 The NAND flash memory array 550 of the SSD 500 according to the present invention (in) Figure 6 A schematic diagram (shown in more detail below) is shown. The NAND flash array 550 includes multiple NAND flash devices 523. Each channel 522 transmits data and commands from the flash subsystem 520 to a subset 526a, 526b...526p of NAND flash devices 524 in the NAND flash array 550. Each subset contains 16 NAND flash devices 524 (also referred to as LUNs). Each NAND flash device 524 is coupled to one channel 522, and no NAND flash device 524 is coupled to more than one channel 522. In other SSDs according to the invention, fewer or more channels may be used. Similarly, in other SSDs according to the invention, fewer or more NAND flash devices may be provided for each channel. Each NAND flash device 524 includes on-chip SRAM 528 and flash memory 530.
[0060] In some embodiments, the SRAM 528 is 1MB in size, but in other embodiments it can be larger. In some other embodiments, more than 16 NAND flash memory devices may be included in a subset and / or more than 16 channels and subsets may be coupled to the flash memory subsystem 520.
[0061] Figure 6 This is a data flow diagram of the SSD 500 performing a write operation 600 on data blocks according to the present invention. In step 602, the SSD 500 receives data blocks from the host device 130, comprising multiple data blocks to be written to the NAND flash array 550. Upon receiving each block, the front-end CPU 504 temporarily stores the block in SRAM 514, and after successful storage in SRAM 514, in step 610, the front-end CPU 504 sends an acknowledgment of the block to the host device 130. When in step 604 (in... Figure 8C When the first block in the stream is received (as shown in the diagram), the backend CPU 506 determines that no stripe has been created for the stream, and in response, creates a stripe 560 and allocates stripe NAND flash devices 524 to the stripe 560, assigning a limit on the number of blocks to be written to each allocated stripe NAND flash device 524. The allocated stripe NAND flash devices 524 comprise a subset of the NAND flash devices 524 in the NAND flash array 550. When the first block in a new stripe 560 is received, stripe NAND flash devices 524 are allocated in each channel 522, and the block of the new stripe 560 is stored in the stripe NAND flash device 524.
[0062] Strip 560 includes one NAND flash memory device 524 in each subset 526a, 526b...526p of NAND flash memory array 550. Strip 560 also includes one or more data blocks 562 within the on-chip SRAM 528 of each NAND flash memory device 524 of strip 560.
[0063] In other SSDs according to the invention, the creation of stripes 560 can be performed elsewhere in the main CPU 502. While stripe 560 uses the first NAND flash memory device 524 from each subset 526a, 526b…526p of the NAND flash memory devices 524 in the NAND flash memory array 550, it will be understood that another stripe 560 can use different NAND flash memory devices 524 from different subsets of the subsets 526a, 526b…526p. For example, a second NAND flash memory device 524 from subset 526a, a tenth NAND flash memory device 524 from subset 526b, a sixth NAND flash memory device 524 from subset 526c, etc., can be used.
[0064] After each block in stripe 560 is received and stored in SRAM 514, without waiting for all blocks in stripe 560 to be received, in step 606, the NFI CPU 508 writes the block to the on-chip SRAM 528 in the stripe NAND flash memory device 524 allocated to that block for temporary storage. After each block is written to the on-chip SRAM 528, the storage space of the block in SRAM 514 is released for subsequent use.
[0065] In some embodiments, strip 560 includes 64 blocks, with four blocks written to each SRAM 528 in strip NAND flash memory device 524. In some such embodiments, the first four receive blocks in strip 560 are written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH0, the next four receive blocks are written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH1, and so on, until the last four receive blocks in strip 560 are written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH15. In other such embodiments, a first receive block in strip 560 is written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH0, a second receive block is written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH1, and so on, until the sixteenth receive block is written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH15. Then, the seventeenth receive block in strip 560 is written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH0, the eighteenth receive block is written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH1, and so on, until the sixty-fourth receive block is written to the SRAM 528 of strip NAND flash memory device 524 coupled to channel 522CH15.
[0066] In other embodiments, stripe 560 may include more or fewer than 64 blocks, wherein the blocks are uniformly or non-uniformly distributed among the stripe NAND flash memory devices 524. In the scenario just described, blocks are sequentially written to the on-chip SRAM 528 of the stripe NAND flash memory device 524 coupled to channels 522CH0, CH1, ... CH15. However, it is understood that in other scenarios, blocks may be written to the on-chip SRAM 528 of the stripe NAND flash memory device 524 coupled to channels 522CH0 to CH15 in any order until the entire stripe 560 is written to the on-chip SRAM 528.
[0067] Also in step 606, the NFI CPU 508 determines whether the limit on the number of blocks of on-chip SRAM 528 to be written to the strip NAND flash memory device 524 has been reached. If the limit is reached, the NFI CPU 508 issues a "commit" command to the strip NAND flash memory device 524, causing it to program blocks from its on-chip SRAM 528 into the NAND flash memory 530 of the strip NAND flash memory device 524. When the limit for other strip NAND flash memory devices 524 is reached, a similar single "commit" command is sent individually to each of these other strip NAND flash memory devices 524. Thus, the NAND flash memory 530 of each strip NAND flash memory device 524 receiving blocks of strip 560 is programmed independently and asynchronously from the NAND flash memory 530 of other strip NAND flash memory devices 524. However, to support recovery from write failures in any of the strip NAND flash memory devices 524, blocks in strip 560 are held in their respective on-chip SRAM 528 until all blocks in strip 560 have been successfully programmed into the NAND flash memory 530 of all strip NAND flash memory devices 524 in strip 560. Only then, in step 608, does the back-end CPU 506 send a "release" command to mark all strip NAND flash memory devices 524 in strip 560 as storage space where their blocks in the on-chip SRAM 528 can be reused. If a write failure occurs in any strip NAND flash memory device 524, no "release" command is sent, and data in one or more of the strip NAND flash memory devices 524 can be recovered from the on-chip SRAM 528, reprocessed as needed, and written to the on-chip SRAM 528 of one or more other NAND flash memory devices 524 to be programmed into the NAND flash memory 530 of one or more other flash memory devices 524.
[0068] After the complete strip 560 is written to the NAND flash array 550, another strip is created in step 604 when an additional block from the same stream is received.
[0069] SSD 500 is used to receive blocks from multiple streams simultaneously. As can be seen from the description of the write operation process 600, SSD 500 can receive a greater number of streams from host device 130 simultaneously than SSD 100. This is because the blocks of each stream received by SSD 500 are stored in SRAM 514, and the amount of time required to store them is only the amount of time required to write each block to the on-chip SRAM 528 in the striped NAND flash memory device 524. Then, the storage space in SRAM 514 for the blocks is freed up for reuse. In contrast, in SSD 100, all blocks in a strip must be stored in SRAM 114 before all blocks in the strip are written to NAND flash memory array 150 and their storage space in SRAM 114 is freed up for reuse.
[0070] Although process 600 is described as storing blocks as part of a stream, it is understood that process 600 can also be used to store blocks sent by host device 130 for storage of persistent database objects and / or for key:value storage.
[0071] If host device 130 performs an "immediate read" operation requesting data currently being written to stripe 560, the requested data can be obtained from the on-chip SRAM 528 of the stripe NAND flash memory device 524 associated with stripe 560 during the lengthy process of programming the data block of stripe 560 into the stripe NAND flash memory device 524. That is, throughout the entire write operation 600, by reading the requested data block from one or more on-chip SRAMs 528, storing them in SRAM 514, and sending the requested block to host device 130 to complete the read operation, an "immediate read" operation requesting data blocks currently being written to stripe 560 can be completed within tens of microseconds (as per reference). Figure 10 (Described in more detail). After the programming of the associated strip NAND flash memory device 524 is completed, and the back-end CPU 506 sends a "release" command to release the storage space of strip 560 in on-chip SRAM 528, the requested data for the "read immediately" operation is no longer available in the strip NAND flash memory device 524. Therefore, the write operation process 600 eliminates the long delay that occurs when the "read immediately" operation is completed in the write operation process 300 of SSD 100, which would have occurred if the "read immediately" operation was received after the refresh operation in step 304 began but before the requested data was programmed into NAND flash memory array 150.
[0072] Figure 7 yes Figure 6The SSD 500 executes a garbage collection process 700. The main CPU 502 prepares the parameters for the garbage collection process 700 by selecting one or more NAND flash memory devices 524 (or source NAND) coupled to channel 522CH0 for garbage collection, selecting a NAND flash memory device 524 (or destination NAND) coupled to channel 522CH15 for receiving collected blocks, and setting a limit on the number of data blocks that can be written to the destination NAND flash memory device 524. Then, to perform garbage collection, valid blocks from the selected source NAND flash memory device 524 are read into the circuitry of the flash subsystem 520. In the flash subsystem 520, the blocks are error-corrected by the LDPC circuitry 542, derandomized by the randomizer 540 using the randomization key of its source NAND flash memory device 524, and then rerandomized by the randomizer 540 using the randomization key of the destination NAND flash memory device 524, with error correction codes added by the LDPC circuitry 542. After re-randomization and error correction coding, the block is written to the on-chip SRAM 528 of the destination NAND flash memory device 524 via CH15 channel 522. While the block is being written to the on-chip SRAM 528, the block in the on-chip SRAM 528 can be individually programmed into the NAND flash memory 530 of the destination NAND flash memory device 524, either in groups when restricted to writing blocks to the on-chip SRAM 528, or in a single write operation after all the blocks have been written to the on-chip SRAM 528.
[0073] In some embodiments, between derandomization and rerandomization, the blocks are sent to an encryption / decryption engine in HW accelerator 516, where the blocks are decrypted and reencrypted before being rerandomized by randomizer 540.
[0074] Although process 700 is described as collecting valid blocks from a source NAND flash memory device 524 coupled to channel 522CH0 and writing the processed blocks to a destination NAND flash memory device 524 coupled to channel 522CH15, it should be understood that process 700 can be used to collect valid blocks from a source NAND flash memory device 524 coupled to any channel 522 and write the collected blocks to a destination NAND flash memory device 524 in any other channel 522.
[0075] Figures 8A to 8D It shows Figure 6 A more detailed view of the write operation process 600. Figure 8AAn overview of the write operation process 600 is shown. In step 602, the SSD 500 receives data blocks from a stream from the host device 130, the stream comprising multiple data blocks to be written to the NAND flash array 550. In step 604, the back-end CPU 506 determines that no stripe 560 has been created for the stream (or stripe creation for the stream has been previously completed), and in response, creates a stripe 560 for storing the received data blocks. In step 606, the SSD 500 stores the received data blocks into one of the NAND flash devices 524 allocated to the stripe 560. After the stripe 560 is filled, step 604 is repeated to create additional stripes 560 upon receiving subsequent data blocks from the stream. References are made below respectively. Figure 8B , Figure 8C and Figure 8D Steps 602, 604, and 606 are described in more detail.
[0076] In step 608, after the NFI CPU 508 reports to the back-end CPU 506 that all striped NAND flash devices 524 have successfully programmed their data blocks for stripe 560 into their NAND flash memory 530, the back-end CPU 506 causes all striped NAND flash devices 524 to mark the portion of their on-chip SRAM 528 containing the data blocks for stripe 560 as reusable.
[0077] The data block received in step 602 includes a stream identifier that identifies the stream to which the data block belongs. The SSD 500 can receive data blocks from multiple streams in a staggered manner. If the SSD 500 receives a data block with a stream identifier different from that of previously received data blocks, the SSD 500 creates a new instantiation of write operation procedure 600 for each newly identified stream. Each instantiation creates an independent stripe 560 for its stream and stores the data blocks of its stream into the independent stripe 560. While the above description uses the term "stream identifier" to identify data in a stream, it is understood that the term can also be used to store streams of persistent database objects or key:value databases.
[0078] Figure 8B Step 602, receiving a data block from the stream from host device 130, is shown in more detail. In step 602a, a data block is received from host device 130. In step 602b, front-end CPU 504 temporarily stores the data block in SRAM 514. After front-end CPU 504 determines that the data block has been successfully stored in SRAM 514, in step 610, front-end CPU 504 sends an acknowledgment of the block to host device 130.
[0079] Figure 8CStep 604 of creating stripe 560 is shown in more detail. In step 604a, backend CPU 506 allocates a subset of multiple NAND flash memory devices 524 (or stripe NAND flash memory devices) to which data blocks of stripe 560 will be stored. In some embodiments, backend CPU 506 allocates one stripe NAND flash memory device 524 to stripe 560 from each subset 526a-526p of NAND flash memory devices 524 of NAND flash memory array 550, i.e., one stripe NAND flash memory device 524 per channel 522. In step 604b, backend CPU 506 allocates a limit on the number of data blocks to be stored in each stripe NAND flash memory device 524. In some embodiments, the limit for each stripe NAND flash memory device 524 is four data blocks.
[0080] Figure 8D The step 606 of storing the received data block into one of the NAND flash memory devices 524 allocated to stripe 560 is shown in more detail. In step 606a, the back-end CPU 506 stores the received data block in the on-chip SRAM 528 of the stripe NAND flash memory device 524. In step 606, after the data block is successfully written into the on-chip SRAM 528 of the stripe NAND flash memory device 524, the main CPU 502 releases the portion of SRAM 514 that stores the data block for subsequent reuse.
[0081] In some embodiments, all received data blocks are stored in the on-chip SRAM 528 of the first stripe NAND flash memory device 524 until the device's data block limit is stored. Then, all subsequently received data blocks are stored in the on-chip SRAM 528 of the second stripe NAND flash memory device 524 until the device's data block limit is stored, and so on, until all data blocks of stripe 560 are stored in the on-chip SRAM 528 of all stripe NAND flash memory devices 524. In other embodiments, each received data block is stored in the on-chip SRAM 528 of any stripe NAND flash memory device 524 until all data blocks of stripe 560 are stored in the on-chip SRAM 528 of the stripe NAND flash memory device 524 of stripe 560.
[0082] In step 606b, after the received data block is stored in the on-chip SRAM 528 of the striped NAND flash memory device 524, the back-end CPU 506 determines whether the limit for the data block to be stored in the on-chip SRAM 528 of the striped NAND flash memory device 524 has been reached. If the limit has not been reached, the write operation process 600 ends. If the limit has been reached, in step 606c, the NFI CPU 508 causes the striped NAND flash memory device 524 to program the data block of strip 560 into its NAND flash memory 530.
[0083] Figures 9A to 9D It shows Figure 7 A more detailed view of the GC process 700. In step 702, the backend CPU 506 prepares the garbage collection parameters, such as... Figure 9B The following is described in more detail. In step 704, the garbage collection process is performed according to the parameters prepared in step 702, such as... Figure 9C It is described in more detail in the text.
[0084] Figure 9B Step 702, preparing garbage collection parameters, is shown in more detail. In step 702a, the backend CPU 506 selects at least one source NAND flash memory device 524 (or source NAND) from which valid data blocks are to be read. If a single source NAND flash memory device 524 does not have a sufficient number of valid data blocks for the complete GC process 700, the backend CPU 506 selects additional source NAND flash memory devices 524 from which valid data blocks are to be read until sufficient data blocks for the complete GC process 700 can be read from the selected source NAND flash memory devices 524. For each selected source NAND flash memory device 524, the backend CPU 506 specifies the location of the valid data blocks to be read.
[0085] In step 702b, the backend CPU 506 selects the destination NAND flash memory device 524 (or destination NAND) to which data blocks will be stored. In step 702c, the backend CPU 506 sets a limit on the number of data blocks that can be written to the destination NAND flash memory device 524. In some embodiments, this limit is set to the number of data blocks considered sufficient for a complete GC process 700, as used in step 702a. In other embodiments, the limit is set to a number of blocks based on the number of blocks that the destination NAND flash memory device 524 is capable of storing.
[0086] Figure 9C Step 704 of the garbage collection process is shown in more detail. In step 706, valid data blocks are read from the source NAND flash memory device 524 and written to the on-chip SRAM 528 of the destination NAND flash memory device 524 (as shown in reference). Figure 9D (For a more detailed explanation). In step 708, it is determined whether a limit has been reached on the number of data blocks to be stored in the on-chip SRAM 528 of the destination NAND flash memory device 524. If the limit has not been reached, process 700 returns to step 706 to read and store another data block. If the limit has been reached, in step 710, the NFI CPU 508 causes the destination NAND flash memory device 524 to program the data block in the on-chip SRAM 528 into the NAND flash memory 530.
[0087] Figure 9D Step 706, which involves reading a data block from a selected source NAND flash memory device 524 and writing it to the on-chip SRAM 528 of the selected destination NAND flash memory device 524, is illustrated in more detail. In step 706a, the NFI CPU 508 reads a data block from a specified location in the source NAND flash memory device 524 and corrects the data block using the error correction circuitry of the flash subsystem 520. Then, the NFI CPU 508 derandomizes the data block using the randomizer circuitry of the flash subsystem 520 via a randomization key associated with the source NAND flash memory device 524. In step 706b, the NFI CPU 508 rerandomizes the derandomized and error-corrected data block using the randomization key associated with the selected destination NAND flash memory device 524 via the randomizer circuitry of the flash subsystem 520, adds error correction codes via the LDPC circuitry 542, and writes the resulting data block to the on-chip SRAM 528 of the selected destination NAND flash memory device 524.
[0088] In some embodiments, between steps 706a and 706b, the derandomized and error-corrected blocks are sent to the encryption / decryption engine in the HW accelerator 516, where the blocks are decrypted and re-encrypted before being rerandomized by the randomizer 540.
[0089] Figure 10A flowchart of a read operation process 1000 according to the present invention is shown. In step 1002, SSD 500 receives a read operation request from host device 130. The read operation request specifies a data block to be read and includes a stream identifier for the block. In step 1004, main CPU 502 determines whether the requested data block is part of a stripe 560 currently being written to NAND flash array 550 in the instantiation of write operation process 600 (i.e., whether the requested data block is stored in the on-chip SRAM of one or more stripe NAND flash devices 524). Step 1004 includes determining whether the instantiation of write operation process 600 has reached step 608, wherein a portion of the on-chip SRAM 528 storing the data block of stripe 560 is released and marked for reuse. If it is determined that the data block is not currently being written to in write operation process 600, then in step 1006, main CPU 502 initiates a conventional read operation process to read the requested data block from NAND flash array 550.
[0090] If it is determined in step 1004 that the requested data block is part of stripe 560 currently being written in the instantiation of write operation process 600, then in step 1008, the back-end CPU 506 causes the NFI CPU 508 to read the requested data block from the on-chip SRAM 528 of the stripe NAND flash memory device 524, and then the requested data block is sent to the host device 130. Before sending the requested data block to the host, in step 1008, part or all of the requested data block is temporarily stored in SRAM 514.
[0091] During write operation process 600 or GC process 700, if a power loss event is detected in SSD 500, the power loss protection (PLP) function of SSD 500 causes the main CPU 502 to cause any NAND flash memory device 524 with data blocks temporarily stored in its on-chip SRAM 528 to program the data blocks into its NAND flash memory 530 to prevent data loss. After power is restored to SSD 500, the main CPU 502 causes the stored data blocks to be retrieved by the associated NAND flash memory device 524 into its on-chip SRAM 528 and executes the power loss recovery process to complete any write operation process 600 and / or GC process 700 interrupted by the power loss event.
[0092] Figure 11This is a schematic diagram of a processor device 1100 according to an embodiment of the present invention. The processor device 1100 is suitable for implementing the disclosed embodiments described herein. The processor device 1100 includes a processor, logic unit or other suitable processing circuitry for processing data 1130; a bus transceiver (XCVR) 1140; and a bus port 1150 for communication via… Figure 6 and Figure 7 The interconnect network (or bus) 510 shown transmits and receives data; memory 1260 is used to store data. Processor device 1100 is adapted to implement the functions described herein performed by main CPU 502, front-end CPU 504, back-end CPU 106, or NFI CPU 508.
[0093] Processor 1130 is implemented through hardware and software. Processor 1130 may be implemented as one or more CPU chips, cores (e.g., multi-core processors), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and digital signal processors (DSPs). Processor 1130 communicates with bus transceiver 1140, bus port 1150, and memory 1160. Processor 1130 includes an SSD control module 1170. SSD control module 1170 implements the disclosed embodiments described above. For example, SSD control module 1170 performs one or more steps of write operation process 600 and garbage collection process 700. Therefore, including SSD control module 1170 provides a substantial improvement to the functionality of processor device 1100 and enables transitions of processor device 1100 to different states. Alternatively, SSD control module 1170 is implemented as instructions stored in memory 1160 and executed by processor 1130.
[0094] Memory 1160 can be used as an overflow data storage device to store programs when a program is selected for execution, as well as instructions and data read during program execution. Memory 1160 can be volatile and / or non-volatile, and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and static random-access memory (SRAM).
[0095] Figure 12 The following diagram illustrates one or more methods for implementing the methods described herein (e.g. Figure 8A The write operation process 600) is performed by means of device 1200. Device 1200 includes a component 1202 for receiving data blocks from a host device, as shown in reference 1200. Figure 8B As described; component 1204 for creating stripes in a NAND flash memory device for storing received data blocks, as referenced Figure 8C As described; component 1206 for storing received data blocks into one of the NAND flash memory devices allocated to a stripe, as referenced Figure 8D As described.
[0096] Figure 13 The following diagram illustrates one or more methods for implementing the methods described herein (e.g. Figure 9A The device 1300 is for a waste collection process 700. The device 1300 includes: a component 1302 for preparing waste collection parameters, as shown in reference... Figure 9B As described; component 1304 for performing the garbage collection process according to parameters, as referenced Figure 9C As described.
[0097] Figure 14 The following diagram illustrates one or more methods for implementing the methods described herein (e.g. Figure 10 The apparatus 1400 includes: a component 1402 for receiving a read operation request from a host device; a component 1404 for determining whether a data block specified in the read request is stored in the on-chip SRAM of a NAND flash memory device; and a component 1406 for reading the requested data block from the on-chip SRAM and sending the requested data block to the host device.
[0098] The disclosed embodiments can be systems, apparatuses, methods, and / or computer program products at any possible level of integration technical detail. Computer program products may include computer-readable storage media having computer-readable program instructions that cause a processor to perform aspects of the invention. Computer-readable storage media may be tangible devices capable of retaining and storing instructions for use by an instruction execution device.
[0099] While this invention provides several embodiments, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the invention. These examples are intended to be illustrative rather than restrictive and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated into another system, or some features may be omitted or not implemented.
[0100] Furthermore, without departing from the scope of the invention, the technologies, systems, subsystems, and methods described and illustrated as discrete or separate in the various embodiments can be combined or integrated with other systems, modules, technologies, or methods. Other items shown or discussed as coupled or directly coupled or communicating with each other may also be indirectly coupled or communicating via an interface, device, or intermediate component using electrical, mechanical, or other means. Other examples of variations, substitutions, and modifications can be determined by those skilled in the art and may be exemplified without departing from the spirit and scope disclosed herein.
Claims
1. A write operation method, characterized in that, Implemented by an SSD controller comprising a solid-state drive (SSD) having multiple NAND flash memory devices, wherein the multiple NAND flash memory devices have on-chip static random access memory (SRAM) and NAND flash memory, the method comprising: Receive data blocks from a stream that includes multiple data blocks; Determine whether a stripe has been created for the stream; When it is determined that the stripe has not yet been created for the stream, a first subset of the plurality of NAND flash memory devices is allocated to the stripe; a limit is set on the number of the plurality of data blocks that can be stored for the stripe in the on-chip SRAM of each of the plurality of NAND flash memory devices in the first subset; The data block is stored for the stripe in the on-chip SRAM of one of the NAND flash memory devices in the first subset; When storing the data block in the on-chip SRAM of one of the NAND flash memory devices results in the limit being reached, the one of the NAND flash memory devices is instructed to program each data block stored for the stripe in the on-chip SRAM of the one of the NAND flash memory devices into the NAND flash memory of the one of the NAND flash memory devices.
2. The method according to claim 1, characterized in that, Also includes: When all NAND flash memory devices in the first subset successfully program the data blocks in the on-chip SRAM of the NAND flash memory devices in the first subset into the NAND flash memory of the NAND flash memory devices in the first subset, each NAND flash memory device in the first subset is marked as reusable of the on-chip SRAM of each NAND flash memory device in the first subset.
3. The method according to claim 1 or 2, characterized in that, Each data block in the stream is received from a host device, and the method further includes: storing the data block for the stripe in the on-chip SRAM of one of the NAND flash memory devices in the first subset of the NAND flash memory devices. The data block is stored in the SRAM of the SSD controller; Send an acknowledgment message to the host device; When the data block is successfully stored in the on-chip SRAM of one of the NAND flash memory devices, the SRAM of the SSD controller storing the data block is marked as reusable.
4. The method according to claim 1 or 2, characterized in that, The SSD controller includes multiple channels, each channel being coupled to a second subset of the multiple NAND flash memory devices, and each NAND flash memory device in the first subset being coupled to a different channel than the other NAND flash memory devices in the first subset.
5. The method according to claim 1 or 2, characterized in that, Also includes: The step of determining whether the stripe has been created for the stream includes: determining that the stripe has not yet been created for the stream when all data blocks of a previously created stripe are stored in the on-chip SRAM of the NAND flash memory device in the first subset.
6. The method according to claim 1 or 2, characterized in that, The stream is a first stream, and each data block in the first stream includes a first stream identifier that identifies the first stream. The method further includes: Receive a second data block from a second stream comprising a second plurality of data blocks, the second data block comprising a second stream identifier that identifies the second stream; Determine whether a second stripe has been created for the second stream; When it is determined that the second stripe has not yet been created for the second stream. Assign a third subset of the plurality of NAND flash memory devices to the second stripe; set a second limit on the number of the second plurality of data blocks that can be stored in the on-chip SRAM of each of the plurality of NAND flash memory devices in the third subset for the second stripe; The second data block is stored for the second stripe in the on-chip SRAM of one of the NAND flash memory devices in the third subset; When storing the second data block in the on-chip SRAM of one of the NAND flash memory devices in the third subset results in the second limit being reached, the NAND flash memory device in the third subset is instructed to program each data block stored in the on-chip SRAM of the NAND flash memory device in the third subset for the second stripe into the NAND flash memory of the NAND flash memory device in the third subset.
7. The method according to claim 6, characterized in that, Receive data blocks from the first stream, interspersed with data blocks from the second stream.
8. The method according to claim 1 or 2, characterized in that, Also includes: Receive a read request from the host device, the read request specifying the requested data block to be read; Determine whether the requested data block is stored in the on-chip SRAM of one or more of the plurality of NAND flash memory devices; Based on the determination that the requested data block is stored in the on-chip SRAM of one or more of the plurality of NAND flash memory devices; Read the requested data block from the on-chip SRAM of one or more of the plurality of NAND flash memory devices; Send the requested data block to the host device.
9. The method according to claim 8, characterized in that, Also includes: The requested data block, read from the on-chip SRAM of one or more of the plurality of NAND flash memory devices, is stored in the SRAM of the SSD controller; The requested data block is sent from the SRAM of the SSD controller to the host device.
10. The method according to claim 1 or 2, characterized in that, Also includes: When a power failure event is detected, any of the plurality of NAND flash memory devices having data blocks stored in the on-chip SRAM will program the data blocks into the NAND flash memory of the NAND flash memory device.
11. A garbage collection (GC) method, characterized in that, Implemented by an SSD controller comprising a solid-state drive (SSD) having multiple NAND flash memory devices, wherein the multiple NAND flash memory devices have on-chip static random access memory (SRAM) and NAND flash memory, the method comprising: Select a source NAND flash memory device from the plurality of NAND flash memory devices; Select the destination NAND flash memory device from the plurality of NAND flash memory devices; Set a limit on the number of data blocks that can be written to the destination NAND flash memory device; The data block is sent from the source NAND flash memory device to the destination NAND flash memory device through the following steps: Read the data block from the source NAND flash memory device; The data block is stored in the on-chip SRAM of the destination NAND flash memory device; When storing the data block in the on-chip SRAM of the destination NAND flash memory device results in the limitation being reached, the destination NAND flash memory device programs the data block in the on-chip SRAM of the destination NAND flash memory device into the NAND flash memory of the destination NAND flash memory device.
12. The method according to claim 11, characterized in that, The SSD includes a flash memory subsystem coupled to the plurality of NAND flash memory devices, the flash memory subsystem including a randomizer and error correction circuitry, wherein: The steps of reading the data block from the source NAND flash memory device include: Error-correcting data blocks are created by correcting the errors in the data blocks. A derandomized data block is created by derandomizing the error-correcting data block; The step of storing the data block in the on-chip SRAM of the destination NAND flash memory device includes storing the processed data block by the following steps: Randomized data blocks are created by randomizing the derandomized data blocks; The processed data block is created by adding error correction codes to the randomized data block.
13. The method according to claim 11 or 12, characterized in that, Also includes: The data block is decrypted and re-encrypted between the step of reading the data block from the source NAND flash memory device and the step of storing the data block in the on-chip SRAM of the destination NAND flash memory device.
14. The method according to claim 11 or 12, characterized in that, The SSD controller includes multiple channels, each channel being coupled to a subset of the multiple NAND flash memory devices, and the source NAND flash memory device being coupled to a different channel than the destination NAND flash memory device.
15. The method according to claim 11 or 12, characterized in that: The step of selecting a source NAND flash memory device includes selecting multiple source NAND flash memory devices; The step of sending the data block from the source NAND flash memory device to the destination NAND flash memory device includes reading subsequent data blocks from a second source NAND flash memory device of the plurality of source NAND flash memory devices when no data block is reserved on the first source NAND flash memory device of the plurality of source NAND flash memory devices.
16. The method according to claim 11 or 12, characterized in that, Also includes: Specify the location of the data block to be read from the source NAND flash memory device within the source NAND flash memory device; The data block is read from the specified location in the source NAND flash memory device.
17. The method according to claim 11 or 12, characterized in that, The limitation is set based on the number of data blocks that the destination NAND flash memory device can store.
18. The method according to claim 11 or 12, characterized in that: The data block read from the source NAND flash memory device is derandomized using a first randomization key associated with the source NAND flash memory device to generate the derandomized data block; The derandomized data block is generated by randomizing it using a second randomization key associated with the destination NAND flash memory device.
19. The method according to claim 11 or 12, characterized in that, Also includes: When a power failure event is detected, any of the plurality of NAND flash memory devices having data blocks stored in the on-chip SRAM will program the data blocks into the NAND flash memory of the NAND flash memory device.
20. An SSD controller having multiple Not-AND (NAND) flash memory devices, characterized in that, The plurality of NAND flash memory devices have on-chip static random access memory (SRAM) and NAND flash memory, and the SSD controller includes: A component for receiving data blocks from a stream that includes multiple data blocks; Components used to determine whether a stripe has been created for the flow; A component for creating a strip for a stream based on the determination that the strip has not yet been created for the stream, the strip being created through the following steps: Assign a first subset of the plurality of NAND flash memory devices to the stripe; A limit is set on the number of the plurality of data blocks that can be stored for the stripe in the on-chip SRAM of each of the plurality of NAND flash memory devices in the first subset; Components for storing the data block for the stripe in the on-chip SRAM of one of the NAND flash memory devices in the first subset; A component for instructing the NAND flash memory device to program each data block stored for the stripe in the on-chip SRAM of the NAND flash memory device into the NAND flash memory of the NAND flash memory device when storing the data block in the on-chip SRAM of the NAND flash memory device results in the limit being reached.
21. The SSD controller according to claim 20, characterized in that, Also includes: A component for receiving read requests from a host device, the read request specifying a block of data to be read; Used to determine whether the requested data block is stored in the on-chip SRAM of one or more of the plurality of NAND flash memory devices; A component for reading the requested data block from the on-chip SRAM of one or more of the plurality of NAND flash memory devices and sending the requested data block to the host device, based on the determination that the requested data block is stored in the on-chip SRAM of one or more of the plurality of NAND flash memory devices.
22. An SSD controller having multiple Not-AND (NAND) flash memory devices, characterized in that, The plurality of NAND flash memory devices have on-chip static random access memory (SRAM) and NAND flash memory, and the SSD controller includes: Components for selecting a source NAND flash memory device from the plurality of NAND flash memory devices and selecting a destination NAND flash memory device from the plurality of NAND flash memory devices; A component for setting a limit on the number of data blocks that can be written to the destination NAND flash memory device; Components for sending data blocks from the source NAND flash memory device to the destination NAND flash memory device via the following steps: Read the data block from the source NAND flash memory device; The data block is stored in the on-chip SRAM of the destination NAND flash memory device; Components for causing the destination NAND flash device to program the data block in the on-chip SRAM of the destination NAND flash device into the NAND flash memory of the destination NAND flash device when storing the data block in the on-chip SRAM of the destination NAND flash device results in the limitation being reached.