Semiconductor structure and method for manufacturing the same

Abstract

The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a semiconductor substrate; a first metal layer located on a surface of the semiconductor substrate; a second metal layer located above the surface of the first metal layer; an insulating layer located between the first metal layer and the second metal layer and used to isolate the first metal layer from the second metal layer; a test via that penetrates the insulating layer and connects the first metal layer and the second metal layer via conductive material in the test via; and at least one pair of dummy vias that penetrate the insulating layer and connect either the first metal layer or the second metal layer.

Description

Technical Field

[0001] The embodiments of the present application relate to semiconductor manufacturing technology, and relate to but are not limited to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices such as memory and chips are typically fabricated using a multilayer structure on a semiconductor substrate. Electrical connections between the various layers on the semiconductor substrate surface are achieved through metal wires, which in turn are connected via vias. The resistance of a via is a critical parameter affecting connection performance. Therefore, test keys are often used during the manufacturing process to test the resistance of vias.

[0003] However, the test unit is located outside the device and there are no other graphics around it, which can easily cause the through-hole to deform, making it difficult for the test results to reflect the actual resistance value of the through-hole inside the device. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same in order to solve at least one problem existing in the prior art.

[0005] In a first aspect, the semiconductor structure provided by the embodiments of the present application includes:

[0006] semiconductor substrates;

[0007] A first metal layer is located on the surface of the semiconductor substrate;

[0008] a second metal layer, located above a surface of the first metal layer;

[0009] an insulating layer, located between the first metal layer and the second metal layer, and used to isolate the first metal layer from the second metal layer;

[0010] a test through hole, penetrating the insulating layer and connecting the first metal layer and the second metal layer through a conductive material in the test through hole;

[0011] At least one pair of dummy through holes penetrates the insulating layer and connects any one of the first metal layer and the second metal layer.

[0012] In a second aspect, the present invention provides a method for manufacturing a semiconductor structure, including:

[0013] forming a first metal layer on a surface of the semiconductor substrate;

[0014] forming an insulating layer on the first metal layer;

[0015] forming a test through hole and at least one pair of dummy through holes penetrating the insulating layer;

[0016] Filling the test through hole and the dummy through hole with a conductive material;

[0017] A second metal layer is formed on the insulating layer, the test via and the dummy via, wherein the test via connects the first metal layer and the second metal layer, and the dummy via connects any one of the first metal layer and the second metal layer.

[0018] The semiconductor structure provided in the embodiment of the present application adopts at least one pair of dummy through holes to be set at different positions around the test through hole. On the one hand, it can play a supporting role and reduce the possibility of deformation of the test through hole during the manufacturing process; on the other hand, the dummy through hole can improve the regional exposure energy distribution of the through hole, improve the process window and the morphology of the through hole. At the same time, a single through hole is easily deformed in the subsequent process. After setting at least one pair of dummy through holes, the deformation of the through hole in the subsequent process can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0020] Figure 2 is a schematic diagram of a semiconductor structure having a test through hole;

[0021] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 2 ;

[0022] Figure 4 A schematic diagram of a first metal layer in a semiconductor structure provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of the first metal layer and the locations of test vias and dummy vias in a semiconductor structure provided in an embodiment of the present application;

[0024] Figure 6 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 3 ;

[0026] Figure 8 is a schematic diagram of forming a test through hole in one embodiment;

[0027] Figure 9 is a schematic diagram of forming a semiconductor structure in one embodiment;

[0028] Figure 10 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 4 ;

[0029] Figure 11 A cross-sectional view of the locations of test vias and dummy vias in a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] The present application provides a semiconductor structure, such as Figure 1 As shown, the semiconductor structure 100 includes:

[0033] a semiconductor substrate 110;

[0034] A first metal layer 120 is located on the surface of the semiconductor substrate 110;

[0035] a second metal layer 130 , located above the surface of the first metal layer 120 ;

[0036] an insulating layer 140 , located between the first metal layer 120 and the second metal layer 120 , and used to isolate the first metal layer 120 from the second metal layer 130 ;

[0037] A test through hole 150 , penetrating the insulating layer 140 and connecting the first metal layer 120 and the second metal layer 130 through the conductive material in the test through hole 150 ;

[0038] At least one pair of dummy vias 160 penetrates the insulating layer 140 and connects to either the first metal layer 120 or the second metal layer 130 .

[0039] In the embodiments of the present application, the semiconductor structure may be a test structure located around a semiconductor device for testing, or referred to as a test unit. The semiconductor structure may be formed simultaneously with the semiconductor device during the process of manufacturing various semiconductor devices (such as memory devices and chips) using a wafer. Since the semiconductor structure is separated from the semiconductor device, it does not affect the performance of the semiconductor device.

[0040] The semiconductor structure can be used for testing during the manufacturing process of semiconductor devices, thereby enabling process monitoring of the semiconductor devices. When the semiconductor device is manufactured, the area containing the semiconductor structure can be cut away, leaving only the semiconductor device, which can then be packaged separately. Of course, the semiconductor structure can also be retained and packaged together with the semiconductor device to facilitate product testing.

[0041] The first and second metal layers are formed simultaneously with the different metal layers in the semiconductor device. Both the first and second metal layers may have patterns formed by etching or other methods, such as linear or mesh patterns. The first and second metal layers are isolated from each other by an insulating layer, which may be made of an insulating material such as silicon oxide or silicon nitride.

[0042] The first and second metal layers can be connected to each other through vias, which penetrate the insulating layer. The test vias connect to both the first and second metal layers, allowing them to be electrically connected through the test vias. The dummy vias connect only to either the first or second metal layer, providing support and balancing for stress.

[0043] In the embodiments of the present application, a dummy via is a via having a structure similar to a test via that penetrates the insulating layer. The dummy via may also contain conductive materials such as metal, but it does not have the function of connecting the first metal layer and the second metal layer. In other words, the dummy via can only connect the first metal layer or only connect the second metal layer.

[0044] Dummy vias can be used to support the entire semiconductor structure. For example, the position distribution of dummy vias and test vias can be centrally or axially symmetrical, thereby making the semiconductor structure more stable. Alternatively, dummy vias can be distributed around the test vias to support the test vias and reduce test inaccuracies caused by deformation of the test vias. In addition, dummy vias can improve the regional exposure energy distribution of the vias, improve the process window and the morphology of the vias. At the same time, a single via is prone to deformation in subsequent processes. Providing at least a pair of dummy vias can avoid deformation of the vias in subsequent processes.

[0045] So, compared to Figure 2The semiconductor structure 200 shown has only one test through hole 201. The semiconductor structure in the embodiment of the present application has a more stable structure and is not easily deformed during the manufacturing process, thereby improving the accuracy and efficiency of testing using the semiconductor structure.

[0046] In some embodiments, the first metal layer includes: a plurality of bottom metal lines distributed in parallel along a first direction;

[0047] The second metal layer includes: a plurality of top-layer metal lines distributed in parallel along a second direction; wherein the second direction is perpendicular to the first direction.

[0048] In the embodiment of the present application, the first metal layer can be a linear metal line and can include multiple metal lines distributed side by side. Since the first metal layer is a metal layer close to the substrate surface, these metal lines can be referred to as bottom metal lines. Here, the multiple bottom metal lines can all be distributed in parallel along a first direction. The first direction can be any direction parallel to the substrate surface and can be based on a method that is convenient to implement during actual manufacturing.

[0049] In an embodiment of the present application, the second metal layer can be a plurality of parallel metal lines having a similar structure to the first metal layer. Compared to the first metal layer, the second metal layer is further away from the substrate surface and can therefore be referred to as the top metal line. The plurality of top metal lines are arranged in parallel along a second direction. The second direction can be perpendicular to the first direction, which can provide a more stable structure.

[0050] In some embodiments, the test via is located at an overlapping position of one of the bottom metal lines and one of the top metal lines.

[0051] The metal lines of the first and second metal layers are perpendicular to each other. Therefore, each bottom metal line of the first metal layer and each top metal line of the second metal layer overlap. These overlapping locations lie on the same straight line perpendicular to the substrate surface. Therefore, the test vias can be formed at these overlapping locations, thereby achieving a connection between the first and second metal layers.

[0052] In some embodiments, the bottom metal line connected to the test via has two test ends, and the top metal line connected to the test via has two test ends;

[0053] The test end is used to perform a resistance test on the test through hole by using a Kelvin four-wire detection method.

[0054] Since the test via connects a top metal line and a bottom metal line perpendicular to each other, each of the two metal lines has two test terminals, and a total of four test terminals can be provided.

[0055] The Kelvin four-wire detection method is also known as the four-terminal detection or the four-point probe method. This method can eliminate the impedance of wiring and contact resistance by separating the electrodes for current and voltage, thereby achieving accurate resistance testing. In an embodiment of the present application, the metal wires connected to the at least four through-holes can be used to connect different detection terminals respectively, thereby achieving four-wire detection, which can improve the accuracy of detection compared to the single-point test method.

[0056] In some embodiments, as Figure 3 As shown, the at least one pair of dummy vias 160 includes a pair of dummy vias 160 and the test via 150 connected to the same top metal line 131 .

[0057] When forming the top metal line, if the top metal line deforms, it can easily cause the test via to deform, thereby affecting the test results. In the embodiment of the present application, a dummy via is set at the location of the top metal line connected to the test via to provide support, reduce the probability of top metal line deformation, and thus reduce the possibility of test inaccuracy caused by test via deformation.

[0058] In some embodiments, as Figure 3 As shown, the at least one pair of dummy through holes 160 includes at least two pairs of dummy through holes 160 and the test through holes 150 connected to different top metal lines 131, and the at least one pair of dummy through holes 160 includes at least two pairs of dummy through holes 160 and the test through holes 150 connected to different bottom metal lines 121.

[0059] In an embodiment of the present application, multiple pairs of dummy vias can be arranged around the test via. These include not only dummy vias connected to the same top metal line as the test via, but also multiple pairs of dummy vias connected to different top metal lines and bottom metal lines. In this way, multiple dummy vias can make the semiconductor structure more stable and reduce the impact of deformation. Furthermore, the dummy vias can improve the regional exposure energy distribution of the via, improving the process window and the morphology of the via.

[0060] In some embodiments, as Figure 4 As shown, at least two of the plurality of bottom metal lines 121 include at least two metal line segments 122 spaced apart from each other, and a spacing region 123 is formed between two adjacent metal line segments 122 .

[0061] Considering that the dummy vias only connect to the top metal line or the bottom metal line, a portion of the bottom metal line can be configured as a plurality of spaced metal line segments, with a spacer area between every two adjacent metal line segments.

[0062] These bottom metal lines do not have a connection function and only have the function of simulating the structure in the semiconductor device. Therefore, these bottom metal lines do not need to be connected to test through holes and do not need to have external test terminals.

[0063] It should be noted that the bottom metal line connected to the test through hole does not have this structure, but is a complete metal line with the following structure: Figure 4 The external test terminal 124 is shown. The bottom metal line with the spacer region can be located adjacent to the complete bottom metal line, or at other spaced locations.

[0064] In some embodiments, projections of at least three of the top-level metal lines on the semiconductor substrate are partially located within a projection of the spacer on the semiconductor substrate.

[0065] Therefore, at least three top metal lines cannot communicate with these bottom metal lines through the through holes when they are at the overlapping position. In other words, the bottom metal line composed of multiple metal line segments has at least three spacing areas, so that multiple dummy through holes can be easily set.

[0066] In some embodiments, as Figure 5 As shown, the top end of the dummy via 160 is connected to the top metal line (not shown in the figure), and the bottom end of the dummy via 160 is connected to the spacer 123 .

[0067] Thus, the overlapping position of the top metal line and the bottom metal line is located in the gap between the bottom metal line. One end of the dummy via is connected to the top metal line, and the other end can be connected to the gap, thereby preventing the first metal layer and the second metal layer from conducting.

[0068] In some embodiments, the distribution pattern of the test through holes and the at least one pair of dummy through holes is axially symmetrical or centrally symmetrical.

[0069] The dummy through hole and the test through hole together form a symmetrical structure, which can make the semiconductor structure have a balanced and stable structure, can be used for repeated testing, and is not easy to be damaged.

[0070] In some embodiments, the dummy vias are arranged symmetrically about a centerline of the semiconductor structure. The distances between each dummy via in the first symmetrical distribution and the center of the semiconductor structure may vary. The test via may be located on the aforementioned centerline. If there are multiple test vias, they may also be arranged symmetrically about the aforementioned centerline. The distances between each dummy via and the test via may be the same or different.

[0071] In some embodiments, the test vias and the dummy vias form a first centrosymmetric distribution centered about the center of the semiconductor structure, and the dummy vias in the first centrosymmetric distribution are equidistant from the center of the semiconductor structure. The center of the semiconductor structure is the center of symmetry. If there is only one test via, it can be located at the center of symmetry. If there are multiple test vias, the test vias can be centrosymmetric about the center of symmetry.

[0072] In some embodiments, the dummy through hole is filled with a conductive material.

[0073] In an embodiment of the present application, the dummy via can be manufactured simultaneously with the test via, using the same process flow. Therefore, the dummy via can have a structure identical to that of the test via, i.e., a structure filled with a conductive material. Because the dummy via is located within the spacer region of the underlying metal wire, it does not conduct current to the underlying metal wire. This can, on the one hand, save manufacturing process steps, and on the other hand, improve the regional exposure energy distribution of the via, thereby improving the process window and the via morphology.

[0074] In other embodiments, the dummy through-holes may also be filled with insulating materials, such as organic materials, oxides, etc. This can reduce electrical interference between through-holes.

[0075] The present application also provides a method for manufacturing a semiconductor structure. Figure 6 Shown, including:

[0076] Step S101, forming a first metal layer on the surface of a semiconductor substrate;

[0077] Step S102: covering the first metal layer with an insulating layer;

[0078] Step S103, forming a test through hole and at least one pair of dummy through holes penetrating the insulating layer;

[0079] Step S104: filling the test through hole and the dummy through hole with a conductive material;

[0080] Step S105 , forming a second metal layer on the insulating layer, the test via and the dummy via, wherein the test via connects the first metal layer and the second metal layer, and the dummy via connects either the first metal layer or the second metal layer.

[0081] Since the semiconductor structure can be a test structure located around a semiconductor device for testing, the manufacturing process of the semiconductor structure is performed simultaneously with the manufacturing process of the semiconductor device product. The first metal layer, the second metal layer, and the insulating layer are all formed simultaneously with the corresponding layers in the semiconductor device.

[0082] The above-mentioned test vias and dummy vias are also carried out synchronously with the process of forming vias in the semiconductor device, such as Figure 7 As shown, after forming an insulating layer (not shown in the figure) on the first metal layer 120, test vias 150 and dummy vias 160 are simultaneously formed at multiple target locations, and then subsequent related processes such as the second metal layer 130 are performed. Figure 8 As shown, the method of forming only one through hole 801 on the first metal layer 120 can make the entire structure more stable, improve the regional exposure energy distribution of the through hole, improve the process window and the morphology of the through hole, and at the same time, a single through hole is easy to deform in the subsequent process. After setting at least one pair of dummy through holes, the deformation of the through hole in the subsequent process can be avoided.

[0083] In some embodiments, forming a first metal layer on the surface of the semiconductor substrate includes:

[0084] forming a plurality of bottom metal lines distributed in parallel along a first direction on the surface of the semiconductor substrate;

[0085] The forming of a second metal layer on the insulating layer, the test through hole and the dummy through hole comprises:

[0086] A plurality of top-layer metal lines distributed in parallel along a second direction are formed on the insulating layer, the test vias, and the dummy vias; wherein the second direction is perpendicular to the first direction.

[0087] Here, a metal layer may be formed on the surface of the semiconductor substrate first, and then a plurality of metal lines may be formed by pattern etching.

[0088] After the first metal layer is formed, an insulating material may be deposited thereon to form an insulating layer.

[0089] In some embodiments, at least two of the plurality of underlying metal lines include at least two spaced-apart metal line segments, and a spacer region is formed between two adjacent metal line segments.

[0090] After forming the above-mentioned bottom metal lines, partial areas of some metal lines can be removed by etching to form spacing areas, so that these bottom metal lines form a plurality of spaced metal line segments.

[0091] In some embodiments, a top end of the dummy via is connected to the top metal line, and a bottom end of the dummy via is connected to the spacer.

[0092] In this way, the dummy vias can be formed simultaneously with the test vias, and the top metal lines can be connected to the dummy vias. Since the dummy vias are located within the spacer area when connected to the first metal layer, they will not connect to the bottom metal lines, thus having no testing function and no electrical interference with the test vias. However, they can provide support and stabilize the semiconductor structure.

[0093] In some embodiments, projections of at least three of the top-level metal lines on the semiconductor substrate are partially located within a projection of the spacer on the semiconductor substrate.

[0094] In this way, there is no metal overlap between the top metal lines and the bottom metal lines with the spacer regions, and the dummy vias are connected to the spacer regions, and thus are not connected to the bottom metal lines.

[0095] The present application also provides the following examples:

[0096] For MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, each metal layer in the back-end of line (BEOL) process is connected through vias. Traditional ISO test-keys (Isolation Test-keys) generally test the resistance of a single via.

[0097] like Figure 9 As shown, the via test structure includes a bottom metal line 901, a top metal line 902, and a test via 903 located at the intersection of these two metal lines and connecting them. This structure is susceptible to the effects of surrounding isolation layers, leading to unstable photolithography processes. Furthermore, the absence of other graphic structures surrounding a single test via can easily cause deformation of the test via during subsequent metal layer planarization processes, making testing impossible. Furthermore, the resistance value of a single test via is highly likely to be inaccurate, failing to accurately reflect the actual resistance of the via in the device.

[0098] In the embodiment of this application, Figure 10 As shown, the first metal layer 1010 includes a plurality of bottom metal lines 1011, and the second metal layer 1020 includes a plurality of top metal lines 1021. At the intersection where one of the bottom metal lines intersects with one of the top metal lines, a test via 1030 is provided, connecting the bottom metal line 1011 and the top metal line 1021. In addition, an insulating layer (not shown) is provided between the first metal layer 1010 and the second metal layer 1020.

[0099] The bottom metal line 1011 and the top metal line 1021 respectively connected to the test through hole 1030 are connected through the test pads 1012 and 1022 respectively, so that the test through hole 1030 can be tested for resistance by the Kelvin test method using the test pads 1012 and 1022.

[0100] In addition, in order to stabilize the entire semiconductor structure, a dummy through hole 1040 may be provided. Figure 11 As shown, dummy via 1040 is connected to second metal layer 1020, passes through insulating layer 1050 between first metal layer 1010 and second metal layer 1020, but is not connected to first metal layer 1010. In an embodiment of the present application, the bottom metal line of the first metal layer may have multiple disconnected and distributed metal line segments, and the disconnected segments have spacers. In this way, when the dummy via is connected to the position of the first metal layer, it contacts the spacers but does not contact the metal line, thereby not conducting the first metal layer.

[0101] The dummy through hole 1040 and other through holes can be used to form a stable symmetrical structure to reduce the possibility of deformation of the test through hole. Therefore, the dummy through hole 1040 does not need to be conductive, and the dummy through hole 1040 can be filled with insulating material, such as Figure 11 Of course, in order to simplify the manufacturing process, the dummy vias can be formed simultaneously with the test vias, and the dummy vias are filled with metal material. However, since the dummy vias are not connected to the bottom metal wire of the first metal layer, they will not conduct electricity between the first metal layer and the second metal layer.

[0102] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0103] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0105] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0106] In addition, all functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above-mentioned integrated units can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0107] The above is merely an embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: semiconductor substrates; A first metal layer is located on the surface of the semiconductor substrate; a second metal layer, located above a surface of the first metal layer; an insulating layer, located between the first metal layer and the second metal layer, and used to isolate the first metal layer from the second metal layer; a test through hole, penetrating the insulating layer and connecting the first metal layer and the second metal layer through a conductive material in the test through hole; at least one pair of dummy through holes, penetrating the insulating layer and connecting any one of the first metal layer or the second metal layer; The first metal layer includes: a plurality of bottom metal lines distributed in parallel along a first direction; The second metal layer includes: a plurality of top metal lines distributed in parallel along a second direction; wherein the second direction is perpendicular to the first direction; The at least one pair of dummy vias includes at least two pairs of top-layer metal lines connected to different top-layer metal lines of the dummy vias and the test vias, and the at least one pair of dummy vias includes at least two pairs of bottom-layer metal lines connected to different bottom-layer metal lines of the dummy vias and the test vias; At least two of the plurality of bottom metal lines include at least two spaced-apart metal line segments, with a spacer region being formed between two adjacent metal line segments; The top end of the dummy through hole is connected to the top metal line, and the bottom end of the dummy through hole is connected to the spacer area.

2. The semiconductor structure according to claim 1, wherein: The test via is located at an overlapping position of one of the bottom metal lines and one of the top metal lines.

3. The semiconductor structure according to claim 2, wherein: The bottom metal line connected by the test via has two test ends, and the top metal line connected by the test via has two test ends; The test end is used to perform a resistance test on the test through hole by using a Kelvin four-wire detection method.

4. The semiconductor structure according to claim 2, wherein: The at least one pair of dummy through holes includes a pair of dummy through holes and the test through hole connected to the same top metal line.

5. The semiconductor structure according to claim 1, wherein: Projections of at least three of the top-level metal lines on the semiconductor substrate are located within a projection of the spacer on the semiconductor substrate.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The distribution pattern of the test through holes and the at least one pair of dummy through holes is axially symmetrical or centrally symmetrical.

7. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The dummy through hole is filled with conductive material.

8. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: forming a first metal layer on a surface of the semiconductor substrate; forming an insulating layer on the first metal layer; forming a test through hole and at least one pair of dummy through holes penetrating the insulating layer; Filling the test through hole and the dummy through hole with a conductive material; forming a second metal layer on the insulating layer, the test via, and the dummy via, wherein the test via connects the first metal layer and the second metal layer, and the dummy via connects either the first metal layer or the second metal layer; The step of forming a first metal layer on the surface of the semiconductor substrate comprises: forming a plurality of bottom metal lines distributed in parallel along a first direction on the surface of the semiconductor substrate; The forming of a second metal layer on the insulating layer, the test through hole and the dummy through hole comprises: forming a plurality of top-layer metal lines distributed in parallel along a second direction on the insulating layer, the test vias, and the dummy vias; wherein the second direction is perpendicular to the first direction; At least two of the plurality of bottom metal lines include at least two spaced-apart metal line segments, with a spacer region being formed between two adjacent metal line segments; The top end of the dummy through hole is connected to the top metal line, and the bottom end of the dummy through hole is connected to the spacer area.

9. The method according to claim 8, characterized in that Projections of at least three of the top-level metal lines on the semiconductor substrate are located within a projection of the spacer on the semiconductor substrate.

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