Gate array structure integrated device and method of manufacturing the same

Abstract

This invention discloses an integrated device with a gate array structure and its fabrication method, relating to the field of semiconductor device technology. The device includes: a substrate; a buffer layer located on one side of the substrate; a channel layer located on the side of the buffer layer facing away from the substrate; a barrier layer located on the side of the channel layer facing away from the substrate; a passivation layer located on the side of the barrier layer facing away from the substrate; a first trench penetrating the passivation layer and the barrier layer, and at least a portion of the channel layer, in a direction perpendicular to the substrate; a second trench penetrating the passivation layer and the barrier layer, in a direction perpendicular to the substrate; the second trench being located between the first trenches; a first gate serving as a radio frequency gate, comprising a first branch and a second branch, the first branch being located within the first trench of the channel layer, and the second branch being located within the second trench, the first branch and the second branch forming an array structure; a second gate being a DC gate; the second gate and the first gate being arranged at intervals along a second direction. This application can effectively ensure high signal linearity of the integrated device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an integrated gate array structure device and its fabrication method. Background Technology

[0002] Antennas, as components for receiving and transmitting electromagnetic wave signals, are core accessories for some terminal devices such as mobile phones. Among them, 5G, as a new generation of communication technology, has brought about many technological and standard innovations with the increase in frequency bands, which has increased the difficulty of antenna design and manufacturing, and further driven antennas to develop towards higher complexity and integration.

[0003] In the prior art, as the complexity of the RF front-end switching circuit increases and the area increases, the isolation and insertion loss will deteriorate to some extent; at the same time, the degradation of the channel carrier mobility of the device also deteriorates the linearity of the RF front-end device.

[0004] Therefore, it is urgent to solve the problems of large number of switching power amplifier components, large area, slow switching speed, and deteriorated signal linearity in existing technologies. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an integrated gate array structure device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, this application provides an integrated gate array structure device, comprising:

[0007] Substrate;

[0008] A buffer layer, located on one side of the substrate;

[0009] The channel layer is located on the side of the buffer layer away from the substrate;

[0010] The barrier layer is located on the side of the channel layer away from the substrate;

[0011] The passivation layer is located on the side of the barrier layer that faces away from the substrate;

[0012] The first trench extends through the passivation layer and the barrier layer, as well as at least a portion of the channel layer, in a direction perpendicular to the substrate.

[0013] The second trench penetrates the passivation layer and the barrier layer in a direction perpendicular to the substrate; the second trench is located between the first trenches, and the first trenches and the second trench are connected.

[0014] The first gate is located on the side of the buffer layer away from the substrate and is a radio frequency gate. The first gate includes a first branch and a second branch. The first branch is located in the first trench of the channel layer and the second branch is located in the second trench. The first branch and the second branch form an array structure.

[0015] The second gate is located on the side of the barrier layer away from the substrate, and the second gate is a DC gate; the second gate extends along a first direction, and the second gate and the first gate are spaced apart along a second direction; the second gate includes a third branch and a fourth branch, the third branch is located in a third trench, and the fourth branch covers the third branch; the first direction intersects the second direction.

[0016] Secondly, this application also provides a method for fabricating an integrated gate array structure device, applicable to the integrated gate array structure device provided in this application, the method comprising:

[0017] Provide a substrate;

[0018] A buffer layer, a channel layer, a barrier layer, and a passivation layer are sequentially fabricated on the substrate.

[0019] Trenches are etched on the passivation layer and barrier layer, and source and drain electrodes are fabricated.

[0020] A first trench and a second trench are etched on the passivation layer, and a first branch of the first gate is formed in the first trench, and a second branch of the first gate is formed in the second trench.

[0021] The beneficial effects of this invention are:

[0022] This invention provides an integrated device with a gate array structure and its fabrication method. On one hand, a first gate and a second gate are integrated into the same device, that is, a radio frequency switch and a power amplifier (PA) are integrated onto the same device through a dual-gate structure. The first gate is an RF gate, employing an array structure, and functions as a power amplifier. The second gate is a DC gate, employing a T-type or I-type structure, which includes a gate and a gate cap, and functions as a switch. Integrating the RF switch and power amplifier onto the same device reduces the number of RF front-end devices, reduces chip area, and improves switching speed. Furthermore, compared to a single switching device, the integrated device exhibits superior isolation and other performance characteristics. On the other hand, by setting the RF gate as an array structure, while ensuring good switching and power amplifier characteristics, the sidewall gate's additional gate control effect on the channel carriers can suppress the nonlinear increase in drain current density with the linear increase of gate voltage caused by the degradation of the device channel carrier mobility, thereby improving transconductance linearity. The linearity of the amplifier's frequency parameters is also greatly improved. In addition, because the number of channels in a large-scale antenna is very large, the integrated device with a dual-gate structure can greatly reduce the number of RF front-end devices, effectively reduce the chip area of ​​the RF front-end, and greatly improve the isolation of the RF switches. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a gate array structure integrated device provided in an embodiment of the present invention;

[0024] Figure 2 This is another structural schematic diagram of the integrated gate array structure device provided in the embodiment of the present invention;

[0025] Figure 3 This is another structural schematic diagram of the integrated gate array structure device provided in the embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of signal processing for an integrated gate array structure device provided in an embodiment of the present invention;

[0027] Figure 5 This is a flowchart of a method for fabricating an integrated gate array structure device according to an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of a preparation process provided in an embodiment of the present invention;

[0029] Figure 7 This is another structural schematic diagram of the preparation process provided in the embodiment of the present invention. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0031] In related technologies, massive MIMO antennas utilize a large number of radio frequency (RF) switches. These RF switches control the switching of microwave signal channels within the circuit, playing a crucial role in the RF transceiver front-end. The basic structure of the RF transceiver front-end connects the power amplifier and the low-noise amplifier via RF switches. The performance indicators of the RF switches, such as isolation, insertion loss, and linearity, determine the effectiveness of the received RF signal. The development of RF switches, to a certain extent, reflects the development of RF integrated circuits.

[0032] Based on their working principle, radio frequency (RF) microwave switches can be classified into electromechanical switches and solid-state switches. Electromechanical switches trigger switching performance through mechanical contact. Solid-state switches include two main categories: field-effect transistors (FETs) and PIN diodes. FET switches form a channel, allowing current to flow from the drain to the source, thus creating an on-state. PIN diodes, on the other hand, form a switching state by inserting a high-resistivity dielectric layer between highly doped positive and negative charge materials. In current research, GaN HEMTs are widely used in RF device manufacturing due to their superior performance. In 2007, Mark Yu et al. first reported the development of a high-power single-pole four-throw hybrid switch using AlGaN / GaN heterostructure field-effect transistors on silicon substrates; in 2008, Jim M. Carroll used gallium nitride field-effect transistors for high-power RF switches; in 2018, Corrado Florian described that the performance degradation of RF GaN-on-SiC HEMT switches due to charge trapping was triggered by high voltage in the operating state; in 2019, Sinan Osmanoglu described three different topologies of single-pole double-throw RF switches based on high-power, low-loss, and high-isolation GaN HEMTs in the X-band and compared and analyzed them.

[0033] Typically, RF switches are connected to power amplifiers, and much research has been conducted on power amplifier devices, particularly regarding their linearity. In 2006, Roberto Pena et al. presented an experimental GaN HEMT grown on a sapphire substrate at the International Symposium on Integrated Nonlinear Microwave and Millimeter-Wave Circuits for the design and testing of resistive mixers. They optimized conversion losses by selecting the gate-to-source bias voltage, and using a smaller drain-to-source bias value helped improve linearity. In 2016, Dragan Gecan mentioned at the 24th Telecommunications Forum that using dynamic gate bias operation to design power amplifiers significantly improved the linearity of PA performance. In recent years, researchers in semiconductor devices have conducted extensive studies on the relationship between array structures and linearity, and array structures are widely used in integrated circuit manufacturing. Array field-effect transistors (FETs) have significant advantages over traditional planar transistors. This is because the channels of FETs are mostly lightly doped, avoiding scattering caused by discrete dopant atoms, thus increasing carrier mobility. Furthermore, compared to traditional planar CMOS, FETs can effectively suppress subthreshold current and gate leakage current.

[0034] In view of this, this application provides an integrated device with a gate array structure. Based on gallium nitride high electron mobility field-effect transistor (GaN HEMT), a multifunctional adjustable integrated device is fabricated using a dual-gate structure, and the radio frequency gate is set as an array structure, which significantly optimizes the signal linearity.

[0035] Please see Figures 1-3 , Figure 1 This is a schematic diagram of a gate array integrated device provided in an embodiment of the present invention. Figure 2 This is another structural schematic diagram of the integrated gate array structure device provided in the embodiment of the present invention. Figure 3 This is another schematic diagram of the integrated gate array structure device provided in this embodiment of the invention. The integrated gate array structure device provided in this application includes:

[0036] Substrate;

[0037] A buffer layer, located on one side of the substrate;

[0038] The channel layer is located on the side of the buffer layer away from the substrate;

[0039] The barrier layer is located on the side of the channel layer away from the substrate;

[0040] The passivation layer is located on the side of the barrier layer that faces away from the substrate;

[0041] The first trench extends through the passivation layer and the barrier layer, as well as at least a portion of the channel layer, in a direction perpendicular to the substrate.

[0042] The second trench penetrates the passivation layer and the barrier layer in a direction perpendicular to the substrate; the second trench is located between the first trenches, and the first trenches and the second trench are connected.

[0043] The first gate is located on the side of the buffer layer away from the substrate and is a radio frequency gate. The first gate includes a first branch and a second branch. The first branch is located in the first trench of the channel layer and the second branch is located in the second trench. The first branch and the second branch form an array structure.

[0044] The second gate is located on the side of the barrier layer away from the substrate, and the second gate is a DC gate; the second gate extends along the first direction D1, and the second gate and the first gate are arranged at intervals along the second direction D2; the second gate includes a third branch and a fourth branch, the third branch is located in the third trench, and the fourth branch covers the third branch; the first direction D1 intersects the second direction D2.

[0045] For details, please refer to [link / reference]. Figures 1-3This embodiment provides an integrated gate array structure device, which sequentially comprises a substrate, a buffer layer, a channel layer, a barrier layer, and a passivation layer. A first gate, which is an RF gate, is disposed on the side of the buffer layer away from the substrate. The first gate is partially located in the channel layer and partially located in the barrier layer and passivation layer. The first gate is an array structure, with a first branch and a second branch arranged alternately. The first branch is located in the channel layer, and the second branch is located in the barrier layer and passivation layer. Along the direction perpendicular to the substrate, the first branch and the second branch have no overlapping area. A second gate, which is a DC gate, is disposed on the side of the barrier layer away from the substrate. The first gate and the second gate are arranged alternately. The second gate includes a third branch and a fourth branch. The third branch is located in the third trench, and the fourth branch covers the third branch. The first direction D1 intersects the second direction D2. Optionally, the first direction D1 is perpendicular to the second direction D2. In this embodiment, on the one hand, the first gate and the second gate are integrated into the same device, that is, the radio frequency switch and the power amplifier (PA) are integrated into the same device through a dual-gate structure; the first gate is an RF gate, which adopts an array structure and acts as a power amplifier; the second gate is a DC gate, which adopts a T-type or I-type structure, and its structure includes a gate and a gate cap, which acts as a switch; integrating the RF switch and the power amplifier into the same device can reduce the number of RF front-end devices, reduce the chip area, and improve the switching speed; in addition, compared with a single switching device, the isolation and other performance of the integrated device are also very good. On the other hand, by setting the RF gate as an array structure, while ensuring good switching and power amplifier characteristics, the sidewall gate's additional gate control effect on the channel carriers can suppress the nonlinear increase in drain current density with the linear increase of gate voltage caused by the degradation of the device channel carrier mobility, thereby improving transconductance linearity. The linearity of the amplifier's frequency parameters is also greatly improved. In addition, because the number of channels in a large-scale antenna is very large, the integrated device with a dual-gate structure can greatly reduce the number of RF front-end devices, effectively reduce the chip area of ​​the RF front-end, and greatly improve the isolation of the RF switches.

[0046] In one optional embodiment of this application, when the transmitter is in a blocking state, a large negative voltage Vg2 is applied to the DC gate to deplete the carriers and clamp the channel, preventing the signal in the antenna from passing through the power amplifier, thus achieving a shutdown function. When the transmitter is in a conducting state, the integrated device acts as both a radio frequency switch and a power amplifier. A voltage Vg1 is applied to the radio frequency gate in the integrated device to input the radio frequency signal. The radio frequency gate can control the switching on and off of the circuit on both sides. At the same time, a positive voltage Vg2 is applied to the DC gate to control the opening and closing of the channel. Changing the magnitude of the positive voltage Vg2 of the DC gate controls the degree of channel opening, thereby changing the amplification level and the signal gain. After being amplified by the integrated device, the signal can be directly transmitted to the antenna for transmission.

[0047] It should be noted that, Figure 1 The embodiments shown are only schematic representations of the positional relationships of the film layers in the device and do not represent the actual dimensions. In particular, the dimensions of the first trench and the second trench do not represent the actual dimensions and can be adjusted during the manufacturing process. Figure 2 The embodiment shown is only a schematic diagram illustrating the position of the first gate and does not represent its actual size; Figure 3 The embodiment shown is only a schematic diagram illustrating the position of the first gate and does not represent its actual size.

[0048] It should be noted that, please refer to Figure 4 , Figure 4 This is a schematic diagram of signal processing for an integrated gate array structure device provided in this embodiment of the invention. Using the integrated device provided in this embodiment, an RF switch and a power amplifier are integrated on the same device through a dual-gate structure. A signal is input at the input terminal Pin, which includes only one amplitude. After processing by the integrated device, a signal is output at the output terminal Pout, which includes multiple amplitudes. Thus, using the integrated device provided in this embodiment, gain adjustment can be achieved.

[0049] Please continue reading Figures 1-3 As shown, in an optional embodiment of this application, the first branch and the second branch are arranged alternately along the first direction D1.

[0050] For details, please continue to see Figures 1-3 As shown, in this embodiment, the first branch and the second branch are alternately arranged along the first direction D1 to form the first gate of the array structure, which further forms a power amplifier of a high linearity integrated device. By using the RF gate of the array structure, while ensuring good switching characteristics and power amplifier characteristics, the linearity of the power amplifier frequency parameters is also improved due to the additional gate control effect of the sidewall gate on the carriers in the channel.

[0051] In one alternative embodiment of this application, the orthographic projection of the third branch on the substrate overlaps with the orthographic projection of the fourth branch on the substrate along a direction perpendicular to the substrate.

[0052] Specifically, the second gate provided in this embodiment is an I-type gate, which can effectively reduce the parasitic capacitance of the integrated device and improve the isolation.

[0053] Please continue reading Figures 1-3 As shown, in an optional embodiment of this application, along a direction perpendicular to the substrate, the orthogonal projection of the third branch on the substrate is located at the orthogonal projection of the fourth branch on the substrate.

[0054] For details, please continue to see Figures 1-3 As shown, the second gate provided in this embodiment is a T-type gate. A voltage greater than the threshold voltage is applied to the DC gate. As the applied voltage is different, the band bending of the two-dimensional electron gas layer at the heterojunction interface, that is, at the junction of the barrier layer and the channel layer, is different, the potential well depth changes, and the concentration of the two-dimensional electron gas in the channel changes. The degree of current amplification of the signal from the RF gate through the two-dimensional electron gas layer is also different.

[0055] In one alternative embodiment of this application, the depth of the first trench in the channel layer along the direction perpendicular to the substrate is less than 20 nm.

[0056] Specifically, in this embodiment, the first trench is at least partially located in the channel layer, and the depth of the channel layer is less than 20nm, which can ensure that the array structure of the first gate can achieve good functionality.

[0057] Please continue reading Figures 1-3 As shown, in an optional embodiment of this application, it further includes: a source and a drain, both located on the side of the trench layer away from the substrate, the source and drain being arranged at intervals, and the first gate and the second gate being located between the source and the drain.

[0058] Based on the same inventive concept, please refer to Figure 5 , Figure 5 This is a flowchart illustrating the fabrication of an integrated gate array structure device according to an embodiment of the present invention. This application also provides a method for fabricating an integrated gate array structure device, applicable to the integrated gate array structure device provided in the above embodiments of this application. Embodiments of the integrated device can be referenced above and will not be repeated here. The method includes:

[0059] Provide a substrate;

[0060] A buffer layer, a channel layer, a barrier layer, and a passivation layer are sequentially fabricated on the substrate.

[0061] Trenches are etched on the passivation layer and barrier layer, and source and drain electrodes are fabricated.

[0062] A first trench and a second trench are etched on the passivation layer, and a first branch of the first gate is formed in the first trench, and a second branch of the first gate is formed in the second trench.

[0063] Specifically, Figure 6 This is a schematic diagram of a preparation process provided in an embodiment of the present invention. Figure 7 This is another structural schematic diagram of the preparation process provided in the embodiment of the present invention. Please continue to refer to... Figure 5 As shown, and in combination Figure 6 and Figure 7 As shown, the following steps are used to fabricate the integrated device in this embodiment.

[0064] S101 provides a SiC substrate.

[0065] S102. Sequentially fabricate a buffer layer / GaN channel layer / AlGaN barrier layer on the substrate.

[0066] S103. Source and drain ohmic metals are prepared on the AlGaN barrier layer.

[0067] S104. SiN passivation layer is grown on the AlGaN barrier layer by PECVD.

[0068] S105. Fabrication of the array structure RF gate: Using an EBL electron beam lithography machine, photolithography is performed on the passivation layer SiN portion. Then, using an ICP etching machine, F-based etching is performed on the surface of the passivation layer SiN. (See [link to previous section]) Figure 6 As shown, the etching depth is the thickness of the SiN passivation layer; then, an EBL electron beam lithography machine is used to perform photolithographic exposure on the AlGaN layer; finally, an ICP etching machine is used for Cl-based etching. Please refer to [link to relevant documentation]. Figure 7 As shown, etching is performed to 10nm below the interface between the AlGaN barrier layer and the GaN channel layer heterojunction; then, a stepper lithography machine is used to perform a double-layer photoresist process to etch the gate pattern, and finally, the RF gate metal is evaporated to form the RF gate.

[0069] S106. DC gate fabrication: First, DC gate groove fabrication is performed using a Stepper lithography machine with EPI621 photoresist. Groove etching is then performed, and F-based etching is performed on the passivation layer SiN using an ICP etching device. Next, DC gate cap fabrication is performed using a double-layer photoresist to lithographically create the gate pattern. Finally, DC gate metal is evaporated.

[0070] S107. Perform metal interconnection and air bridge fabrication to form an integrated device with gate array structure.

[0071] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A device with an integrated gate array structure, characterized in that, Gallium nitride high electron mobility field-effect transistors include: Substrate; A buffer layer is located on one side of the substrate; The channel layer is located on the side of the buffer layer opposite to the substrate; A barrier layer is located on the side of the channel layer opposite to the substrate; A passivation layer is located on the side of the barrier layer opposite to the substrate; A first trench extends through the passivation layer and the barrier layer, as well as at least a portion of the channel layer, in a direction perpendicular to the substrate; The second trench extends through the passivation layer and the barrier layer in a direction perpendicular to the substrate; the second trench is located between the first trenches, and the first trenches and the second trench are connected. A first gate is located on the side of the buffer layer opposite to the substrate. The first gate is a radio frequency gate. The first gate includes a first branch and a second branch. The first branch is located in the first trench of the channel layer, and the second branch is located in the second trench. The first branch and the second branch form an array structure. The first gate is a radio frequency gate and adopts an array structure to function as a power amplifier. The second gate is located on the side of the barrier layer away from the substrate, and the second gate is a DC gate; the second gate extends along a first direction, and the second gate and the first gate are spaced apart along a second direction; the second gate includes a third branch and a fourth branch, the third branch is located in a third trench, and the fourth branch covers the third branch; the second gate is a DC gate, adopting a T-type or I-type structure, which includes a gate and a gate cap, and plays a switching role; the first direction intersects the second direction.

2. The integrated gate array structure device according to claim 1, characterized in that, The first branch and the second branch are arranged alternately along the first direction.

3. The integrated gate array structure device according to claim 1, characterized in that, Along a direction perpendicular to the substrate, the orthographic projection of the third branch on the substrate overlaps with the orthographic projection of the fourth branch on the substrate.

4. The integrated gate array structure device according to claim 1, characterized in that, Along a direction perpendicular to the substrate, the orthographic projection of the third branch on the substrate is located at the orthographic projection of the fourth branch on the substrate.

5. The integrated gate array structure device according to claim 1, characterized in that, The first trench located in the channel layer has a depth of less than 20 nm in the direction perpendicular to the substrate.

6. The integrated gate array structure device according to claim 1, characterized in that, Also includes: The source and drain are both located on the side of the trench layer away from the substrate. The source and drain are arranged at intervals, and the first gate and the second gate are located between the source and the drain.

7. A method for fabricating a device with an integrated gate array structure, characterized in that, Applied to a gate array structure integrated device as claimed in any one of claims 1-6, the method comprises: Provide one of the aforementioned substrates; The buffer layer, the channel layer, the barrier layer, and the passivation layer are sequentially fabricated on the substrate. Trenches are etched on the passivation layer and the barrier layer to fabricate the source and drain electrodes; The first trench and the second trench are etched on the passivation layer, and the first branch of the first gate is formed in the first trench, and the second branch of the first gate is formed in the second trench.

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