Micro-scale two-dimensional array integrated temperature measurement method based on MEMS process

Abstract

The application discloses a microscale two-dimensional array integrated temperature measurement method based on a MEMS process, and comprises the following steps: S1, integrating a two-dimensional temperature measurement thermistor network in a microfluidic device; S2, establishing a mathematical relationship model of data points and external end resistance values; and S3, testing the external end resistance values of the resistance network, inversely deriving internal resistance values of the resistance network, and deducing a temperature field distribution in a microchannel of the microfluidic device based on resistance temperature characteristics in the resistance network and the relationship model. The application organically combines a two-dimensional resistance network with microscale temperature measurement, tests external end resistance values of the resistance network, establishes a mathematical model, inversely derives internal resistance values, deduces a two-dimensional temperature field according to resistance temperature characteristics of metal, and innovatively realizes high-precision temperature field acquisition by using a contact type temperature measurement method.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of micro-scale temperature measurement, and particularly relates to a micro-scale two-dimensional array integrated temperature measurement method based on a MEMS process. BACKGROUND

[0002] The latest progress in micro-technology and nanotechnology has produced microfluidic devices involving a large number of micro-channels in order to perform analysis using very small amounts of fluid. In order to further develop devices such as chip laboratories and micro-total analysis systems, it is very important to understand the physical characteristics of multiphase flow, single-phase flow transmission processes in micro-channels. In addition, it is essential to monitor and optimize flow conditions such as fluid / wall temperature, pressure and velocity, which requires integrating detection systems in micro-channels, such as integrating silicon-based temperature sensor arrays for monitoring channel wall boundary conditions into micro-channels. There have been a large number of studies on the hydraulic diameter, width-height ratio, roughness, surface structure and surface modification of micro-channels, but there are certain differences between the results of different scholars, and even self-contradictory, especially in the field of flow heat transfer.

[0003] The main reason for this problem is that micro-scale temperature measurement technology has not become more perfect and accurate with the development of micro-mechanics, and to a large extent, traditional testing methods and testing means are used, such as the thermocouple line temperature measurement scheme of Spizzichino M et al.:

[0004] Spizzichino M, Sinibaldi G, Romano G P. Experimental Investigation on Fluid Mechanics of Micro-Channel Heat Transfer Devices [J]. Experimental Thermal and Fluid Science (EXP THERM FLUID SCI), 2020, 118: 110141.

[0005] A few micro-sensor technologies developed according to micro-electro-mechanical system integration are still in the research stage, and there are still deficiencies in theory and technology. At the same time, the integrated temperature measurement technology currently proposed is still mainly single-point temperature measurement, such as the gold thin film thermal resistance used as an integrated temperature sensor by Zhenlan Xue et al.

[0006] Zhenlan Xue, Huihe Qiu. Integrating micromachined fast response temperature sensor array in a glass microchannel[J]. Sensors and Actuators A, 122, 2005, 189-195.

[0007] However, the process, testing and other problems caused by the increase in the number of sensors limit the number of data points, which is still insufficient compared with the demand for micro-scale advanced temperature measurement technology. Therefore, it is necessary to develop a temperature measurement array technology based on MEMS technology, break through the limitations of traditional technology, realize the integrated design and arrangement of temperature sensors, adopt advanced design concepts and mathematical models, realize the array arrangement of temperature sensors, and form a standardized test method in the field of micro-scale test technology, obtain accurate and unified research conclusions, and produce advanced scientific research results and practical industrial products.

[0008] In the current micro-scale temperature measurement scheme, there are mainly two problems. First, the test precision is insufficient, and the experimental data depends on the traditional temperature measurement method, mainly using the thermocouple or thermal resistance sold in the market, which is directly arranged on the surface of the equipment to be tested. The manual error caused by the arrangement is in the order of millimeters, while the hydraulic diameter of the micro-scale channel is generally in the order of microns. Such test precision is unbearable in micro-scale temperature measurement. Second, the number of data points is insufficient. The current manual arrangement of traditional thermocouples or thin-film thermistors, or the more advanced integrated arrangement of thermocouples and thermistors, is in the range of single-point temperature measurement. For a single experimental piece, the number of data points generally does not exceed ten, and the data obtained is extremely limited. Therefore, it is still far from the goal of completely describing the flow field information in the micro-scale channel. In addition, infrared temperature measurement is a commonly used two-dimensional temperature measurement method, which is also applied in the micro-scale field. However, the size of the pixel is generally in the order of tens of microns, and the material and observation position of the experimental piece need to be strictly limited. The temperature test precision is slightly weaker than that of thermocouples and thermistors. In addition, the high resolution optical device brings high price, which often makes many researchers hesitate. SUMMARY

[0009] The application aims to provide a micro-scale two-dimensional array integrated temperature measurement technology with higher integration and more data points compared with the existing temperature measurement method, so as to realize the two-dimension, integration and standardization of the micro-scale temperature measurement scheme. Relying on the current MEMS processing technology, the temperature measurement thermistor is arranged from the traditional millimeter level to the micron level, the arrangement is more reasonable, and the in-situ measurement of the channel is realized. Relying on the design of the two-dimensional resistance network, the internal resistance is inverted through the external resistance value test of the resistance network, and the corresponding temperature field is derived according to the resistance temperature characteristics of the metal, so as to realize the high-precision integrated test of the micro-scale temperature field and reduce various errors.

[0010] To achieve the above object, the application provides a micro-scale two-dimensional array integrated temperature measurement method based on a MEMS process, which comprises the following steps:

[0011] S1. Integrating a two-dimensional temperature measurement thermistor network in a micro-fluid device based on a MEMS magnetron sputtering process;

[0012] S2. Establishing a mathematical relationship model between data points and external resistance values;

[0013] S3. Testing the external resistance value of the resistance network, inverting the internal resistance value of the resistance network, and deriving the temperature field distribution in the micro-channel of the micro-fluid device based on the resistance temperature characteristics in the resistance network and the relationship model.

[0014] Optionally, the micro-fluid device comprises a glass sheet, an intermediate silicon sheet and a lower silicon sheet.

[0015] In step S1, the step of integrating the two-dimensional temperature measurement thermistor network in the micro-channel device is:

[0016] S11. Processing the glass sheet;

[0017] S12. Processing the intermediate silicon sheet;

[0018] S13. Processing the lower silicon sheet;

[0019] S14. Bonding the glass sheet, the intermediate silicon sheet and the lower silicon sheet in sequence.

[0020] Optionally, the relationship between the data points and the leads is:

[0021]

[0022] Wherein, n is the number of data points, and b is the number of leads.

[0023] Optionally, the number of data points of the two-dimensional temperature measurement resistance network is less than or equal to the number of test data.

[0024] Optionally, the material, size and resistance of each resistor in the resistance network are the same.

[0025] Optionally, each resistor in the resistance network is a thin-film platinum thermal resistor.

[0026] Optionally, in step S2, the mathematical relationship model is:

[0027]

[0028] wherein n is the number of resistance lines between each two mutually connected data points, a1-a n is the resistance value of the resistance line between each two mutually connected data points, b is the number of external test points, is the resistance value between the external test points, is a functional relationship between the resistance values of the external test points and the data points, and the specific functional form is determined according to the form of the resistance network.

[0029] Optionally, in step S3, the specific method of inversion includes two methods: iteration method and Laplace matrix method.

[0030] Optionally, the iteration method is to perform iterative calculation on the original equation set according to the original value, and the specific analytical form is determined according to the resistance network, and the theoretical methods that can be adopted include dichotomy method, simple iteration method, Newton method and secant method, the resistance value of the resistance line between the internal data points is obtained, a linear equation set is established between the resistance value between the internal data points and the temperature, an optimization method is used to solve the linear equation set, and an optimized solution such as least square solution is obtained, that is, the internal temperature field of the resistance network;

[0031] The Laplace matrix method is to first construct a Laplace matrix according to the resistance network, the Laplace matrix represents the relationship between the resistance value of the resistance line between the data points and the external test value, then the generalized inverse of the Laplace matrix is solved, during which an optimization method such as KKT method is used, the resistance value between the internal data points is obtained according to the external test value, a linear equation set is established between the resistance value between the internal data points and the temperature, and finally an optimization method is used to solve the linear equation set again, and an optimized solution such as least square solution is obtained, that is, the internal temperature field of the resistance network.

[0032] The technical effect of the present application is:

[0033] The present application organically combines two-dimensional resistance network and micro-scale temperature measurement, tests the external resistance value of the resistance network, establishes a mathematical model, inverts the internal resistance value, deduces a two-dimensional temperature field according to the resistance-temperature characteristics of the metal, and innovatively realizes the use of contact type temperature measurement method to obtain a high-precision temperature field.

[0034] The application enriches the diversity and controllability of processing methods and practical applications by flexible design of the two-dimensional resistance network, under the premise that the number of data points is less than or equal to the number of test data, and according to different test scenes and process conditions, the two-dimensional resistance network can be designed into any shape and any density.

[0035] The application significantly reduces the number of lead Pads under the same data points by combining the method of lead Pad cross combination test with the design of the two-dimensional resistance network, and performing pairwise permutation and combination test between the lead Pads.

[0036] The application realizes integrated measurement by integrated arrangement of the thin film thermal resistance, and uses the MEMS magnetron sputtering process to arrange the two-dimensional network of the thin film thermal resistance, so as to achieve micron-level arrangement precision and processing precision. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which form a part of this application, are included to provide a further understanding of the application and are incorporated in and constitute a part of this application. The embodiments of the application illustrated in the drawings, and their description, are used to explain the application and are not intended to limit the application. In the drawings:

[0038] Figure 1 A 4*4 rectangular array resistance network scheme diagram is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0039] Figure 2 A 4*4 to m*n rectangular array resistance network schematic diagram is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0040] Figure 3 A schematic diagram is used to illustrate the comparison between the micro-scale two-dimensional array test technology and the traditional test technology in the embodiments of the application;

[0041] Figure 4 A conceptual diagram of the MEMS-based micro-scale two-dimensional array integrated temperature measurement experimental piece is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0042] Figure 5 A process flow diagram of the experimental piece is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0043] Figure 6 A top view of the glass sheet processing technology is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0044] Figure 7 A top view of the intermediate silicon wafer processing technology is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0045] Figure 8 A bottom view of the intermediate silicon wafer processing technology is used to illustrate the micro-scale two-dimensional array test technology in the embodiments of the application;

[0046] Figure 9A top view of a lower silicon wafer processing process in the embodiment of the present application.

[0047] Wherein:

[0048] Figure 6 In the figure, 1 is a micro-channel; 2 is a turbulence column; 3 is a bonding surface; and 4 is a heating film Pad lead hole.

[0049] Figure 7 In the figure, 1 is a micro-channel; 2 is a turbulence column; 3 is a bonding surface; and 4 is a heating film Pad lead hole.

[0050] Figure 8 In the figure, 1 is a two-dimensional array thin film thermal resistance; and 2 is a thin film thermal resistance Pad.

[0051] Figure 9 In the figure, 1 is a heating film; 2 is a heating film Pad; and 3 is a thin film thermal resistance Pad lead hole. DETAILED DESCRIPTION

[0052] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0053] Embodiment one

[0054] As shown in the figure, the present embodiment provides a micro-scale two-dimensional array integrated temperature measurement method based on a MEMS process, which comprises: Figures 1-9 In the integrated process design of the micro-scale thin film thermal resistance, the scheme of the present application adopts a two-dimensional resistance network-based array temperature measurement system to replace the original single-point thermal resistance scheme. The internal resistance value of the resistance network is obtained through the external resistance value test of the resistance network, and then the distribution of the temperature field is derived by using the resistance temperature characteristics of the thin film thermal resistance itself. The two-dimensional resistance network in the scheme of the present application can be of any shape and any density, as long as the number of data points is less than or equal to the number of test data.

[0055] In the test principle of the two-dimensional array integrated temperature measurement system, the scheme of the present application adopts a resistance network in the forefront of academic research to layout the temperature sensor, as shown in the figure. The scheme of the present application is not limited to the number of data points and the shape of the resistance network. For the convenience of understanding, a 4*4 rectangular array resistance network is taken as an example for principle analysis, as shown in the figure.

[0056] Figure 1 Figure 2 ​​The data points are 16 in total for a 4*4 rectangular array resistance network, distributed at the junctions between the resistance lines, and the resistance line between every two data points can be equivalent to a resistance whose resistance value changes with temperature, and the resistance network can lead out 12 pads from the outside, and the connection between every two pads can obtain 66 external test resistance values Ri, and a corresponding mathematical model can be established between the external test resistance values and the 16 temperature data points:

[0057]

[0058] It can be seen that the number of external test resistance values exceeds the number of data points, so the optimal method can be used to fit the equation result to obtain the optimal solution. At the same time, it is proved that the number of lead pads can be reduced, bad points can be excluded, and the fault tolerance rate in the process of manufacturing can be improved. The two-dimensional resistance network is introduced into the temperature measurement system, so that the whole temperature measurement system is optimized from the test principle.

[0059] In the test logic of the two-dimensional array integrated temperature measurement system, the present application adopts a cross test method in which a plurality of lead pads are connected to each other. Compared with the traditional single-point test scheme, the number of lead pads is significantly reduced. In the traditional single-point test scheme, a thin-film thermal resistance is composed of a positive electrode and a negative electrode, and two lead pads are obtained, that is, one data point. Even if the common ground is considered, if a data points need to be measured, the number of effective pads needs to be at least a+1. However, for the two-dimensional array test scheme, any two lead pads are connected to each other, and the corresponding resistance value can be obtained. If a data points need to be measured, only b effective pads are needed, so that the number of dependent variables is greater than the number of independent variables, and the equation has a solution. It can be seen in Figure 3 that the more data points that need to be tested, the more obvious the advantages of the two-dimensional array temperature measurement scheme compared with the traditional test method.

[0060] In the integrated process of the two-dimensional array integrated temperature measurement system, the MEMS integrated temperature measurement technology is adopted, the thin-film thermal resistance is magnetron sputtered on the lower surface of the channel, the layout precision is micron-level, the in-situ measurement with high precision is realized, the ICP plasma etching technology is used to process the micro-channel with complex structure, and the lead points are reserved to realize the integrated temperature measurement system design.

[0061] According to the patent application scheme, a design scheme of a micro-scale two-dimensional array integrated temperature measurement technology based on the MEMS process is proposed, and the corresponding processing schemes are given. In terms of design scheme, the integrated temperature measurement technology is composed of two parts, the first part is the design of the two-dimensional array integrated experimental piece (as shown in Figure 4 , and the second part is the processing based on the MEMS process (as shown in Figure 5 ).

[0062] The design of the experimental piece is mainly rectangular array, a 5*4 rectangular array is designed, there are 8 external lead numbers in total, 28 values can be measured, there are 20 data points in total, the number of test points is greater than the number of data points, the following equation has a solution:

[0063]

[0064] The number of test points is greater than the number of data points, so the least square method in the optimization method is used to fit and analyze the measured data in the post-processing process, so as to obtain the final internal resistance value, and finally the temperature field distribution is derived according to the resistance temperature characteristic of platinum metal.

[0065] The processing design of the experimental piece is completed by bonding three wafers (such as Figure 5 ), the three wafers from top to bottom are glass sheet, middle silicon sheet and lower silicon sheet, the bonding methods are silicon-glass anodic bonding, silicon-silicon auxiliary bonding. The anodic bonding of glass sheet and middle silicon sheet mainly plays the role of sealing microchannels (such as Figure 7 1 and 2), the auxiliary bonding of middle silicon sheet and lower silicon sheet mainly plays the role of integrating the heating film (such as Figure 9 1) of the lower silicon sheet and the microchannels (such as Figure 7 1 and 2) and the thin film resistance (such as Figure 8 1). The main purpose of the glass sheet process is to leave the lead position of the heating film of the lower silicon sheet (such as Figure 6 1), the main purpose of the middle silicon sheet process is to integrate the two-dimensional array thin film resistance network at the bottom (such as Figure 8 1 and 2), and the main purpose of the lower silicon sheet process is to integrate the heating film (such as Figure 9 1) with the same size as the designed heating area, and the process steps are as follows (such as Figure 6 ):

[0066] 1. Glass sheet processing flow

[0067] Step one: clean the glass sheet to remove dust, impurities and organic matter on the surface of the glass sheet, the specific steps are deionized water-alcohol-acetone-alcohol-deionized water, and the glass sheet surface is dried in an oven after cleaning.

[0068] Step two: laser cutting and punching of 4-inch 500μm thick glass sheet, processing the lead through hole (such as Figure 6 1) of the lower silicon sheet.

[0069] Step three: clean the punched glass sheet to remove dust, impurities and organic matter on the surface of the glass sheet, the specific steps are deionized water-alcohol-acetone-alcohol-deionized water, and the surface moisture of the glass sheet is dried in an oven after cleaning.

[0070] 2. Processing flow of intermediate silicon wafer

[0071] Step one: clean the silicon wafer to remove dust, impurities and organic matter on the surface of the silicon wafer, the specific steps are deionized water-alcohol-acetone-alcohol-deionized water, and the surface moisture of the silicon wafer is dried in an oven after cleaning.

[0072] Step two: 4-inch 340-μm-thick double-polished intrinsic silicon wafer with an oxide layer thickness of 2 μm, first spin-coat photoresist S1813, then ultraviolet exposure Figure 7 The structural pattern in the middle is developed with a special developer, and then immersed in a BOE solution, and after a period of time, the oxide layer at the front channel, back via, and alignment mark is selectively removed, and the silicon wafer is cleaned.

[0073] Step three: glue coating and exposure, using photoresist as a mask, after ultraviolet exposure and development, patterned magnetron sputtering Ti adhesion layer with a thickness of 6 nm, patterned magnetron sputtering Pt film with a thickness of 300 nm (as shown in Figure 8 Fig. 1), and patterned magnetron sputtering Au film with a thickness of 300 nm as the lead part of the thin film thermal resistance (as shown in Figure 8 Fig. 2).

[0074] Step four: high-temperature annealing in a low-vacuum or nitrogen environment, with a heating rate of 300°C / h, a temperature of 600°C, a holding time of 4 h, and natural cooling, to make the electrical properties of the thin film more stable and reduce the stress of the thin film through metal recrystallization.

[0075] Step five: complete the etching of the front channel 300 μm (as shown in Figure 7 Figs. 1 and 2), and the post-etching lead via structure (as shown in Figure 7 Fig. 4).

[0076] 3. Processing flow of lower silicon wafer

[0077] Step one: clean the silicon wafer to remove dust, impurities and organic matter on the surface of the silicon wafer, the specific steps are deionized water-alcohol-acetone-alcohol-deionized water, and the surface moisture of the silicon wafer is dried in an oven after cleaning.

[0078] Step two: 4-inch 500-μm-thick double-polished silicon wafer with an oxide layer thickness of 2 μm, first spin-coat photoresist S1813, then ultraviolet exposure (as shown in Figure 9The structure pattern in the middle 3 is developed with special developer, and then immersed in BOE solution, and the oxide layer at the front side, back side via and alignment mark of the silicon wafer is selectively removed after a period of time. Figure 9 The structure pattern in the middle 3 is developed with special developer, and then immersed in BOE solution, and the oxide layer at the front side, back side via and alignment mark of the silicon wafer is selectively removed after a period of time.

[0079] Step three: glue coating and exposure, using photoresist as mask, after UV exposure and development, patterned Ti adhesion layer by magnetron sputtering, thickness 10 nm, patterned Pt thin film by magnetron sputtering, thickness 100 nm, as the lower silicon wafer heating film (as shown in the middle 1), patterned Au thin film by magnetron sputtering, thickness 300 nm, as the lead part of the lower silicon wafer heating film (as shown in the middle 2). Figure 9 The structure pattern in the middle 3 is developed with special developer, and then immersed in BOE solution, and the oxide layer at the front side, back side via and alignment mark of the silicon wafer is selectively removed after a period of time. Figure 9 The structure pattern in the middle 3 is developed with special developer, and then immersed in BOE solution, and the oxide layer at the front side, back side via and alignment mark of the silicon wafer is selectively removed after a period of time.

[0080] Step four: high temperature annealing in low vacuum or nitrogen environment, heating rate 300℃ / h, temperature 600℃, holding time 4h, natural cooling, through metal recrystallization, the electrical properties of the film are more stable, and the film stress is reduced.

[0081] Step five: via etching by plasma, complete the etching of the lead via (as shown in the middle 3). Figure 9 The structure pattern in the middle 3 is developed with special developer, and then immersed in BOE solution, and the oxide layer at the front side, back side via and alignment mark of the silicon wafer is selectively removed after a period of time.

[0082] 4. Multi-layer wafer bonding

[0083] Step one: standard silicon-glass anodic bonding is performed on the upper silicon wafer and glass.

[0084] Step two: spin-coat BCB auxiliary bonding glue on the surface of the lower silicon wafer, and put it into the bonding machine for auxiliary bonding of the glass-upper silicon wafer and the lower silicon wafer under vacuum condition.

[0085] The above is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this, any change or replacement within the technical range disclosed by the present application can be easily thought by those skilled in the art, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A microscale two-dimensional array integrated temperature measurement method based on MEMS technology, characterized in that, The method comprises the following steps: S1. Integrating a two-dimensional temperature measurement resistance network in a microfluidic device based on a MEMS magnetic control sputtering process; S2. Establishing a mathematical relationship model between data points and external terminal resistance values; S3. Testing the external terminal resistance values of the resistance network, inversely deriving the internal resistance values of the resistance network, and deriving the temperature field distribution in a microchannel of the microfluidic device based on the resistance temperature characteristics in the resistance network and the relationship model; In step S3, the specific method of the inversion includes two methods: an iterative method and a Laplace matrix method; The iterative method is to iteratively calculate the original equation set according to the original value, to obtain the resistance values of the resistance lines between the internal data points by using a bisection method, a simple iterative method, a Newton method and a secant method, to establish a linear equation set between the resistance values and the temperatures of the internal data points, to solve the linear equation set by using an optimization method, and to obtain an optimized solution, which is the internal temperature field of the resistance network; The Laplace matrix method is to first construct a Laplace matrix according to the resistance network, to then solve the generalized inverse of the Laplace matrix, to obtain the resistance values between the internal data points according to the external test values during the solving process by using an optimization method, to establish a linear equation set between the resistance values and the temperatures of the internal data points, and to finally solve the linear equation set by using an optimization method again to obtain an optimized solution, which is the internal temperature field of the resistance network.

2. The microscale two-dimensional array integrated temperature measurement method based on a MEMS process according to claim 1, wherein The microfluidic device comprises a glass sheet, an intermediate silicon sheet and a lower silicon sheet; In step S1, the step of integrating the two-dimensional temperature measurement resistance network in the microchannel device comprises the following steps: S11. Processing the glass sheet; S12. Processing the intermediate silicon sheet; S13. Processing the lower silicon sheet; S14. Bonding the glass sheet, the intermediate silicon sheet and the lower silicon sheet in sequence.

3. The microscale two-dimensional array integrated temperature measurement method based on a MEMS process according to claim 2, wherein The relationship between the data points and the leads is as follows: wherein a is the number of the data points, and b is the number of the leads.

4. The microscale two-dimensional array integrated temperature measurement method based on a MEMS process according to claim 2, wherein The number of the data points of the two-dimensional temperature measurement resistance network is less than or equal to the number of the test data.

5. The microscale two-dimensional array integrated temperature measurement method based on a MEMS process according to claim 2, wherein The materials, sizes and resistance values of the resistors in the resistance network are all the same.

6. The microscale two-dimensional array integrated temperature measurement method based on a MEMS process according to claim 2, wherein The resistors in the resistance network are all thin-film platinum thermal resistors.

7. The microscale two-dimensional array integrated temperature measurement method based on a MEMS process according to claim 1, wherein In step S2, the mathematical relationship model is as follows: wherein n is the number of resistance lines between the data points that are connected to each other, a1-a n are the resistance values of the resistance lines between the data points that are connected to each other, b is the number of external test points, are the resistance values between the external test points, is a functional relationship between the resistance values of the external test points and the data points.

Images