A chip test and pin multiplexing unit and related methods and related chips

Abstract

Embodiments of the present application disclose a chip test and pin multiplexing unit, a related method and a related chip. The chip test and pin multiplexing unit is applied to a chip, the chip comprising M chip function units, M pins and the chip test and pin multiplexing unit, the chip function units and the pins corresponding one by one; the chip test and pin multiplexing unit comprising a chip test module, a pin multiplexing module, M first switch modules and M second switch modules, the value of M being an integer greater than 1, and the value of N being twice the value of M, so that the pins corresponding to the chip function units of the chip are multiplexed to realize chip test, and no independent pin needs to be additionally added for chip test, thereby being conducive to reducing the pins of the chip in the design, packaging and integration and the like, and further being conducive to reducing the size of the chip and reducing the cost of the chip in the design, integration and packaging.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing, specifically to chip testing and pin multiplexing units and related methods and chips. Background Technology

[0002] Before mass production, chips need to undergo various test modes. In these test modes, the chip is tested using built-in test circuits. After completing the tests, the chip transitions from test mode to normal operating mode and executes its functions through built-in circuits, ensuring the quality of the chip's output and operation.

[0003] However, current chip testing methods often utilize individual pins. This necessitates the addition of extra pins for chip testing during chip design, integration, and packaging, resulting in increased chip size and higher costs in design, integration, and packaging. Summary of the Invention

[0004] This application provides a chip testing and pin reuse unit, related methods, and related chips, which aim to achieve chip testing by reusing the pins corresponding to the existing chip functional units, without the need to add additional independent pins for chip testing. This helps to reduce the number of pins in the chip design, packaging, and integration stages, thereby reducing the chip size and lowering the cost of chip design, integration, and packaging.

[0005] In a first aspect, this application provides a chip testing and pin multiplexing unit applied to a chip, the chip including M chip functional units, M pins and the chip testing and pin multiplexing unit, the chip functional units and the pins corresponding one-to-one; the chip testing and pin multiplexing unit includes a chip testing module, a pin multiplexing module, M first switch modules and M second switch modules, where M is an integer greater than 1 and N is twice the value of M;

[0006] The chip testing module connects to M pins through M first switch modules and the pin multiplexing module;

[0007] Each of the chip functional units is connected to a corresponding pin through a second switch module and the pin multiplexing module;

[0008] The pin multiplexing module is connected to M pins, M first switch modules, and M second switch modules respectively;

[0009] The chip testing module is used to perform chip testing on the chip by reusing the pins corresponding to each of the M chip functional units.

[0010] The chip functional unit is used to perform the chip functions it possesses;

[0011] The pin multiplexing module is used to control M first switch modules and M second switch modules so that the chip test module multiplexes the pins corresponding to each of the M chip functional units.

[0012] As can be seen, the chip testing and pin multiplexing unit of this application realizes chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip, without the need to add independent pins for chip testing. This helps to reduce the number of pins in the design, packaging and integration of the chip, thereby reducing the chip size and the cost of chip design, integration and packaging.

[0013] In addition, since the pin multiplexing module can control M first switch modules and M second switch modules, the M pins can be repeatedly allocated to the chip test module for use, thereby ensuring that the chip can repeatedly enter and exit the test mode, improving the efficiency of chip testing and increasing the utilization of the chip.

[0014] Secondly, this application provides a chip testing and pin multiplexing method applied to a chip, wherein the chip includes M chip functional units, M pins, and a chip testing and pin multiplexing unit, wherein the chip functional units and the pins correspond one-to-one, and the chip testing and pin multiplexing unit includes a chip testing module, a pin multiplexing module, M first switch modules, and M second switch modules, wherein M is an integer greater than 1, and N is twice the value of M; the method includes:

[0015] When the chip is powered on and in standby mode, it receives a wake-up signal, which is used to trigger the chip to enter the detection mode.

[0016] When the chip enters the detection state, the signals detected from the M pins by the pin multiplexing module are used to control the M first switch modules and the M second switch modules so that the chip test module multiplexes the pins corresponding to the M chip functional units.

[0017] As can be seen, this application achieves chip testing by reusing the pins corresponding to the existing chip functional units, without the need to add additional independent pins for chip testing. This helps to reduce the number of pins in the design, packaging and integration stages of the chip, thereby reducing the chip size and lowering the cost of chip design, integration and packaging.

[0018] In addition, since the pin multiplexing module can control M first switch modules and M second switch modules, the M pins can be repeatedly allocated to the chip test module for use, thereby ensuring that the chip can repeatedly enter and exit the test mode, improving the efficiency of chip testing and increasing the utilization of the chip.

[0019] Thirdly, this application provides a chip including M chip functional units, M pins, and the chip testing and pin multiplexing unit mentioned in the first aspect, wherein the chip functional units and the pins correspond one-to-one, and the value of M is an integer greater than 1. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the structure of another chip provided in the embodiments of this application;

[0023] Figures 3 to 6 This is a schematic diagram of the state control and transition structure of a chip provided in an embodiment of this application;

[0024] Figure 7 This is a schematic flowchart of a chip testing and pin reuse method provided in an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0026] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, software, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0027] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed connection, an electrical connection, a detachable connection, a flexible connection, a direct connection, an indirect connection through an intermediate medium, a spaced connection, etc., without any specific limitation.

[0028] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0029] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. The chip 10 may include: M chip functional units (such as chip functional unit 1201, chip functional unit 1202, etc.), M pins (such as pin 1301, pin 1302, etc.), and a chip testing and pin multiplexing unit 110. The chip testing and pin multiplexing unit 110 may include a chip testing module 1101, a pin multiplexing module 1102, M first switch modules (such as first switch module 1103, first switch module 1104, etc.), and M second switch modules (such as second switch module 1105, second switch module 1106). M is an integer greater than 1, and N is twice the value of M.

[0030] In this chip, the functional units and pins can be matched one-to-one. It is understandable that each of the existing functional units of chip 10 has its own corresponding pin.

[0031] For example, chip functional unit 1201 corresponds to pin 1301, and chip functional unit 1202 corresponds to pin 1302.

[0032] The chip test module 1101 can be connected to M pins through M first switch modules and pin multiplexing module 1102.

[0033] For example, the chip test module 1101 is connected to pins 1301 and 1302 through the first switch module 1103, the first switch module 1104 and the pin multiplexing module 1102.

[0034] Each chip functional unit can be connected to a corresponding pin through a second switch module and a pin multiplexing module 1102.

[0035] For example, chip functional unit 1201 is connected to pin 1301 through second switch module 1105 and pin multiplexing module 1102, and chip functional unit 1202 is connected to pin 1302 through second switch module 1106 and pin multiplexing module 1102.

[0036] The pin multiplexing module 1102 can connect to M pins, M first switch modules, and M second switch modules respectively.

[0037] For example, the pin multiplexing module 1102 is connected to pins 1301, 1302, the first switch module 1103, the first switch module 1104, the second switch module 1105, and the second switch module 1106, respectively.

[0038] The chip test module 1101 can be used to perform chip testing on chip 10 by reusing the pins corresponding to each of the M chip functional units.

[0039] For example, chip test module 1101 performs chip test on chip 10 by multiplexing pins 1301 and 1302.

[0040] The chip functional unit can be used to execute the chip functions it possesses. Furthermore, different chip functional units may execute different chip functions of chip 10.

[0041] The pin multiplexing module 1102 can control M first switch modules and M second switch modules to enable the chip test module 1101 to multiplex the pins corresponding to the M chip functional units. It can be understood that the pin multiplexing module 1102 can control the on / off states of the M first switch modules and M second switch modules.

[0042] For example, the pin multiplexing module 1102 controls the on / off states of the first switch module 1103, the first switch module 1104, the second switch module 1105, and the second switch module 1106 so that the chip test module 1101 multiplexes the pin 1301 corresponding to the chip functional unit 1201 and the pin 1302 corresponding to the chip functional unit 1202.

[0043] It's important to note that before mass production, chips need to undergo various testing modes. In these modes, the chip is tested using built-in test circuits. After completing the tests, the chip transitions from test mode to normal operating mode and executes its functions via built-in circuitry, ensuring the quality of the chip's output and operation.

[0044] However, current chip testing methods often utilize individual pins. This necessitates the addition of extra pins for chip testing during chip design, integration, and packaging, resulting in increased chip size and higher costs in design, integration, and packaging.

[0045] For example, in Figure 2 In this chip, chip 20 adds two extra pins for chip testing, namely pins 2301 and 2302. These two pins are unrelated to the pins corresponding to the chip functional units (pin 2303 for chip functional unit 2201 and pin 2304 for chip functional unit 2202). Although chip 20 can reuse pins 2301 and 2302 to enter test mode via chip test module 2101, these two extra pins will be idle and wasted when chip 20 completes testing and enters operating mode to use the chip functional units. Therefore, when chip pin resources are particularly scarce, adding extra pins for chip testing will increase the chip size and the cost of chip design / integration / packaging.

[0046] Based on this, the pin multiplexing module 1102 of this application embodiment controls M first switch modules and M second switch modules so that the chip test module 1101 multiplexes the pins corresponding to each of the M chip functional units, and then the chip test module performs chip test on the chip 10 through the multiplexed M pins.

[0047] As can be seen, the chip testing and pin multiplexing unit 110 of this application embodiment realizes chip testing by multiplexing the pins corresponding to the existing chip functional units of the chip 10, without the need to add independent pins for chip testing. This helps to reduce the number of pins in the design, packaging and integration of the chip, thereby reducing the size of the chip and the cost of chip design, integration and packaging.

[0048] In addition, since the pin multiplexing module 1102 can control M first switch modules and M second switch modules, the M pins can be repeatedly allocated to the chip test module 1101 for use, thereby ensuring that the chip 10 can repeatedly enter and exit the test mode, improving the efficiency of chip testing and increasing the utilization of the chip.

[0049] Based on the above description, the pin multiplexing module 1102 of this application embodiment will be specifically described below.

[0050] Specifically, the pin multiplexing module 1102 can be used to detect a first signal through M pins; the first signal can be used to trigger the pin multiplexing module 1102 to control M first switch modules and M second switch modules to allocate the M pins to the chip test module 1101 or M chip functional units.

[0051] It should be noted that the pin multiplexing module 1102 of this application can detect signals outside the chip 10 through M pins to determine whether to allocate the M pins to the chip test module 1101 or to the M chip function modules.

[0052] For example, if chip 10 needs to enter test mode, and pin multiplexing module 1102 detects the first signal through M pins, then pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate M pins to chip test module 1101 for use.

[0053] If chip 10 needs to enter the working mode, or chip 10 needs to enter the working mode from the test mode, and the pin multiplexing module 1102 detects the first signal through M pins, then the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to M chip functional units for use.

[0054] Optionally, the first signal may include a pull-up voltage signal or a pull-down voltage signal.

[0055] If the pin multiplexing module 1102 detects a pull-up voltage signal outside the chip 10 through M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to the chip test module 1101 for use; if the pin multiplexing module 1102 detects a pull-down voltage signal outside the chip 10 through M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to M chip functional units for use.

[0056] Similarly, when a pull-down voltage is applied to M pins outside the chip 10, the M pins are allocated to the chip test module 1101 for use, without any specific restrictions.

[0057] For example, please refer to Figure 3After power-on, chip 10 is in standby mode. When a wake-up signal is generated, chip 10 enters detection mode and detects signals applied to M pins externally through pin multiplexing module 1102.

[0058] If the pin multiplexing module 1102 detects a pull-up voltage signal through the M pins, it controls the M first switch modules and the M second switch modules to allocate the M pins to the chip test module 1101 for use, thereby enabling the chip 10 to enter the test mode.

[0059] If the pin multiplexing module 1102 detects a pull-down voltage signal through the M pins, it controls the M first switch modules and the M second switch modules to allocate the M pins to the M chip functional units, thereby enabling the chip 10 to enter the working mode.

[0060] If chip 10 needs to enter working mode from test mode, and pin multiplexing module 1102 detects pull-down voltage signals through the M pins, it controls the M first switch modules and M second switch modules to allocate the M pins to the M chip functional units, thereby enabling chip 10 to enter working mode from test mode.

[0061] In the working mode, chip 10 can choose whether to enter the standby mode according to the current state, and this cycle continues continuously, so as to ensure that chip 10 can switch freely between the test mode and the working mode according to actual needs, and to achieve the purpose of multiplexing M pins.

[0062] Specifically, the pin multiplexing module 1102 can be used to detect the presence of a second signal within a preset time using M pins; the second signal can be used to trigger the pin multiplexing module 1102 to allocate the M pins to the chip test module by controlling M first switch modules and M second switch modules; wherein, if the second signal is detected within the preset time, the pin multiplexing module 1102 allocates the M pins to the chip test module 1101; if the second signal is not detected within the preset time, the pin multiplexing module 1102 allocates the M pins to M chip functional units.

[0063] It should be noted that, unlike the above, this application also considers that it does not require the detection of external signals to trigger the pin multiplexing module 1102 to allocate the M pins to the M chip functional units. Instead, it directly determines whether a second signal is detected within a preset time. If the second signal is detected within the preset time, the M pins are allocated to the chip test module 1101; if the second signal is not detected within the preset time, the M pins are allocated to the M chip functional units, thereby improving processing efficiency.

[0064] Optionally, the second signal may include a pull-up voltage signal or a pull-down voltage signal.

[0065] If a pull-up voltage signal is detected within a preset time, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate M pins to the chip test module 1101 for use; if no pull-up voltage signal is detected within the preset time, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate M pins to M chip functional units for use.

[0066] For example, please refer to Figure 4 After power-on, chip 10 is in standby mode. When a wake-up signal is generated, chip 10 enters detection mode, and in detection mode, the pin multiplexing module 1102 detects whether signals are externally applied to M pins within a preset time.

[0067] If the pin multiplexing module 1102 detects the second signal through the M pins within a preset time, it controls the M first switch modules and the M second switch modules to allocate the M pins to the chip test module 1101 for use, thereby enabling the chip 10 to enter the test mode.

[0068] If the pin multiplexing module 1102 does not detect a pull-up voltage signal through the M pins within a preset time, it controls the M first switch modules and the M second switch modules to allocate the M pins to the M chip functional units, thereby enabling the chip 10 to enter the working mode.

[0069] If chip 10 needs to enter working mode from test mode, it exits test mode by detecting a signal (either by detecting the first signal through pin multiplexing module 1102 or by detecting a signal through chip test module 1101, as described below), thereby enabling chip 10 to enter working mode from test mode.

[0070] In working mode, chip 10 can choose whether to enter standby mode based on the current state, and this cycle continues continuously, thereby ensuring that it can switch freely between test mode and working mode according to actual needs, and achieving the purpose of multiplexing M pins.

[0071] Based on the above description, the chip testing module 1101 of this application embodiment will be specifically described below.

[0072] Specifically, the chip test module 1101 can be used to detect a third signal through M pins when M pins are allocated to the chip test module 1101; the third signal can be used to trigger the chip test module 1101 to send a fourth signal to the pin multiplexing module 1102; the fourth signal is used to trigger the pin multiplexing module 1102 to allocate the M pins to M chip functional units by controlling M first switch modules and M second switch modules.

[0073] It should be noted that the allocation of M pins to the chip test module 1101 can be understood as the chip test module 1101 multiplexing the pins corresponding to the M chip functional units, or the chip 10 entering test mode. Therefore, when the chip 10 needs to enter the working mode from the test mode, the chip test module 1101 can detect the third signal through the M pins, and the third signal triggers the chip test module 1101 to send a fourth signal to the pin multiplexing module 1102. Finally, the fourth signal triggers the pin multiplexing module 1102 to allocate the M pins to the M chip functional units, thereby realizing the chip 10 entering the working mode from the test mode.

[0074] Optionally, the third signal may include at least one of the following: an Inter-Integrated Circuit (I2C) protocol signal, a Serial Peripheral Interface (SPI) protocol signal, or a Joint Test Action Group (JTAG) protocol signal.

[0075] It should be noted that if the third signal includes an I2C protocol signal, and the I2C protocol is usually a two-wire serial bus, then the value of M can be 2. That is, the chip test module reuses the pins corresponding to the two existing chip functional units of chip 10, so as to realize the chip 10 from test mode to working mode through the two-wire communication protocol (I2C).

[0076] If the third signal includes an SPI protocol signal, and the SPI protocol is usually a three-wire or four-wire serial bus, then the value of M can be 3 or 4. That is, the chip test module reuses the pins corresponding to the existing 3 or 4 chip functional units of chip 10, so as to realize the chip 10 from test mode to working mode through the three-wire or four-wire communication protocol (SIP).

[0077] If the third signal includes a JTAG protocol signal, and the JTAG protocol is usually a four-wire serial bus, then the value of M can be 4. That is, the chip test module reuses the pins corresponding to the four existing chip functional units of chip 10, thereby enabling chip 10 to enter the working mode from the test mode through the four-wire communication protocol (JTAG).

[0078] Optionally, the fourth signal can be determined by the protocol interface supported by the chip test module 1101 and the pin multiplexing module 1102, such as a serial interface, a synchronous serial interface, or an I2C protocol interface.

[0079] For example, please refer to Figure 5 or Figure 6 In combination with the above Figure 3 or Figure 4 It can be seen that, in Figure 5 or Figure 6 If chip 10 needs to enter working mode from test mode, and pin multiplexing module 1102 detects a third signal through the M pins, then chip test module 1101 sends a fourth signal to pin multiplexing module 1102, and pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to M chip functional units, thereby enabling chip 10 to enter working mode.

[0080] Specifically, the chip test module 1101 can be used to detect a fifth signal through M pins when M pins are assigned to the chip test module 1101. The fifth signal can be used to determine the chip test strategy for the chip, which includes at least one of the following: reading the internal operating state of the chip, debugging and calibrating the internal circuit of the chip, and burning configuration parameters into the chip's memory.

[0081] The configuration parameters can be used to update and upgrade chip 10, perform chip testing, etc.

[0082] It should be noted that when the chip test module 1101 reuses the pins corresponding to each of the M chip functional units, or when the chip 10 enters the test mode, the chip test module 1101 can read the internal operating status of the chip 10, debug and calibrate the internal circuit of the chip 10, and burn configuration parameters into the memory of the chip 10 through the fifth signal detected by the M pins.

[0083] Optionally, the fifth signal may include at least one of the following: I2C protocol signal, SPI protocol signal, and JTAG protocol signal.

[0084] It should be noted that if the fifth signal includes an I2C protocol signal, and the I2C protocol is usually a two-wire serial bus, then the value of M can be 2. That is, the chip test module reuses the pins corresponding to the two existing chip functional units of chip 10, thereby performing chip testing on chip 10 through the two-wire communication protocol (I2C).

[0085] If the fifth signal includes an SPI protocol signal, and the SPI protocol is usually a three-wire or four-wire serial bus, then the value of M can be 3 or 4. That is, the chip test module reuses the pins corresponding to the existing 3 or 4 chip functional units of chip 10, so as to perform chip testing on chip 10 through the three-wire or four-wire communication protocol (SIP).

[0086] If the fifth signal includes a JTAG protocol signal, and the JTAG protocol is usually a four-wire serial bus, then the value of M can be 4. That is, the chip test module reuses the pins corresponding to the four existing chip functional units of chip 10, thereby performing chip testing on chip 10 through the four-wire communication protocol (JTAG).

[0087] Consistent with the above embodiments, the following embodiments of this application will describe the execution steps of the chip testing and pin multiplexing unit from the perspective of method examples. Please refer to... Figure 7 . Figure 7 This is a flowchart illustrating a chip testing and pin multiplexing method provided in an embodiment of this application. The method is applied to chip 10, which includes M chip functional units, M pins, and a chip testing and pin multiplexing unit 110. The chip functional units and pins correspond one-to-one. The chip testing and pin multiplexing unit 110 may include a chip testing module 1101, a pin multiplexing module 1102, M first switch modules, and M second switch modules. M is an integer greater than 1, and N is twice the value of M. The method includes the following steps:

[0088] S710: When the chip is powered on and in standby mode, it receives a wake-up signal, which is used to trigger the chip to enter the detection state.

[0089] S720: When the chip enters the detection state, the signal detected from M pins by the pin multiplexing module is used to control M first switch modules and M second switch modules so that the chip test module can multiplex the pins corresponding to the M chip functional units.

[0090] It should be noted that, firstly, chip 10 needs to detect a wake-up signal in standby mode, and then enters the detection mode after detecting the wake-up signal. The wake-up signal can be determined by the communication protocol supported by the internal mode of chip 10, such as a serial signal or a synchronous serial signal.

[0091] Secondly, chip 10 detects signals in the detection state to determine whether it has entered the detection state or the working state. In test mode, chip 10 can perform chip tests through the chip test module; in working mode, chip 10 can execute relevant chip functions through M chip functional units.

[0092] Finally, the pin multiplexing module 1102 in chip 10 controls M first switch modules and M second switch modules to enable chip test module 1101 to multiplex the pins corresponding to each of the M chip functional units, so that chip 10 enters the test mode, and finally chip test module 1101 performs chip test on chip 10 through the multiplexed M pins.

[0093] As can be seen, this application achieves chip testing by reusing the pins corresponding to the existing chip functional units, without the need to add additional independent pins for chip testing. This helps to reduce the number of pins in the design, packaging and integration stages of the chip, thereby reducing the chip size and lowering the cost of chip design, integration and packaging.

[0094] In addition, since the pin multiplexing module can control M first switch modules and M second switch modules, the M pins can be repeatedly allocated to the chip test module for use, thereby ensuring that the chip can repeatedly enter and exit the test mode, improving the efficiency of chip testing and increasing the utilization of the chip.

[0095] Specifically, in S730, the signal detected from M pins by the pin multiplexing module to control M first switch modules and M second switch modules so that the chip test module can multiplex the pins corresponding to the M chip functional units can include: detecting a first signal from the M pins by the pin multiplexing module, and the first signal can be used to trigger the pin multiplexing module to control the M first switch modules and M second switch modules to allocate the M pins to the chip test module or the M chip functional units.

[0096] It should be noted that the pin multiplexing module 1102 of this application can detect signals outside the chip 10 through M pins to determine whether to allocate the M pins to the chip test module 1101 or to the M chip function modules.

[0097] For example, if chip 10 needs to enter test mode, and pin multiplexing module 1102 detects the first signal through M pins, then pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate M pins to chip test module 1101 for use.

[0098] If chip 10 needs to enter the working mode, or chip 10 needs to enter the working mode from the test mode, and the pin multiplexing module 1102 detects the first signal through M pins, then the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to M chip functional units for use.

[0099] Optionally, the first signal may include a pull-up voltage signal or a pull-down voltage signal.

[0100] If the pin multiplexing module 1102 detects a pull-up voltage signal outside the chip 10 through M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to the chip test module 1101 for use; if the pin multiplexing module 1102 detects a pull-down voltage signal outside the chip 10 through M pins, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate the M pins to M chip functional units for use.

[0101] Similarly, when a pull-down voltage is applied to M pins outside the chip 10, the M pins are allocated to the chip test module 1101 for use, without any specific restrictions.

[0102] For example, please refer to the above. Figure 3 This will not be elaborated upon here.

[0103] Specifically, in S730, the signal detected from M pins by the pin multiplexing module to control M first switch modules and M second switch modules so that the chip test module multiplexes the pins corresponding to the M chip functional units can include: the pin multiplexing module detecting the presence of a second signal from the M pins within a preset time. The second signal can be used to trigger the pin multiplexing module to control the M first switch modules and M second switch modules to allocate the M pins to the chip test module for use. If the second signal is detected within the preset time, the M pins are allocated to the chip test module for use; if the second signal is not detected within the preset time, the M pins are allocated to the M chip functional units for use.

[0104] It should be noted that, unlike the above, this application also considers that it does not require the detection of external signals to trigger the pin multiplexing module 1102 to allocate the M pins to the M chip functional units. Instead, it directly determines whether a second signal is detected within a preset time. If the second signal is detected within the preset time, the M pins are allocated to the chip test module 1101; if the second signal is not detected within the preset time, the M pins are allocated to the M chip functional units, thereby improving processing efficiency.

[0105] Optionally, the second signal may include a pull-up voltage signal or a pull-down voltage signal.

[0106] If a pull-up voltage signal is detected within a preset time, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate M pins to the chip test module 1101 for use; if no pull-up voltage signal is detected within the preset time, the pin multiplexing module 1102 controls M first switch modules and M second switch modules to allocate M pins to M chip functional units for use.

[0107] For example, please refer to the above. Figure 4 This will not be elaborated upon here.

[0108] Specifically, this application may further include: under the condition that the chip test module reuses the pins corresponding to each of the M chip functional units, the chip test module detects a third signal from the M pins, the third signal is used to trigger the chip test module to send a fourth signal to the pin multiplexing module, and the fourth signal is used to trigger the pin multiplexing module to allocate the M pins to the M chip functional units for use by controlling the M first switch modules and the M second switch modules.

[0109] It should be noted that the allocation of M pins to the chip test module 1101 can be understood as the chip test module 1101 multiplexing the pins corresponding to the M chip functional units, or the chip 10 entering test mode. Therefore, when the chip 10 needs to enter the working mode from the test mode, the chip test module 1101 can detect the third signal through the M pins, and the third signal triggers the chip test module 1101 to send a fourth signal to the pin multiplexing module 1102. Finally, the fourth signal triggers the pin multiplexing module 1102 to allocate the M pins to the M chip functional units, thereby realizing the chip 10 entering the working mode from the test mode.

[0110] Optionally, the third signal may include at least one of the following: I2C protocol signal, SPI protocol signal, and JTAG protocol signal.

[0111] It should be noted that this application can enable the chip 10 to enter the working mode from the test mode via a two-wire communication protocol (I2C) or a three-wire or four-wire communication protocol (SIP, JTAG).

[0112] Optionally, the fourth signal can be determined by the protocol interface supported by the chip test module 1101 and the pin multiplexing module 1102, such as a serial interface, a synchronous serial interface, or an I2C protocol interface.

[0113] For example, please refer to the above. Figure 5 or Figure 6 This will not be elaborated upon here.

[0114] Specifically, this application may also include: under the condition that the chip test module reuses the pins corresponding to the M chip functional units, the chip test module detects a fifth signal from the M pins, the fifth signal is used to determine the chip test strategy for the chip, and the chip test strategy includes at least one of the following: reading the internal operating state of the chip, debugging and calibrating the internal circuit of the chip, and burning configuration parameters to the chip's memory.

[0115] The configuration parameters can be used to update and upgrade chip 10, perform chip testing, etc.

[0116] It should be noted that when the chip test module 1101 reuses the pins corresponding to each of the M chip functional units, or when the chip 10 enters the test mode, the chip test module 1101 can read the internal operating status of the chip 10, debug and calibrate the internal circuit of the chip 10, and burn configuration parameters into the memory of the chip 10 through the fifth signal detected by the M pins.

[0117] Optionally, the fifth signal may include at least one of the following: I2C protocol signal, SPI protocol signal, and JTAG protocol signal.

[0118] It should be noted that this application can perform chip testing on chip 10 through two-wire communication protocol (I2C), three-wire or four-wire communication protocol (SIP, JTAG), such as reading the internal operating status of the chip, debugging and calibrating the internal circuit of the chip, and burning configuration parameters to the chip's memory.

[0119] The chip testing and pin multiplexing unit and chip testing and pin multiplexing method provided in the embodiments of this application have been described in detail above. Specific embodiments have been used to illustrate the principles and implementation methods involved in the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. A chip testing and pin multiplexing unit, characterized in that, The chip is applied to a chip, which includes M chip functional units, M pins, and a chip testing and pin multiplexing unit, wherein the chip functional units and the pins correspond one-to-one; the chip testing and pin multiplexing unit includes a chip testing circuit, a pin multiplexing circuit, M first switching circuits, and M second switching circuits, wherein the value of M is an integer greater than 1; The chip test circuit connects to the M pins through the M first switching circuits and the pin multiplexing circuit; Each of the chip functional units is connected to a corresponding pin through a second switching circuit and the pin multiplexing circuit; The pin multiplexing circuit is connected to M pins, M first switching circuits and M second switching circuits respectively; The chip test circuit is used to perform chip testing on the chip by reusing the pins corresponding to each of the M chip functional units. The chip functional unit is used to perform the chip functions it possesses; The pin multiplexing circuit is used to control M first switching circuits and M second switching circuits so that the chip test circuit multiplexes the pins corresponding to each of the M chip functional units; wherein, the pin multiplexing circuit can control the on / off state of the M first switching circuits and M second switching circuits.

2. The chip test and pin multiplexing unit of claim 1, wherein, The pin multiplexing circuit is specifically used to detect a first signal through the M pins; The first signal is used to trigger the pin multiplexing circuit to control M first switching circuits and M second switching circuits to allocate M pins to the chip test circuit or M chip functional units.

3. The chip test and pin multiplexing unit of claim 2, wherein, The first signal includes a pull-up voltage signal or a pull-down voltage signal.

4. The chip testing and pin multiplexing unit of any one of claims 1 to 3, wherein, The pin multiplexing circuit is specifically used to detect the presence of a second signal within a preset time using the M pins. The second signal is used to trigger the pin multiplexing circuit to allocate the M pins to the chip test circuit by controlling the M first switching circuits and the M second switching circuits; wherein, If the second signal is detected within the preset time period, the pin multiplexing circuit will allocate M of the pins to the chip test circuit for use; If the second signal is not detected within the preset time, the pin multiplexing circuit will allocate M of the pins to M of the chip functional units for use.

5. The chip testing and pin multiplexing unit of any one of claims 1 to 3, wherein, The chip test circuit is specifically used to detect a third signal through the M pins when the M pins are allocated to the chip test circuit. The third signal is used to trigger the chip test circuit to send a fourth signal to the pin multiplexing circuit; The fourth signal is used to trigger the pin multiplexing circuit to allocate the M pins to the M chip functional units by controlling the M first switching circuits and the M second switching circuits.

6. The chip test and pin multiplexing unit of claim 5, wherein, The third signal includes at least one of the following: internal integrated circuit I2C protocol signal, serial peripheral interface SPI protocol signal, and joint test working group JTAG protocol signal.

7. The chip testing and pin multiplexing unit of any one of claims 1 to 3, wherein, The chip test circuit is specifically used to detect the fifth signal through the M pins when the M pins are allocated to the chip test circuit. The fifth signal is used to determine a chip testing strategy for the chip, which includes at least one of the following: reading the internal operating state of the chip, debugging and calibrating the internal circuitry of the chip, and burning configuration parameters into the memory of the chip.

8. A method for chip testing and pin multiplexing, comprising: The chip is applied to a chip, which includes M chip functional units, M pins, and a chip testing and pin multiplexing unit. The chip functional units and the pins correspond one-to-one. The chip testing and pin multiplexing unit includes a chip testing circuit, a pin multiplexing circuit, M first switching circuits, and M second switching circuits. The value of M is an integer greater than 1. The chip test circuit connects to M pins via M first switch circuits and the pin multiplexing circuit; Each of the chip functional units is connected to a corresponding pin through a second switching circuit and the pin multiplexing circuit; The pin multiplexing circuit is connected to M pins, M first switching circuits, and M second switching circuits respectively; wherein, the pin multiplexing circuit can control the on / off state of the M first switching circuits and the M second switching circuits; The method includes: When the chip is powered on and in standby mode, it receives a wake-up signal, which is used to trigger the chip to enter the detection mode. When the chip enters the detection state, the signals detected from the M pins by the pin multiplexing circuit control the M first switching circuits and the M second switching circuits so that the chip test circuit multiplexes the pins corresponding to the M chip functional units.

9. The method of claim 8, wherein, The step of controlling M first switching circuits and M second switching circuits by means of signals detected from M pins through the pin multiplexing circuit, so that the chip test circuit multiplexes the pins corresponding to each of the M chip functional units, includes: A first signal is detected from the M pins via the pin multiplexing circuit. This first signal triggers the pin multiplexing circuit to control the M first switching circuits and the M second switching circuits to allocate the M pins to the chip test circuit or the M chip functional units; or... The pin multiplexing circuit detects whether a second signal exists in the M pins within a preset time, the second signal being used to trigger the pin multiplexing circuit to control the M first switch circuits and the M second switch circuits to allocate the M pins to the chip test circuit; if the second signal is detected within the preset time, the M pins are allocated to the chip test circuit; if the second signal is not detected within the preset time, the M pins are allocated to the M chip functional units.

10. A chip comprising M chip functional units, M pins and a chip test and pin multiplexing unit according to any one of claims 1 to 7, the chip functional units and the pins being in one-to-one correspondence, M being an integer greater than 1.

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