Memory controller and method for controlling access to a memory module

Abstract

A memory controller coupled between a memory module and a host controller to control access of the memory module by the host controller, the memory controller comprising: a central buffer coupled to the host controller via a command / address bus to receive command / address signals from the host controller, wherein the central buffer is configured to determine whether the command / address signals comply with an access management rule and configure a buffer control command according to the determination result, such that the buffer control command indicates whether to restrict access of the memory module by the host controller; and a data buffer coupled to the central buffer via a buffer control channel to receive the buffer control command, the data buffer is configured to selectively restrict access of the memory module by the host controller according to the buffer control command; wherein the buffer control command comprises a plurality of fields having a time sequence relationship, and the central buffer is configured to configure a field at a second or later time sequence in the buffer control command according to the determination result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and more particularly, to a memory controller and a method for controlling access to a memory module. BACKGROUND

[0002] In a computer system, a memory module is usually mainly used to provide storage of data required by a host controller or central processing unit (CPU) during operation. In some cases, for the sake of data security, a data access permission management rule is configured in the computer system and the host controller is limited or allowed to access the memory module according to the data access permission management rule.

[0003] A memory system can include a memory controller for controlling access of a host controller to a memory module. To control access of the host controller to the memory module, the memory controller can determine whether a received command / address (C / A) signal complies with a predetermined permission management rule, and selectively mask, convert to an invalid signal, or redirect the C / A signal that does not comply with the permission management rule to another memory address based on a determination result.

[0004] Such a memory controller can prevent the C / A signal that does not comply with the permission management rule from illegally reading data in the memory module or illegally writing data to the memory module, thereby effectively improving data security. However, the determination of the above permission management rule increases the processing time of the memory controller, can cause an error of an error checking and correction (ECC) function of the host controller, and can cause an unintended operation. Therefore, it is necessary to improve the existing computer system. SUMMARY

[0005] It is an object of the present application to provide a memory controller and a method for controlling access of a host controller to a memory module to improve control of an access command signal.

[0006] According to an aspect of the present application, a memory controller is provided, which is coupled between a memory module and a host controller to control access of the memory module by the host controller, the memory controller comprising: a central buffer coupled to the host controller via a command / address bus to receive command / address signals from the host controller, wherein the central buffer is configured to determine whether the command / address signals comply with an access management rule and configure a buffer control command according to the determination result, such that the buffer control command indicates whether to restrict access of the memory module by the host controller; and a data buffer coupled to the central buffer via a data buffer command channel to receive the buffer control command, the data buffer being configured to selectively restrict access of the memory module by the host controller according to the buffer control command; wherein the buffer control command comprises a plurality of fields having a timing relationship, and the central buffer is configured to configure a field in the second or later timing in the buffer control command according to the determination result.

[0007] In some embodiments, the central buffer is configured to configure a field in the last timing in the buffer control command according to the determination result.

[0008] In some embodiments, the data buffer comprises: a bypass data module configured to store meaningless data; and a buffer control module configured to control transmission of the meaningless data to the host controller in response to the command / address signals comprising a read command and the command / address signals not complying with the access management rule. In some such embodiments, the bypass data module comprises a meaningless data generation module configured to generate the meaningless data. In one embodiment, the meaningless data generation module is configured to receive a random seed from the central buffer and generate the meaningless data according to the random seed. In some such embodiments, the bypass data module is configured to receive the meaningless data from the central buffer.

[0009] In some embodiments, the central buffer comprises: a main signal path configured to receive the command / address signals from the main controller and provide the command / address signals to the memory module; a branch signal path coupled to the main signal path to receive the command / address signals, the branch signal path comprising a verification module configured to determine whether the command / address signals comply with the permission management rule and configure the buffer control command according to the determination result. In some such embodiments, the verification module is coupled to the data buffer through the data buffer command channel to send the buffer control command to the data buffer. In some such embodiments, the verification module comprises: an identification module coupled to the main signal path to receive the command / address signals, the identification module configured to identify an access command, an access address and / or an identity source information in the command / address signals; a management module coupled to the identification module to receive the access command, the access address and / or the identity source information in the command / address signals, the management module configured to determine whether the command / address signals comply with the permission management rule based on the access command, the access address and / or the identity source information and configure the buffer control command according to the determination result; and a rule module storing the permission management rule, the rule module coupled to the management module to provide the permission management rule to the management module. In some such embodiments, the verification module further comprises a configuration module coupled to the rule module, via which the permission management rule can be preconfigured or dynamically configured.

[0010] In some embodiments, the data buffer comprises: a bypass data module; a buffer control module, wherein the buffer control module is configured to, in response to the command / address signals comprising a write command and the command / address signals not complying with the permission management rule, control transmission of write data corresponding to the command / address signals into the bypass data module.

[0011] In some embodiments, the data buffer comprises: a bypass data module configured to store read data from the memory module; and a buffer control module, wherein the buffer control module is configured to control transmission of the read data stored in the bypass data module to the memory module in response to the command / address signals comprising a write signal and the command / address signals not complying with the permission management rule. In some such embodiments, the read data corresponds to a first address in the memory module, the buffer control module is configured to control transmission of the read data to a first address of the memory module in response to the command / address signals comprising a write command and not complying with the permission management rule, and the command / address signals comprising address information corresponding to the first address.

[0012] In another aspect of the present application, a memory system comprising the memory controller and the memory module of the above aspect is also provided; and a computer system comprising the memory of the above aspect is also provided.

[0013] In yet another aspect of the present application, a method for controlling access of a host controller to a memory module is also provided, the method comprising: receiving, by a central buffer, command / address signals from the host controller; determining, by the central buffer, whether the command / address signals comply with a permission management rule and configuring a buffer control command according to the determination result, such that the buffer control command indicates whether to limit access of the host controller to the memory module; and selectively limiting, by a data buffer, access of the host controller to the memory module according to the buffer control command; wherein the buffer control command comprises a plurality of fields having a time sequence relationship, and the central buffer configures a field in the second or later time sequence in the buffer control command according to the determination result.

[0014] According to the technical solution of the present application, time can be reserved for the central buffer to determine whether the C / A signal complies with the permission management rule after receiving the C / A signal, so that the system does not need to additionally increase the time for the central buffer to process the C / A signal. In addition, for the C / A signal that does not comply with the permission management rule, the technical solution of the present application can still send data to the host controller or send an indication of write success, which can avoid causing ECC error of the system. In addition, based on the received data or the indication of write success, an attacker sending the C / A signal that does not comply with the permission management rule will mistakenly think that illegal data has been written to the corresponding address in the memory module or mistakenly think that real data in the memory module has been obtained, so the technical solution of the present application can also confuse the attacker.

[0015] The above summary of the present application is thus meant to be illustrative only and not intended to be limiting in any way. Thus, those skilled in the art will appreciate that the summary is merely illustrative and is merely intended to describe some aspects of the present application and does not limit the scope of the claimed subject matter. This summary section is neither intended nor should it be construed to identify critical features or essential features of the claimed subject matter. Nor does it limit the scope of the claimed subject matter in any way. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other features of the present application will become more fully understood from the following detailed description, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several embodiments of the application and are not to be considered limiting of its scope, the application will be described with additional specificity and detail through the use of the accompanying drawings.

[0017] Figure 1 A memory system according to one embodiment of the present application is shown;

[0018] Figure 2 A central buffer according to one embodiment of the present application is shown;

[0019] Figure 3 A buffer control command according to one embodiment of the present application is shown;

[0020] Figure 4 A data buffer according to one embodiment of the present application is shown;

[0021] Figure 5 A method for controlling access of a host controller to a memory module according to one embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify

[0023] The inventors of the present application have found that for existing memory systems, when processing a received C / A signal, the central buffer needs to wait for the result of determining whether the C / A signal complies with the authority management rule before deciding how to process the C / A signal. Limited by the computing power, the complexity of the authority management rule, and the manufacturing process of the chip, and other factors, the determination of whether the C / A signal complies with the authority management rule can not be completed within the time period originally set for the central buffer to process the C / A signal, and therefore the time for the central buffer to process the C / A signal can need to be increased. This means that the settings of the entire system need to be adjusted, and can affect the data read / write performance of the memory system.

[0024] In addition, for existing memory systems, in some cases, the memory controller will mask the C / A signal that does not comply with the authority management rule or convert it into an invalid signal, so that after issuing the C / A signal, the host controller will not receive any indication of reading data or successfully writing data, which can cause the error checking and correction (ECC) function of the host controller to fail. In addition, in some cases, in order to meet the ECC requirement, the memory controller can alternatively regenerate a new C / A signal for the C / A signal that does not comply with the authority management rule, but given the limited number of address bits, the newly generated C / A signal can be positioned to other protected data segments, thereby causing unintended operations.

[0025] Embodiments of the present application disclose a memory controller, which can be applied to Figure 1 The memory system 100 shown in FIG. 1 will be taken as an example below to describe the memory controller of the present application in detail.

[0026] As shown in FIG. 1, the memory system 100 includes a host controller 110, a memory controller 120, and a memory 130. Figure 1As shown, the memory system 100 includes a memory module 102, which in this embodiment is configured as a memory module, for storing data. In some embodiments, the memory module 102 can be a memory module that conforms to JEDEC Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM) standards, such as including JEDEC DDR, DDR2, DDR3, DDR4, DDR5, and other double data rate memory standards. In addition, the memory module 102 can also be an internal memory that conforms to other standards or protocols, such as RAMBUS internal memory, or a memory that conforms to future memory standards or protocols. In some embodiments, the memory module 102 can include volatile memory (such as random access memory), non-volatile memory (such as flash memory, such as NAND or NOR flash memory), or a combination of both. In other embodiments, the memory module 102 can also be a new type of memory manufactured using different production processes, including but not limited to: magnetoresistive memory, phase change memory, resistive memory, semi-floating gate memory, or any other type of memory. It is noted that Figure 1 For example only, in other embodiments, the memory module can also include only one bank, or each bank can include more than two memory units, and the number of memory units in each bank can be the same or different. In addition, it is noted that the memory module 102 described herein can be one memory die, or can include two or more memory dies.

[0027] Further, the memory array or memory die included in the memory module 102 can be configured using various suitable interconnect structures. For example, multiple memory dies can be configured in parallel to form a memory module; alternatively, multiple memory dies can also be configured using a multi-level interconnect structure (such as two levels). For example, one or more memory dies can be configured as a first level of storage, while another one or more memory dies can be configured as a second level of storage, providing different levels of storage. The lower level second storage level can interact with the outside of the memory module as a whole through the first level of storage.

[0028] As Figure 1As shown, the memory system 100 further includes a memory controller 104 having a central buffer (RCD) 106. Specifically, the central buffer 106 is coupled between a host controller 110 and the memory modules 102, which can receive a Command / Address (C / A) signal including an access command and an access address from the host controller 110. For example, the C / A signal can include a data storage address (i.e., an access address) in the memory modules 102 and a command to access (e.g., read or write) the access address. Further, the central buffer 106 can provide the received C / A signal to the memory modules 102, so that the memory modules 102 can perform a corresponding data access operation according to the C / A signal. For a memory system complying with the DDR3, DDR4 or DDR5 standard, the central buffer 106 can be integrated in a register clock driver (RCD). Accordingly, the central buffer 106 is coupled between the host controller 110 and the memory modules 102 through a C / A bus to receive the C / A signal from the host controller 110 and provide the received C / A signal to the memory modules 102. For example, for a memory system complying with the DDR4 standard, the C / A bus can include pins A0-A17, pins BG0-BG1 and / or pins BA0-BA1. Among them, the pins BG0-BG1 are used to determine which memory bank group (Memory Bank Group) in the memory modules 102 is processed, e.g., written or read; the pins BA0-BA1 are used to determine which memory bank (Memory Bank) in the memory modules 102 is processed; and the pins A0-A17 are used to address and determine which memory cell in a memory bank is processed. In addition, the inputs of the four pins A16 (RAS_n), A15 (CAS_n) and A14 (WE_n) and ACT_n can be used to determine the input data access command, such as a read command, a write command and other predefined control commands.

[0029] The central buffer 106 includes a main signal path A coupled between a receiving side (DCA side) and an output side (QCA side) of the C / A bus and a branch signal path B coupled to the main signal path A. On the main signal path A, the central buffer 106 is configured to pass the C / A signal to the memory modules 102. A verification module 112 is coupled on the branch path B to determine whether each C / A signal complies with the authority management rule and configure a buffer control command (as described in detail below) according to the determination result.

[0030] In some embodiments, the verification module 112 can determine whether each C / A signal complies with the permission management rules according to the identity source information of each C / A signal. For example, for C / A signals sent by the master controller 110, each C / A signal has a corresponding identity source, i.e., a signal or command sent by a specific process or program according to the data processing needs. In one embodiment, the computer system can execute multiple processes, such as process 1, process 2, process 3,..., and process n, and a C / A signal can be a signal sent by a specific process (e.g., process 3) for writing data to a specific memory address or reading data from a specific memory address. In another embodiment, for a computer system, it can execute processes or programs related to multiple users, such as user 1, user 2, user 3,..., and user n, and a C / A signal can be a signal sent by a process or program logged in by a specific user (e.g., user 3), i.e., the source of the C / A signal is the process or program related to the specific user. Accordingly, when sending a C / A signal, the master controller 110 sends the corresponding identity authentication information for identifying the source of each C / A signal. In one embodiment, the master controller 110 can send the identity authentication information of the process source of each C / A signal, such as the process ID (e.g., PID) of the process, when sending each C / A signal. In another embodiment, the master controller 110 can send the identity authentication information of the user source of each C / A signal, such as the user ID of the user, when sending each C / A signal. In yet another embodiment, the C / A signal can also have other types of sources, such as each C / A signal can come from different CPU cores (e.g., multiple CPU cores included in a multi-core CPU), and the master controller 110 can send the identity authentication information of the CPU core source of each C / A signal when sending each C / A signal. It can be understood that one or more types of the foregoing identity authentication information can be sent together with the C / A signal.

[0031] For the branch signal path B of the central buffer 106, the verification module 112 thereon is coupled to the main signal path A of the C / A signals to receive the C / A signals transmitted on the C / A bus and the identity authentication information for identifying the source (e.g. process source, user source, etc.) of each C / A signal. The verification module 112 can perform real-time interception on the C / A signals transmitted on the C / A bus, i.e. can extract the access command, the access address and the corresponding identity authentication information included in the C / A signals. In addition, the verification module 112 can store or receive from outside the permission management rules. In some embodiments, the permission management rules can include the access command type allowed for each identity authentication information and / or the access address range of the storage module 102 allowed. The verification module 112 can compare the identity authentication information corresponding to each C / A signal, the access command and / or the access address included therein with the permission management rules to determine whether each C / A signal complies with the permission management rules.

[0032] For example, in some embodiments where the memory system 100 is configured to manage each C / A signal based on the process origin of each C / A signal, the host controller 110 sends the process identification information, such as a process ID, of each C / A signal along with each C / A signal. For example, the memory system 100 includes three processes: process 1, process 2, and process 3, and the host controller 110 sends the process ID that indicates the process origin of each C / A signal along with each C / A signal. In one such embodiment, the permission management rules stored by or received by the verification module 112 include the types of access commands allowed and the ranges of access addresses allowed for each process ID. The verification module 112 compares the access command and the access address included in a C / A signal from a particular process with the permission management rules. For example, Table 1 lists several possible cases of comparing the access command and the access address included in a C / A signal with the permission management rules based on the process origin information of the C / A signal according to one embodiment. Referring to Table 1 for a C / A signal from process 1, if the access command included in the C / A signal from process 1 is a read command and the access address falls within the range of the first to third memory cells of the first memory sub-module, the C / A signal is determined to comply with the permission management rules. Otherwise, if the access command included in the C / A signal from process 1 is not a write operation, the C / A signal is determined to not comply with the permission management rules. Referring to Table 1 for a C / A signal from process 2, if the access address included in the C / A signal from process 2 does not fall within the range of the first to fifth memory cells of the third memory sub-module, the verification module 112 determines that the C / A signal does not comply with the permission management rules. Similarly, the permission management rules can not include any permission management rules for a process, the memory system 100 can be configured to not have any permission management rules for a process, indicating that the process is allowed to access any memory address or that the process is not allowed to access any memory address. In this embodiment, no permission management rules are provided for process 3, indicating that process 3 is not allowed to access any memory address.

[0033] Table 1: Comparing a C / A signal with permission management rules based on the process origin information of the C / A signal

[0034]

[0035] Those skilled in the art can understand that, in other embodiments, the memory system 100 can also be configured to manage each C / A signal for other types of identity sources of the C / A signals, such as managing each C / A signal for user sources of the C / A signals, managing each C / A signal for different CPU cores sending each C / A signal, and the like, without limitation. In addition, those skilled in the art can also understand that the permission management rules stored by or received from the outside by the verification module 112 can only include the types of access commands allowed for each identity source or the ranges of access addresses allowed to be accessed, and the verification module 112 only determines whether the type of command included in each C / A signal is consistent with the type of command allowed for the corresponding identity source included in the permission management rules, or whether the access address included in each C / A signal falls within the range of access addresses allowed for the corresponding identity source included in the permission management rules, without limitation.

[0036] In addition, those skilled in the art can understand that the memory system 100 can also manage each C / A signal only for the identity sources of the C / A signals, without considering the types of access commands and the access addresses included in the C / A signals. For example, in one embodiment, the memory system 100 can be configured to allow all C / A signals from the process 1 and the process 3 to perform any access for any address, and not allow all C / A signals from the process 2 to perform any access. In such an embodiment, upon receiving a C / A signal, the verification module 112 can only identify the identity source information corresponding to the C / A signal, and no longer identify and determine the type of access command and the access address included in the C / A signal. For example, if the verification module 112 identifies that a C / A signal is from the process 1 or the process 3, the verification module 112 directly determines that it complies with the permission management rules; if the verification module 112 identifies that a C / A signal is from the process 2, the verification module 112 directly determines that it does not comply with the permission management rules.

[0037] Figure 2 An exemplary structure of a central buffer 200 according to one embodiment is shown, which can be applied to various memory systems, such as Figure 1 the memory system 100 shown. As Figure 2 shown, the central buffer 200 includes a verification module 202, which further includes an identification module 204, a management module 206, a rule module 208, and an optional configuration module 210.

[0038] The identification module 204 is coupled to the main signal path A of the C / A bus to receive the C / A signals transmitted on the C / A bus. The identification module 204 can perform real-time interception on the C / A signals transmitted on the C / A bus, i.e., can extract the access commands and / or access addresses included in the C / A signals. In some embodiments, the identification module 204 can selectively extract the access commands and / or access addresses included in the C / A signals according to the permission management rules used by the management module 206. For example, when the permission management rules used by the management module 206 only include the types of access commands allowed for each identity authentication information, the identification module 204 can only extract the access commands in the C / A signals without extracting the access addresses; when the permission management rules used by the management module 206 include both the types of access commands allowed for each identity authentication information and the ranges of access addresses allowed for each identity authentication information, the identification module 204 can extract both the access commands and the access addresses in the C / A signals. In addition, the identification module 204 can also be configured to extract both the access commands and the access addresses included in the C / A signals, but selectively send the extracted access commands and / or access addresses to the management module 206 for judgment of whether they comply with the permission management rules, which is not limited in the present application.

[0039] In some embodiments, the identification module 204 can extract the access addresses and / or access commands included in each C / A signal and send the access addresses and / or access commands extracted from each C / A signal to the management module 206 in real time. In other words, the identification module 204 can send the extracted access commands and / or access addresses to the management module 206 immediately after intercepting each C / A signal.

[0040] In some embodiments, the identification module 204 also receives the identity authentication information corresponding to each C / A signal sent by the main controller and sends the identity authentication information to the management module 206 for subsequent judgment. In some embodiments, the identity authentication information corresponding to each C / A signal sent by the main controller is the ID (e.g., PID) of a process. In such embodiments, the identification module 204 can identify the ID from the signal sent by the main controller and send the ID to the management module 206 for subsequent judgment. Similarly, for the sources of other types of C / A signals (e.g., user sources, main controller core sources), the identification module 204 can also identify the corresponding identity authentication information from the signal sent by the main controller and send the identity authentication information to the management module 206 for subsequent judgment.

[0041] The management module 206 is coupled to the identification module 204 to receive the access command and / or access address and corresponding identity authentication information sent by the identification module 204, and is also coupled to the rule module 208 to receive the permission management rules stored therein. The management module 206 can compare the received access command and / or access address and corresponding identity authentication information with the permission management rules to determine whether each C / A signal complies with the permission management rules, for example, as described above in connection with Table 1. After generating the determination result, the management module 206 configures a buffer control command according to the determination result and sends the buffer control command to the data buffer through a data buffer command (BCOM) channel, as described below.

[0042] The rule module 208 can include a non-volatile storage element that stores the permission management rules required by the management module 206 for determination. The rule module 208 is coupled to the management module 206 to provide the permission management rules thereto. Optionally, the rule module 208 can also be coupled to the identification module 204 to selectively listen to each C / A signal (for example, selectively extract the access command or access address included in the C / A signal, or extract both the access command and the access address) according to the current permission management rules, as described above. Optionally, the identification module 204 can also send the extracted access command and / or access address and corresponding identity authentication information to the rule module 208, so that the rule module 208 selects a suitable set of permission management rules from the multiple sets of permission management rules stored therein and provides the selected set of permission management rules to the management module 206.

[0043] In some embodiments, the permission management rules can be directly stored in the rule module 208 in advance (for example, directly stored in the rule module 208 by an initial user before the entire memory system is operated), so that the configuration module 210 can be omitted.

[0044] In some embodiments, the configuration module 210 can be provided, which is coupled to the rule module 208 to pre-configure or dynamically configure the permission management rules stored in the rule module 208. In one embodiment, the permission management rules stored in the rule module 208 can be pre-configured, i.e., the permission management rules of the rule module 208 are configured by the configuration module 210 before the entire memory system (for example, the memory system 100 shown in the figure) is operated. In another embodiment, the permission management rules stored in the rule module 208 can be dynamically configured, i.e., the permission management rules of the rule module 208 are dynamically configured by the configuration module 210 during the operation of the entire memory system (for example, the memory system 100 shown in the figure) according to the operating conditions. Figure 1 Figure 1

[0045] ​​In some implementations, the configuration module 210 can be coupled to the main controller (e.g., Figure 1 The main controller 110 allows users to pass configuration data to the configuration module 210 to configure permission management rules. In some embodiments, the configuration module 210 may be coupled to an external controller (in...). Figure 2 (Not shown in the image, the external controller may include, for example, a user's computer, mobile phone, tablet computer, etc., which are not limited in this application). The configuration data can be transmitted to the configuration module 210 through the external controller to configure the permission management rules.

[0046] In some implementations, configuration module 210 may store multiple sets of configuration data for permission management rules of configuration rule module 208, and configuration module 210 may be coupled to the main controller (e.g., as described above). Figure 1 The main controller 110 or an external controller receives a configuration instruction, which can select a set of preset configuration data from multiple sets of stored preset configuration data to configure the permission management rules of the rule module 208.

[0047] In some implementations, the configuration module 210 can automatically configure the permission management rules of the rule module 208. In one implementation, the configuration module 210 can store multiple sets of preset configuration data for configuring the permission management rules of the rule module 208, and the configuration module 210 also has different application conditions for storing each set of preset configuration data. In a memory system (e.g., Figure 1 During the operation of the memory system 100 shown, the configuration module 210 can automatically apply different preset configuration data under different application conditions to achieve automatic dynamic configuration of permission management rules. For example, the configuration module 210 may include three sets of preset configuration data for a certain process 1, wherein preset configuration data A does not restrict any C / A signals from process 1, preset configuration data B prohibits write commands from process 1, and preset configuration data B simultaneously prohibits both write and read commands from process 1. The configuration module 210 initially applies preset configuration data A. When the frequency or number of times process 1 accesses the memory module exceeds a certain threshold (e.g., more than 5 accesses within one minute), it applies (e.g., a stricter) preset configuration data B. After the number or frequency of access commands and / or access addresses from process 1 that do not match preset configuration data B exceeds a predetermined value, it applies another (e.g., the strictest) preset configuration data C. In other words, the configuration module 210 can adjust the configuration data applied to these processes according to the historical access data of C / A signals from different processes.

[0048] Back Figure 1After determining whether the C / A signal conforms to the access control rules, the central buffer 106 configures buffer control commands based on the determination result. Specifically, this can be done by the management module in the central buffer (e.g., in conjunction with the attached...). Figure 2 The described management module 206) configures buffer control commands based on the judgment result.

[0049] Figure 3 Two buffer control commands 3001 and 3002, transmitted via a BCOM channel according to one embodiment, are illustrated. These commands correspond to two C / A signals received by the central buffer; for example, buffer control command 3001 corresponds to a first C / A signal received at a first time point, and buffer control command 3002 corresponds to a second C / A signal received at a second time point after the first time point. Figure 3 As shown, each buffer control command has multiple fields, such as write / read field 302, data field 304, checksum field 306, and any other fields that can be configured according to actual needs. Write / read field 302 indicates whether the C / A signal includes a read or write command, data field 304 transmits the necessary data, and checksum field 306 is for verification purposes. These fields have a timing relationship, for example... Figure 3 As shown, for buffer control command 3001, the write / read field 3021 is sent in the first time period t1, the data field 3041 is sent in the second time period t2, and the parity field 3061 is sent in the third time period t3. For more information on the fields of the buffer control command, please refer to the relevant definitions in memory standards such as DDR3, DDR4, or DDR5.

[0050] It can be seen that using the BCOM channel to send buffered control commands containing judgment results not only utilizes the redundant or reserved information sending capabilities of the BCOM channel, but also avoids modifying the hardware structure of the memory system, thus improving the compatibility of the permission management mechanism of this application.

[0051] After receiving the C / A signal, the central buffer (e.g.) Figure 2 The central buffer 200 shown in the figure will send data to the data buffer (e.g., below) through the BCOM channel. Figure 4 The data buffer 400 shown sends buffer control commands, and the data buffer controls the storage module (e.g., according to the buffer control commands) to control the storage module (e.g., ...). Figure 1 The storage module 102 shown in the figure) and the main controller (e.g. Figure 1The central buffer can configure the write / read field 302 according to the command type included in the C / A signal, indicating that the data buffer sends data in the storage module to the host controller (e.g., the command included in the corresponding C / A signal is a read command) or that the data buffer sends data from the host controller to the storage module (e.g., the command included in the corresponding C / A signal is a write command).

[0052] According to one embodiment of the present application, when the central buffer determines that the C / A signal does not comply with the permission management rule, the central buffer can configure the buffer control command accordingly, so that the buffer control command indicates that the data buffer restricts the access of the host controller to the storage module. In some embodiments, one field in the buffer control command can be configured to reserve one bit of data, which can be configured to have different values according to the determination result of whether the C / A signal complies with the permission management rule. For example, when the central buffer determines that the corresponding C / A signal complies with the permission management rule, the reserved one bit of data can be configured to have a "0" value; when the central buffer determines that the corresponding C / A signal does not comply with the permission management rule, the reserved one bit of data can be configured to have a "1" value.

[0053] In one embodiment, the central buffer is configured to configure the field in the second or later timing of the buffer control command corresponding to the C / A signal according to the determination result of whether the C / A signal complies with the permission management rule, for example, in the buffer control command 3001 shown in Figure 3 In the buffer control command 3001, the central buffer is configured to configure the data field 3041 or the check field 3061 according to whether the corresponding C / A signal complies with the permission management rule; in the buffer control command 3002, the central buffer is configured to configure the data field 3042 or the check field 3062 according to whether the corresponding C / A signal complies with the permission management rule. The advantage of this is that the central buffer can be given time to determine whether the C / A signal complies with the permission management rule. For example, in the buffer control command 3001 shown in Figure 3 In the buffer control command 3001 shown, after receiving the corresponding C / A signal, the central buffer can determine whether the corresponding C / A signal complies with the permission management rule during the first time period t1 of sending the write / read field 3021, and configure the data field 3041 sent in the second time period t2 or the check field 3061 sent in the third time period t3 accordingly. In one embodiment, the central buffer is configured to configure the field in the last timing of the buffer control command according to whether the C / A signal complies with the permission management rule, for example, in the buffer control command 3002 shown in Figure 3The illustrated buffer control command 3001, the central buffer is configured to configure the check field 3061 according to whether the C / A signal complies with the permission management rule, so that the central buffer can use the first time period t1 for sending the write / read field 3021 and the second time period t2 for sending the data field 3041 to judge whether the C / A signal complies with the permission management rule, so as to maximize the time reserved for the central buffer to judge whether the corresponding C / A signal complies with the permission management rule.

[0054] According to another embodiment of the present application, when the central buffer judges that the C / A signal does not comply with the permission management rule, the central buffer can also modify the fields in the buffer control command accordingly, so that the data buffer cannot parse the modified buffer control command, and thus the data buffer cannot perform subsequent operations, so as to protect the data in the memory from being maliciously read or protect the memory from being maliciously written with data. For example, in Figure 3 In one such embodiment, after judging that the C / A signal corresponding to the buffer control command 3001 does not comply with the permission management rule, the central buffer is configured to modify the fields therein to all 0 or all 1, for example, modify the data field 3041 and / or the check field 3061 to all 0 or all 1. The modified buffer control command 3001 cannot be parsed by the data buffer, so the data buffer cannot perform subsequent operations, so as to protect the data in the memory from being maliciously read or protect the memory from being maliciously written with data. Similar to the embodiments discussed above, after judging that a C / A signal does not comply with the permission management rule, the central buffer can be configured to modify the field in the buffer control command that is in the second or later timing, so as to reserve time for the central buffer to judge whether the C / A signal complies with the permission management rule. In one embodiment, the central buffer is configured to modify the field in the buffer control command that is in the last timing according to whether the C / A signal complies with the permission management rule, so as to maximize the time reserved for the central buffer to judge whether the corresponding C / A signal complies with the permission management rule.

[0055] Returning to Figure 1 , the memory controller 104 further includes a data buffer (DB) 108 coupled between the storage module 102 and the host controller 110 to interact data therebetween. For example, via the data buffer 108, target data stored in the storage module 102 can be read out and sent to the host controller 110; or, via the data buffer 108, target data received from the host controller 110 can be written into the corresponding storage unit in the storage module 102. The data buffer 108 is coupled to the central buffer 106 through the BCOM channel to receive the buffer control command (e.g. Figure 3The buffer control commands 3001 and 3002 shown control the data exchange between the storage module 102 and the main controller 110, which will be described in detail below. The memory controller 104 may include one or more data buffers 108 (e.g., in...). Figure 1 In the middle, there are 4 data buffers 108), each data buffer 108 is coupled to one or more corresponding storage submodules (e.g., in Figure 1 In this application, each data buffer 108 is coupled to a corresponding storage submodule. It is understood that this application does not limit the number of data buffers 108 (e.g., including fewer than 4 data buffers or more than 4 data buffers, such as 8, 9 or 10 data buffers), nor does it limit the number of storage submodules coupled to each data buffer 108.

[0056] Figure 4 A data buffer 400 according to one embodiment is shown, which can be used for, for example... Figure 1 In the memory system 100 shown. For example... Figure 4 As shown, the data buffer 400 includes a buffer control module 402 coupled to the data buffer path DQ and coupled to the BCOM channel, and a bypass data module 404 coupled to the buffer control module 402.

[0057] Buffer control module 402 is coupled to the BCOM channel to receive data from the central buffer (e.g., Figure 1 The central buffer 106 shown Figure 2 The central buffer 200 shown receives buffer control commands (e.g., Figure 3 The buffer control commands 3001 and 3002 are shown. The buffer control module 402 is configured to selectively transfer data between the main controller and the storage module or between the main controller and the bypass data module 404 according to the buffer control commands, as described below.

[0058] The bypass data module 404 has a data storage function configured to store meaningless data, store write data from the host controller, and / or store read data from the storage module. When the buffer control command received by the buffer control module 402 indicates that the C / A signal from the host controller complies with the authority management rule, the bypass data module 404 can not operate, such that the buffer control module 402 controls the read data from the storage module at the corresponding address according to the access address in the C / A signal to be sent to the host controller, or the corresponding write data according to the access address in the C / A signal to be written to the corresponding address in the storage module. Differently, when the buffer control command received by the buffer control module 402 indicates that the C / A signal from the host controller does not comply with the authority management rule, the buffer control module 402 can send the data (e.g., meaningless data as described below) stored in the bypass data module 404 to the host controller or write the data from the host controller to the bypass data module 404.

[0059] In one embodiment, the bypass data module 404 stores meaningless data, such as a set of meaningless codes, a set of randomly generated codes, or any data that does not pose a threat to the security of the system. When the buffer control command received by the buffer control module 402 indicates that the C / A signal from the host controller includes a read command and the C / A signal does not comply with the authority management rule, the data buffer 400 no longer sends the read data from the storage module to the host controller, but instead sends the meaningless data stored in the bypass data module 404 to the host controller. In this way, the host controller can still obtain the returned read data (i.e., the meaningless data stored in the bypass data module 404) even if the issued read signal does not comply with the authority management rule. Of course, the returned read data is not valid data. In this way, the data in the storage module can be protected from being accessed by illegal programs, and the ECC error of the host controller can also be avoided. In addition, the illegal program that sends the C / A signal that does not comply with the authority management rule will mistakenly believe that it has obtained the read data in the storage module after obtaining the meaningless data, thus avoiding the illegal program from continuing to access the storage module after the access fails.

[0060] In one embodiment, the meaningless data can be pre-stored in the bypass data module 404 by a user before the entire system is running. In one embodiment, the meaningless data can be provided to the bypass data module 404 by other components of the memory system. For example, the central buffer can be configured to generate meaningless data, and the bypass data module 404 can be coupled to the central buffer to receive the meaningless data generated thereby. In one embodiment, the meaningless data can be generated by the data buffer 400, e.g., the data buffer 400 can optionally include a meaningless data generation module 406 configured to generate meaningless data and send the meaningless data to the bypass data module 404. The meaningless data generation module 406 can be coupled to or included in the bypass data module 404. In one embodiment, the meaningless data is random code data generated according to a random seed, and the data buffer 400 can pre-store the random seed or receive the random seed from other components of the memory system, e.g., the meaningless data generation module 406 can receive the random seed from the central buffer.

[0061] In another embodiment, the bypass data module 404 can be configured to selectively store write data from the host controller. When the buffer control module 402 receives a buffer control command indicating that the C / A signal from the host controller includes a write command and the C / A signal does not comply with the permission management rule, the data buffer 400 no longer writes the write data from the host controller corresponding to the access address included in the C / A signal to the storage module, but instead writes the write data to the bypass data module 404. In this way, the host controller can still obtain an indication of write data success even though the write signal issued does not comply with the permission management rule, so that both the storage module is protected from being written with illegal data and an ECC error is not caused for the host controller. In addition, an attacker sending a C / A signal that does not comply with the permission management rule can be misled into thinking that illegal data has been written to the corresponding address in the storage module, so such an embodiment can also confuse the attacker.

[0062] In yet another embodiment, when the memory system processes a read command that complies with the access control rule, in addition to sending the corresponding read data to the host controller as usual, the read data can also be stored in the bypass data module 404. In this way, when the buffer control module 402 subsequently receives a buffer control command that indicates that the C / A signal from the host controller includes a write command and that the C / A signal does not comply with the access control rule, the data buffer 400 does not write the write data from the host controller corresponding to the C / A signal to the storage module, but instead writes the read data previously stored in the bypass data module 404 to the storage module again, so that there is actually no change in the data in the storage module. In this way, the host controller can still obtain an indication of the success of the write data even if the write signal sent does not comply with the access control rule, so that the storage module can be protected from being written with illegal data and the host controller can not be caused to have an ECC error. In addition, an attacker sending a C / A signal that does not comply with the access control rule can mistakenly believe that illegal data has been written to the corresponding address in the storage module, so that such an embodiment can also confuse the attacker. The read data stored in the bypass data module 404 can correspond to different addresses in the storage module, for example, the first read data stored in the bypass data module 404 corresponds to a first address in the storage module, the second read data stored in the bypass data module 404 corresponds to a second address in the storage module, the third read data stored in the bypass data module 404 corresponds to a third address in the storage module, and so on. In this way, for a subsequently received C / A signal that includes a write command and does not comply with the access control rule, the buffer control module 402 will also send the corresponding read data stored based on the address information included in the C / A signal to the corresponding address. For example, if the subsequently received C / A signal that includes a write command and does not comply with the access control rule includes address information corresponding to the first address, the buffer control module 402 will send the read data stored corresponding to the first address to the first address of the storage module.

[0063] Figure 5 A method 500 for controlling access of a host controller to a storage module according to an embodiment of the present application is shown. The method 500 can be performed by, for example Figure 1 the memory system 100, Figure 2 the central buffer 200, and Figure 4 the data buffer 400.

[0064] As shown in Figure 5As shown, the method 500 can include: step 502, the central buffer receiving the command / address signal from the host controller; step 504, the central buffer judging whether the command / address signal complies with the authority management rule and configuring a buffer control command according to the judging result, so that the buffer control command indicates whether to restrict the access of the host controller to the storage module; and step 506, the data buffer selectively restricting the access of the host controller to the storage module according to the buffer control command.

[0065] In some embodiments, step 502 can include the main signal path of the central buffer receiving the command / address signal from the host controller and sending the command / address signal to be transmitted on the main signal path to the branch signal path of the central buffer, and step 504 can include judging whether the command / address signal complies with the authority management rule on the branch signal path and configuring a buffer control command according to the judging result. In some such embodiments, the method 500 further includes sending the buffer control command from the branch signal path to the data buffer via a data buffer command channel.

[0066] In some embodiments, step 504 can include: identifying the access command, the access address and / or the identity source information in the command / address signal; receiving the authority management rule; and judging whether the command / address signal complies with the authority management rule based on the access command, the access address and / or the identity source information and configuring a buffer control command according to the judging result. In some embodiments, the authority management rule can be pre-configured or dynamically configured.

[0067] In some embodiments, the buffer control command includes a plurality of fields, one of which can be configured to reserve one bit of data, which can be configured to have different values according to the judging result of whether the C / A signal complies with the authority management rule, so that the buffer control command can indicate whether to restrict the access of the host controller to the storage module according to the reserved one bit of data.

[0068] In some embodiments, the fields included in the buffer control command have a timing relationship, the central buffer is configured to configure the field in the second or later timing and preferably the field in the last timing in the buffer control command according to the judging result of whether the C / A signal complies with the authority management rule, as described above.

[0069] In some embodiments, for step 504, the command / address signal includes identity authentication information, the authority management rule includes the access command type allowed for each identity authentication information and / or the access address range of the storage module allowed for each identity authentication information, and the central buffer can judge whether each command / address complies with the authority management rule accordingly, as described above.

[0070] In some embodiments, step 506 further comprises, in response to the command / address signals including a read command and the command / address signals not complying with the permission management rule, the data buffer transmitting meaningless data stored by the data buffer to the host controller. In one such embodiment, method 500 can further comprise the data buffer generating the meaningless data, and optionally, further comprising the data buffer receiving a random seed from the central buffer and generating the meaningless data based on the random seed. In one such embodiment, method 500 can further comprise the data buffer receiving the meaningless data from the central buffer.

[0071] In some embodiments, step 506 further comprises, in response to the command / address signals including a write command and the command / address signals not complying with the permission management rule, the data buffer transmitting write data corresponding to the command / address signals into the data buffer.

[0072] In some embodiments, step 506 further comprises the data buffer storing read data from the memory module, and in response to the command / address signals including a write command and the command / address signals not complying with the permission management rule, controlling the transmission of the read data stored in the data buffer to the memory module. In some such embodiments, the stored read data corresponds to a first address in the memory module, step 506 further comprises, in response to the command / address signals including a write command and the command / address signals not complying with the permission management rule, and the command / address signals including address information corresponding to the first address, controlling the transmission of the stored read data to the first address of the memory module.

[0073] It should be noted that although several steps of the method for accessing the memory module, and several modules or sub-modules of the memory controller are mentioned in the foregoing detailed description, such partitioning is merely exemplary and not mandatory. Indeed, according to embodiments of the present application, the features and functionalities of two or more modules described above can be embodied in one module. Conversely, the features and functionalities of one module described above can be further partitioned to be embodied by a plurality of modules. In addition, the order of the steps described in the present application is not mandatory, and the order of execution can be adjusted as needed.

[0074] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements and steps, and the word "a" or "an" does not exclude a plurality. In the claims, the term "consisting of means "including and excluding only". In the claims, the term "consisting essentially of means "including and excluding any additional element or step that does not substantially affect the basic function of the claimed application. In the claims, any reference signs placed between parentheses shall have no influence on the scope of the claims. The application is not limited to the embodiments described above, but can vary and develop within the scope of the appended claims.

Claims

1. A memory controller coupled between a memory module and a main controller to control access to the memory module by the main controller, characterized in that, The memory controller comprises: a central buffer coupled to the host controller via a command / address bus to receive a command / address signal from the host controller, wherein the central buffer is configured to determine whether the command / address signal complies with an authority management rule and configure a buffer control command according to the determination result, so that the buffer control command indicates whether to restrict access of the host controller to the memory module; and a data buffer coupled to the central buffer via a data buffer command channel to receive the buffer control command, the data buffer being configured to selectively restrict access of the host controller to the memory module according to the buffer control command; wherein the buffer control command comprises a plurality of fields having a time sequence relationship, and the central buffer is configured to configure a field at a second or later time sequence in the buffer control command according to the determination result.

2. The memory controller of claim 1, wherein, The central buffer is configured to configure a field at a last time sequence in the buffer control command according to the determination result.

3. The memory controller of claim 1, wherein, The data buffer comprises: a bypass data module configured to store meaningless data; a buffer control module configured to, in response to the command / address signal comprising a read command and the command / address signal not complying with the authority management rule, control transmission of the meaningless data to the host controller.

4. The memory controller of claim 3, wherein, The bypass data module comprises a meaningless data generation module configured to generate the meaningless data.

5. The memory controller of claim 1, wherein, The central buffer comprises: a main signal path configured to receive the command / address signal from the host controller and provide the command / address signal to the memory module; a branch signal path coupled to the main signal path to receive the command / address signal, the branch signal path comprising a verification module configured to determine whether the command / address signal complies with the authority management rule and configure the buffer control command according to the determination result.

6. The memory controller of claim 5, wherein, The verification module is coupled to the data buffer via the data buffer command channel to send the buffer control command to the data buffer.

7. The memory controller of claim 5, wherein, The verification module comprises: an identification module coupled to the main signal path to receive the command / address signal, the identification module being configured to identify an access command, an access address and / or identity source information in the command / address signal; a management module coupled to the identification module to receive the access command, the access address and / or the identity source information in the command / address signal, the management module being configured to determine whether the command / address signal complies with the authority management rule based on the access command, the access address and / or the identity source information and configure the buffer control command according to the determination result; and a rule module storing the authority management rule, the rule module being coupled to the management module to provide the authority management rule to the management module.

8. The memory controller of claim 7, wherein, The verification module further comprises a configuration module coupled to the rule module, via which the permission management rule can be pre-configured or dynamically configured.

9. The memory controller of claim 1, wherein, The data buffer comprises: a bypass data module; a buffer control module, wherein the buffer control module is configured to, in response to the command / address signal comprising a write command and the command / address signal not complying with the permission management rule, control transmission of write data corresponding to the command / address signal into the bypass data module.

10. The memory controller of claim 1, wherein, The data buffer comprises: a bypass data module, the bypass data module being configured to store read data from the storage module; a buffer control module, wherein the buffer control module is configured to, in response to the command / address signal comprising a write command and the command / address signal not complying with the permission management rule, control transmission of read data stored in the bypass data module to the storage module.

11. The memory controller of claim 10, wherein, The read data corresponds to a first address in the storage module, the buffer control module is configured to, in response to the command / address signal comprising a write command and the command / address signal not complying with the permission management rule, and the command / address signal comprising address information corresponding to the first address, control transmission of the read data to the first address of the storage module.

12. A memory system, characterized by comprising: The memory system comprises the memory controller and the storage module according to any one of claims 1 to 11.

13. A method for controlling access of a host controller to a memory module, the method comprising: The method comprises: a central buffer receiving a command / address signal from the host controller; the central buffer judging whether the command / address signal complies with a permission management rule and configuring a buffer control command according to a result of the judgment, so that the buffer control command indicates whether to limit access of the host controller to the storage module; and a data buffer selectively limiting access of the host controller to the storage module according to the buffer control command; wherein the buffer control command comprises a plurality of fields having a time sequence relationship, and the central buffer configures a field in the last time sequence in the buffer control command according to the result of the judgment.

14. The method of claim 13, wherein, The central buffer configures a field in the last time sequence in the buffer control command according to the result of the judgment.

15. The method of claim 13, wherein, The data buffer stores meaningless data, and the method comprises, in response to the command / address signal comprising a read command and the command / address signal not complying with the permission management rule, the data buffer transmitting the meaningless data to the host controller.

16. The method of claim 15, wherein, The method further comprises the data buffer generating the meaningless data.

17. The method of claim 13, wherein, The method further comprises: a main signal path of the central buffer receiving the command / address signal from the host controller; sending the command / address signal transmitted on the main signal path to a branch signal path of the central buffer; judging whether the command / address signal complies with the permission management rule on the branch signal path and configuring the buffer control command according to a result of the judgment.

18. The method of claim 17, wherein, The method further comprises sending the buffer control command from the branch signal path to the data buffer through a data buffer command channel.

19. The method of claim 13, wherein, The central buffer determines whether the command / address signals comply with the permission management rule and configures the buffer control command according to the determination result, further comprising: identifying access commands, access addresses and / or identity source information in the command / address signals; receiving the permission management rule; and determining whether the command / address signals comply with the permission management rule based on the access commands, access addresses and / or identity source information and configuring the buffer control command according to the determination result.

20. The method of claim 13, wherein, The permission management rule can be pre-configured or dynamically configured.

21. The method of claim 13, wherein, The method comprises, in response to the command / address signals comprising a write command and the command / address signals not complying with the permission management rule, the data buffer transmitting write data corresponding to the command / address signals to the data buffer.

22. The method of claim 13, wherein, The method comprises: The data buffer stores read data from the storage module; in response to the command / address signals comprising a write signal and the command / address signals not complying with the permission management rule, the data buffer transmitting the stored read data to the storage module.

23. The method of claim 22, wherein, The read data corresponds to a first address in the storage module, and the method comprises, in response to the command / address signals comprising a write command and the command / address signals not complying with the permission management rule, and the command / address signals comprising address information corresponding to the first address, controlling the transmission of the read data to the first address of the storage module.

Images