Method of forming a semiconductor structure

By forming an initial mask layer and a core layer in the first and second device regions of the semiconductor structure, respectively, and using sidewall materials with similar etching selectivity, the problem of poor gate layer height consistency is solved, improving device reliability and performance and simplifying the process flow.

CN115719733BActive Publication Date: 2026-06-09SEMICON MFG INT (SHANGHAI) CORP +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Filing Date
2021-08-24
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

In existing technologies, the gate layer height of semiconductor structures is poorly consistent, resulting in poor performance. This is especially true in fin field-effect transistors and fully enclosed gate transistors, where inconsistent channel lengths lead to large differences in etching selectivity, affecting the reliability and performance of the devices.

Method used

An initial mask layer and a core layer are formed in the first device region and the second device region, respectively. Different mask layers are retained after being covered by sidewalls to ensure that the channel length of the first transistor is greater than that of the second transistor. Sidewall materials with similar material selectivity are used to reduce the difference in etching selectivity and improve the height consistency of the gate layer.

Benefits of technology

By optimizing the mask layer formation process, the gate layer high uniformity of the semiconductor structure is improved, the reliability and performance of the device are enhanced, the process flow is simplified, and damage and polymer residue during the etching process are reduced.

✦ Generated by Eureka AI based on patent content.

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Abstract

A method for forming a semiconductor structure comprises: providing a substrate, the substrate having a gate material layer formed thereon, the substrate comprising a first device region for forming a first transistor and a second device region for forming a second transistor, the first transistor having a channel length greater than the channel length of the second transistor; forming a discrete initial mask layer on the gate material layer in the first device region; after forming the initial mask layer, forming a discrete core layer on the gate material layer in the second device region; forming a sidewall covering the sidewall of the core layer and the sidewall of the initial mask layer; after forming the sidewall, removing the core layer, leaving the sidewall and the initial mask layer in the first device region as a first mask layer, and leaving the sidewall in the second device region as a second mask layer; and patterning the gate material layer into a first gate layer and a second gate layer using the first mask layer and the second mask layer as masks. The method can provide a better height consistency of the first gate layer and the second gate layer.
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