Electrostatic protection circuit of the chip

Abstract

The present application provides an electrostatic protection circuit for a chip. The chip includes a power pad and a ground pad. The electrostatic protection circuit includes: a monitoring unit connected between the power pad and the ground pad, having a first output terminal and a second output terminal, for generating a first trigger signal and a second trigger signal when there is an electrostatic pulse on the power pad; a first discharge transistor, whose control terminal is connected to the first output terminal, whose first end is connected to the power pad, and whose second end is connected to the ground pad, for discharging electrostatic charges to the ground pad under the trigger of the first trigger signal; a second discharge transistor, whose control terminal is connected to the second output terminal, whose first end is connected to the power pad, and whose second end is connected to the ground pad, for discharging electrostatic charges to the ground pad under the trigger of the second trigger signal. This solution can make the conduction of the two discharge transistors more uniform, thereby improving the discharge ability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to an electrostatic protection circuit for a chip. Background Art

[0002] Electrostatic charges exist everywhere. Without an electrostatic protection circuit, a chip will soon be damaged by electrostatic charges introduced for various reasons and will almost be fatally damaged.

[0003] Therefore, an electrostatic protection circuit is usually provided in a chip. The electrostatic protection circuit is used to timely discharge electrostatic charges and prevent the protected circuit from failing or even burning out due to the high voltage brought by the electrostatic charges. Summary of the Invention

[0004] This application provides an electrostatic protection circuit for a chip, aiming to provide an electrostatic protection circuit with adjustable electrostatic protection ability.

[0005] In a first aspect, this application provides an electrostatic protection circuit for a chip. The chip includes a power supply pad and a ground pad. The electrostatic protection circuit includes:

[0006] A monitoring unit, which is connected between the power supply pad and the ground pad, and has a first output terminal and a second output terminal, and is used to generate a first trigger signal and a second trigger signal when there is an electrostatic pulse on the power supply pad;

[0007] A first discharge transistor, whose control terminal is connected to the first output terminal, whose first end is connected to the power supply pad, and whose second end is connected to the ground pad, and is used to discharge electrostatic charges to the ground pad under the trigger of the first trigger signal;

[0008] A second discharge transistor, whose control terminal is connected to the second output terminal, whose first end is connected to the power supply pad, and whose second end is connected to the ground pad, and is used to discharge electrostatic charges to the ground pad under the trigger of the second trigger signal.

[0009] In one embodiment, the monitoring unit includes:

[0010] A monitoring capacitor, which has a first end and a second end;

[0011] A first resistor, which has a first end and a second end, and whose first end is connected to the second end of the monitoring capacitor to form the first output terminal of the monitoring unit;

[0012] A second resistor, which has a first end and a second end, and whose first end is connected to the second end of the first resistor to form the second output terminal of the monitoring unit.

[0013] In one embodiment, the resistance value of the second resistor is greater than that of the first resistor.

[0014] In one embodiment, the chip further includes a substrate, and the distance between the projection of the first discharge transistor on the substrate and the first projection of the power supply pad on the substrate is greater than the distance between the projection of the second discharge transistor on the substrate and the first projection.

[0015] In one embodiment, the first discharge transistor includes a first multi-finger structure, and the second discharge transistor includes a second multi-finger structure, wherein the first multi-finger structure and the second multi-finger structure are arranged adjacent to each other.

[0016] In one embodiment, the first end of the monitoring capacitor is connected to the power supply pad, and the second end of the second resistor is connected to the ground pad.

[0017] In one embodiment, both the first discharge transistor and the second discharge transistor are N-type transistors, and the substrate ends of the first discharge transistor and the second discharge transistor are connected to the ground pad.

[0018] In one embodiment, when there is an electrostatic pulse on the power supply pad, the charging rate of the first output terminal of the monitoring unit is greater than the charging rate of the second output terminal of the monitoring unit.

[0019] In one embodiment, the first end of the monitoring capacitor is connected to the ground pad, and the second end of the second resistor is connected to the power supply pad.

[0020] In one embodiment, both the first discharge transistor and the second discharge transistor are P-type transistors, and the substrate ends of the first discharge transistor and the second discharge transistor are connected to the power supply pad.

[0021] In one embodiment, when there is an electrostatic pulse on the power supply pad, the discharging rate of the first output terminal of the monitoring unit is greater than the discharging rate of the second output terminal of the monitoring unit.

[0022] In one embodiment, the monitoring unit further has a third output terminal, and the electrostatic protection circuit further includes:

[0023] A third discharge transistor, whose control terminal is connected to the third output terminal of the monitoring unit, whose first end is connected to the power supply pad, and whose second end is connected to the ground pad, for discharging electrostatic charges to the ground pad.

[0024] In one embodiment, the monitoring unit further includes:

[0025] A monitoring capacitor, which has a first end and a second end;

[0026] A first resistor, which has a first end and a second end, and whose first end is connected to the second end of the monitoring capacitor to form the first output terminal of the monitoring unit;

[0027] A second resistor, which has a first end and a second end, and whose first end is connected to the second end of the first resistor to form the second output terminal of the monitoring unit;

[0028] A third resistor, having a first end and a second end, wherein the first end of the third resistor is connected to the second end of the second resistor to form a third output terminal of the monitoring unit.

[0029] In one embodiment, the distance between the projection of the first discharge transistor on the substrate and the first projection of the power supply pad on the substrate is greater than the distance between the second projection of the second discharge transistor on the substrate and the first projection;

[0030] The distance between the projection of the third discharge transistor on the substrate and the projection of the power supply pad on the substrate is less than the distance between the second projection and the first projection.

[0031] In one embodiment, the first discharge transistor, the second discharge transistor, and the third discharge transistor are all N-type transistors.

[0032] The present application provides an electrostatic protection circuit for a chip. The monitoring unit has two output terminals, one of which is connected to the control of the first discharge transistor, and the other output terminal is connected to the control terminal of the second discharge transistor, so that the trigger signals of the two discharge transistors are different. By setting the magnitude of the trigger signal, the conduction rates of the two discharge transistors are adjusted, reducing the influence caused by different parasitic parameters on the different conduction rates of the two discharge transistors, making the conduction rates of the two discharge transistors similar, avoiding the failure of the transistor with a fast conduction rate due to excessive electrostatic discharge current, and improving the reliability of the electrostatic protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0034] Figure 1 It is a circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application;

[0035] Figure 2 It is a circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application;

[0036] Figure 3 For Figure 1 And Figure 2 It is a projection diagram on the substrate of the electrostatic protection circuit of the chip provided by the shown embodiment;

[0037] Figure 4 It is a circuit diagram of the electrostatic protection circuit of the chip provided by another embodiment of the present application;

[0038] Figure 5 It is a circuit diagram of the electrostatic protection circuit of the chip provided by another embodiment of the present application;

[0039] Figure 6 ForFigure 5 Projection view of the electrostatic protection circuit of the chip provided by the illustrated embodiment on the substrate;

[0040] Figure 7 Circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application;

[0041] Figure 8 Circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application;

[0042] Figure 9 Circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application;

[0043] Figure 10 Circuit diagram of the electrostatic protection circuit of the chip provided by an embodiment of the present application.

[0044] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and more detailed descriptions will be given hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0045] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other implementation manners of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0047] As Figure 1 shown, an embodiment of the present application provides an electrostatic protection circuit for a chip. The chip includes a power supply pad VDD and a ground pad GND. The internal circuit provided in the chip is located between the power supply pad VDD and the ground pad GND. The electrostatic protection circuit includes a monitoring unit 101 and a discharge transistor 102.

[0048] The monitoring unit 101 is provided with an output terminal N0. The output terminal N0 of the monitoring unit 101 is connected to the control terminal of the discharging transistor 102. The monitoring unit 101 is located between the power supply pad VDD and the ground pad GND. When the monitoring unit 101 detects an electrostatic pulse, a trigger signal is generated. The discharging transistor 102 is turned on under the trigger of the trigger signal, and the electrostatic charge is discharged from the power supply pad VDD to the ground pad GND.

[0049] Among them, the monitoring unit 101 includes a monitoring capacitor C0 and a monitoring resistor R0. The monitoring capacitor C0 and the monitoring resistor R0 are provided with a first end and a second end. The first end of the monitoring capacitor C0 is connected to the power supply pad VDD. The second end of the monitoring capacitor C0 is connected to the first end of the monitoring resistor R0. The second end of the monitoring resistor R0 is connected to the ground pad GND.

[0050] In an embodiment, the discharging transistor 102 is an N-type transistor. When an electrostatic pulse arrives, the impedance of the monitoring capacitor C0 becomes smaller, the voltage at the control terminal of the discharging transistor 102 rises, the discharging transistor 102 gradually turns on, and the electrostatic charge is discharged to the ground pad GND through the discharging transistor 102.

[0051] In an embodiment, as Figure 2 shown, the discharging transistor N0 is also provided with a substrate terminal. The substrate terminal of the discharging transistor N0 is connected to the ground pad GND, which can effectively reduce the influence of the latch-up effect.

[0052] As Figure 3 shown, in order to improve the electrostatic discharge ability, the discharging transistor 102 usually has a larger size. The discharging transistor 102 with a larger size usually adopts a multi-finger structure. For example, a 28-finger structure is adopted. The size of one finger structure is w = 10.5u and L = 0.15u. When an electrostatic pulse arrives, it is necessary to make the 28 finger structures turn on uniformly within a few hundred picoseconds. Once non-uniform conduction occurs in the 28 finger structures, for example, only 1 finger structure conducts first, then the first-conducting finger structure will discharge the electrostatic charge. Because the electrostatic charge is discharged, the rising speed of the electrostatic pulse on the power supply pad VDD is slowed down, which makes it more difficult or slower for other finger structures to conduct. And the discharging current passing through the first-conducting finger structure will become larger and larger, and then burn out the first-conducting finger structure. Usually, the first-conducting finger structure with the smallest parasitic parameters of the gate and drain conducts first, that is, non-uniform conduction will burn out one or several finger structures, resulting in the failure of the electrostatic protection circuit. And the larger the size of the transistor, the greater the risk of non-uniform conduction.

[0053] As Figure 4As shown in the figure, an embodiment of the present application provides an electrostatic protection circuit for a chip. The chip includes a power supply pad VDD and a ground pad GND. The internal circuit provided in the chip is located between the power supply pad VDD and the ground pad GND. The electrostatic protection circuit includes a monitoring unit 201, a first discharge transistor 202, and a second discharge transistor 203.

[0054] Among them, the monitoring unit 201 is provided with a first output terminal N1 and a second output terminal N2. The control terminal of the first discharge transistor 202 is connected to the first output terminal N1, and the control terminal of the second discharge transistor 203 is connected to the second output terminal N2.

[0055] The monitoring unit 201 is connected between the power supply pad VDD and the ground pad GND, and is used to generate a first trigger signal and a second trigger signal when there is an electrostatic pulse on the power supply pad VDD. The first end of the first discharge transistor 202 is connected to the power supply pad VDD, and the second end of the first discharge transistor 202 is connected to the ground pad GND. The first discharge transistor 202 is used to discharge the electrostatic charge to the ground pad GND under the trigger of the first trigger signal. The first end of the second discharge transistor 203 is connected to the power supply pad VDD, and the second end of the second discharge transistor 203 is connected to the ground pad GND. The second discharge transistor 203 is used to discharge the electrostatic charge to the ground pad GND under the trigger of the second trigger signal.

[0056] The parasitic parameters between the respective ends of the first discharge transistor 202 and the power supply pad VDD are different from the parasitic parameters between the respective ends of the second discharge transistor 203 and the power supply pad VDD. When an electrostatic pulse arrives, it will cause the conduction rates of the first discharge transistor 202 and the second discharge transistor 203 to be different. The monitoring unit 201 is provided with a first output terminal N1 and a second output terminal N2. The first trigger signal is output from the first output terminal N1, and the second trigger signal is output from the second output terminal N2. Among them, the amplitudes of the first trigger signal and the second trigger signal are different, so that the charging or discharging rate of the control terminal of the first discharge transistor 202 is different from the charging or discharging rate of the control terminal of the second discharge transistor 203, thereby making the conduction rate of the first discharge transistor 202 different from the conduction rate of the second discharge transistor 203 triggered by the second trigger signal.

[0057] If the conduction rate of the first discharge transistor 202 is less than that of the second discharge transistor 203 due to different parasitic parameters between the terminals of the transistor and the power supply pad VDD, the amplitude of the first trigger signal is made greater than that of the second trigger signal, so that the charging or discharging rate of the control terminal of the first discharge transistor 202 is greater than that of the control terminal of the second discharge transistor 203, thereby accelerating the conduction rate of the first discharge transistor 202, making the conduction rates of the first discharge transistor 202 and the second discharge transistor 203 close, and the static electricity charges flowing through the first discharge transistor 202 and the second discharge transistor 203 similar, which can avoid burning out of one of the discharge transistors after most of the static electricity charges flow through it due to different parasitic parameters of the two discharge transistors. Here, "close" can be understood as the same, or within a small allowable error range, for example, the deviation between the two is 0.1% etc.

[0058] Correspondingly, if the parasitic parameters make the conduction rate of the first discharge transistor 202 greater than that of the second discharge transistor 203, the amplitude of the first trigger signal can be set to be less than that of the second trigger signal, and the charging or discharging rates of the control terminals of the two transistors are controlled by the trigger signal to balance the conduction rates of the first discharge transistor 202 and the second discharge transistor 203, and the discharge currents of the two transistors can be balanced, thereby avoiding the failure of the transistor with a fast conduction rate due to excessive static electricity current and improving the reliability of the electrostatic protection circuit.

[0059] In the above technical solution, the monitoring unit 201 is provided with two output terminals, one of which is connected to the control of the first discharge transistor 202, and the other output terminal is connected to the control terminal of the second discharge transistor 203, so that the trigger signals of the two discharge transistors are different, and the conduction rates of the two discharge transistors are adjusted by setting the magnitudes of the trigger signals, reducing the influence of different conduction rates of the two discharge transistors caused by different parasitic parameters, making the conduction rates of the two discharge transistors close, avoiding the failure of the transistor with a fast conduction rate due to excessive static electricity current, and improving the reliability of the electrostatic protection circuit.

[0060] As Figure 5 shown, an embodiment of the present application provides an electrostatic protection circuit for a chip. The chip includes a power supply pad VDD and a ground pad GND, and the internal circuit provided in the chip is located between the power supply pad VDD and the ground pad GND. The electrostatic protection circuit includes a monitoring unit 201, a first discharge transistor MN1, and a second discharge transistor MN2.

[0061] Among them, the monitoring unit 201 includes a monitoring capacitor C1, a first resistor R1, and a second resistor R2. The monitoring capacitor C1, the first resistor R1, and the second resistor R2 all have a first end and a second end. The first end of the monitoring capacitor C1 is connected to the power supply pad VDD, the second end of the monitoring capacitor C1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the ground pad GND.

[0062] After the first end of the first resistor R1 is connected to the second end of the monitoring capacitor C1, a first output terminal N1 of the monitoring unit 201 is formed, which is used to be connected to the control terminal of the first discharge transistor MN1. After the first end of the second resistor R2 is connected to the second end of the first resistor R1, a second output terminal N2 of the monitoring unit 201 is formed, which is used to be connected to the control terminal of the second discharge transistor MN2.

[0063] In an embodiment, both the first discharge transistor MN1 and the second discharge transistor MN2 are N-type transistors. The voltage signal at the second end of the monitoring capacitor C1 is the first trigger signal, and the voltage signal at the second end of the first resistor R1 is the second trigger signal. When there is static charge on the power supply pad VDD, the impedance of the monitoring capacitor C1 becomes smaller, the voltages at the second end of the monitoring capacitor C1 and the second end of the first resistor R1 both rise, and the voltage amplitude at the second end of the monitoring capacitor C1 is greater than the voltage amplitude at the second end of the first resistor R1, that is, the amplitude of the first trigger signal is greater than the amplitude of the second trigger signal.

[0064] When there is a static pulse on the power supply pad VDD, the charging rate of the first output terminal N1 of the monitoring unit 201 is greater than the charging rate of the second output terminal N2 of the monitoring unit 201, so as to increase the conduction rate of the first discharge transistor MN1. When the conduction rate of the first discharge transistor MN1 is less than that of the second discharge transistor MN2 due to excessive parasitic parameters, the gap between the conduction rates of the first discharge transistor MN1 and the second discharge transistor MN2 can be reduced, avoiding the failure of the transistor with a fast conduction rate due to excessive static discharge current, and improving the reliability of the electrostatic protection circuit.

[0065] When the amplitude of the first trigger signal is greater than the amplitude of the second trigger signal, due to the parasitic parameters of the device, the conduction rate of the first discharge transistor MN1 is less than that of the second discharge transistor MN2, and the trigger signal makes the conduction rate of the first discharge transistor MN1 greater than that of the second discharge transistor MN2, which can ensure that the conduction rates of the first discharge transistor MN1 and the second discharge transistor MN2 are close, so that the discharge current of the first discharge transistor MN1 is similar to the discharge current of the second discharge transistor MN2, avoiding the failure of the transistor with a fast conduction rate due to excessive static current.

[0066] In one embodiment, the first discharge transistor and the second discharge transistor share a substrate. The distance between the projection of the first discharge transistor MN1 on the substrate and the projection of the power supply pad VDD on the substrate is greater than the distance between the projection of the second discharge transistor MN2 on the substrate and the projection of the power supply pad VDD on the substrate, so that the impedance of the parasitic device between the first discharge transistor MN1 and the power supply pad VDD is greater than the impedance of the parasitic device between the second discharge transistor MN2 and the power supply pad VDD.

[0067] Figure 6 This is the projection of the discharge transistor and the power supply pad VDD provided by the present application on the substrate. As Figure 6 shown, in order to improve the discharge capacity of the discharge transistor, the discharge transistor usually adopts a multi-finger structure. The multi-finger structure centered relative to the power supply pad VDD is marked as the second discharge transistor MN2. The central axis of the second discharge transistor coincides with the central axis of the power supply pad VDD, so that the gate parasitic resistance and drain parasitic resistance of the second discharge transistor MN2 relative to the power supply pad VDD are minimized and it conducts first when an electrostatic pulse arrives. The multi-finger structure arranged around the power supply pad VDD is marked as the first discharge transistor MN1, that is, the central axis of the first discharge transistor MN1 does not coincide with the central axis of the power supply pad VDD, so that the gate parasitic resistance and drain parasitic resistance of the first discharge transistor MN1 relative to the power supply pad VDD are a little larger, and its conduction speed is slower than that of the second discharge transistor MN2.

[0068] To solve the problem of non-uniform conduction of the multi-finger structure transistor, the charging speed of the gate of the first-conducting multi-finger structure is slightly reduced. The charging speed of the first output terminal N1 of the monitoring unit 201 relative to the second output terminal N2 node is faster, and the voltage of the first output terminal N1 node relative to the second output terminal N2 node is also a little larger. The first output terminal N1 is used to charge the later-conducting multi-finger structure, and the second output terminal N2 is used to charge the first-conducting multi-finger structure, so as to ensure that the multi-finger structure in the middle and the multi-finger structure in the surrounding can conduct simultaneously or approximately simultaneously. Figure 6 Compared with Figure 3 it, the layout, area, etc. of the layout do not change, but Figure 6 due to the more uniform conduction of the discharge transistor, its electrostatic discharge capacity will be enhanced.

[0069] In one embodiment, the resistance value of the second resistor R2 is greater than that of the first resistor R1. When there is static charge on the power supply pad VDD, the gap between the voltage amplitude at the second end of the monitoring capacitor C1 and the voltage amplitude at the second end of the first resistor R1 decreases, avoiding excessive adjustment of the conduction rate of the second discharge transistor MN2, so as to ensure that the conduction rates of the first discharge transistor MN1 and the second discharge transistor MN2 are similar, making the conduction of the multi-finger structure transistors more uniform.

[0070] In one embodiment, as Figure 7 shown, the first discharge transistor MN1 and the second discharge transistor MN2 also have substrate terminals, and the substrate terminals of the first discharge transistor MN1 and the second discharge transistor MN2 are connected to the ground pad GND, which can effectively reduce the influence of the latching effect.

[0071] As Figure 8 shown, the first end of the monitoring capacitor C1 is connected to the ground pad GND, the second end of the monitoring capacitor C1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the power supply pad VDD.

[0072] In one embodiment, the first discharge transistor MP1 and the second discharge transistor MP2 are both P-type transistors. The voltage signal at the second end of the monitoring capacitor C1 is the first trigger signal, and the voltage signal at the second end of the first resistor R1 is the second trigger signal. When there is static charge on the power supply pad VDD, the impedance of the monitoring capacitor C1 becomes smaller, the voltages at the second end of the monitoring capacitor C1 and the second end of the first resistor R1 both decrease, and the voltage amplitude at the second end of the monitoring capacitor C1 is less than the voltage amplitude at the second end of the first resistor R1, that is, the amplitude of the first trigger signal is less than that of the second trigger signal.

[0073] When there is a static pulse on the power supply pad VDD, the discharge rate of the first output terminal N1 of the monitoring unit 201 is greater than the discharge rate of the second output terminal N2 of the monitoring unit 201, so as to increase the conduction rate of the first discharge transistor MP1. When the conduction rate of the first discharge transistor MP1 is less than that of the second discharge transistor MP2 due to excessive parasitic parameters, the gap between the conduction rates of the first discharge transistor MP1 and the second discharge transistor MP2 can be reduced, avoiding the failure of the transistor with a fast conduction rate due to flowing through a large static current, and improving the reliability of the electrostatic protection circuit.

[0074] In one embodiment, as Figure 9 shown, the first discharge transistor MP1 and the second discharge transistor MP2 also have substrate terminals, and the substrate terminals of the first discharge transistor MP1 and the second discharge transistor MP2 are connected to the power supply pad VDD, which can effectively reduce the influence of the latching effect.

[0075] As Figure 10 shown, the monitoring unit 201 is further provided with a third output terminal N3, and the electrostatic protection circuit further includes a third discharge transistor MN3. The control terminal of the third discharge transistor MN3 is connected to the third output terminal N3 of the monitoring unit 201. The third output terminal N3 is used to output a third trigger signal. The first terminal of the third discharge transistor MN3 is connected to the power supply pad VDD, and the second terminal of the third discharge transistor MN3 is connected to the ground pad GND. The third discharge transistor MN3 is used to discharge the static charge to the ground pad GND under the trigger of the third trigger signal.

[0076] The amplitude of the third trigger signal is different from the amplitudes of the first trigger signal and the second trigger signal. When the amplitude of the third trigger signal is less than the amplitude of the first trigger signal and also less than the amplitude of the second trigger signal, the charging or discharging rate of the control terminal of the third discharge transistor MN3 is less than the charging or discharging rate of the second discharge transistor MN2 and also less than the charging or discharging rate of the first discharge transistor MN1. If the impedance of the parasitic device of the first discharge transistor MN1 is set to be the largest, the impedance of the parasitic device of the second discharge transistor MN2 is the second largest, and the impedance of the parasitic device of the third discharge transistor MN3 is the smallest, under the influence of the parasitic device and the control of the trigger signal, the conduction rates of the first discharge transistor MN1, the second discharge transistor MN2, and the third discharge transistor MN3 can be made close, avoiding the failure of the transistor with a fast conduction rate due to excessive static current flowing through it, and improving the reliability of the electrostatic protection circuit.

[0077] In an embodiment, the monitoring unit 201 includes a monitoring capacitor C1, a first resistor R1, a second resistor R2, and a third resistor R3. The monitoring capacitor C1, the first resistor R1, the second resistor R2, and the third resistor R3 are all provided with a first terminal and a second terminal. The first terminal of the monitoring capacitor C1 is connected to the power supply pad VDD. After the second terminal of the monitoring capacitor C1 and the first terminal of the first resistor R1 are connected, a first output terminal N1 of the monitoring unit 201 is formed. The first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1 to form a second output terminal N2 of the monitoring unit 201. The first terminal of the third resistor R3 is connected to the second terminal of the second resistor R2 to form a third output terminal N3 of the monitoring unit 201.

[0078] In one embodiment, the first discharge transistor MN1, the second discharge transistor MN2, and the third discharge transistor MN3 are all N-type transistors. The voltage signal at the second terminal of the monitoring capacitor C1 is the first trigger signal, the voltage signal at the second terminal of the first resistor R1 is the second trigger signal, and the voltage signal at the second terminal of the second resistor R2 is the third trigger signal. When there is static charge on the power supply pad VDD, the impedance of the monitoring capacitor C1 becomes smaller, and the voltages at the second terminals of the monitoring capacitor C1, the first resistor R1, and the second resistor R2 all increase. The voltage amplitude at the second terminal of the monitoring capacitor C1 is greater than the voltage amplitude at the second terminal of the first resistor R1, and the voltage amplitude at the second terminal of the first resistor R1 is greater than the voltage amplitude at the second terminal of the second resistor R2. That is, the amplitude of the first trigger signal is greater than the amplitude of the second trigger signal, and the amplitude of the second trigger signal is greater than the amplitude of the third trigger signal.

[0079] The distance between the projection of the first discharge transistor MN1 on the substrate and the projection of the power supply pad VDD on the substrate is greater than the distance between the projection of the second discharge transistor MN2 on the substrate and the projection of the power supply pad VDD on the substrate, so that the impedance of the parasitic device between the first discharge transistor MN1 and the power supply pad VDD is greater than the impedance of the parasitic device between the second discharge transistor MN2 and the power supply pad VDD. The distance between the projection of the second discharge transistor MN2 on the substrate and the projection of the power supply pad VDD on the substrate is greater than the distance between the projection of the third discharge transistor MN3 on the substrate and the projection of the power supply pad VDD on the substrate, so that the impedance of the parasitic device between the second discharge transistor MN2 and the power supply pad VDD is greater than the impedance of the parasitic device between the third discharge transistor MN3 and the power supply pad VDD.

[0080] The trigger signal makes the conduction rate of the first discharge transistor MN1 the largest, the conduction rate of the second discharge transistor MN2 the second largest, and the conduction rate of the third discharge transistor MN3 the smallest. The impedance of the parasitic device makes the conduction rate of the first discharge transistor MN1 the smallest, the conduction rate of the second discharge transistor MN2 the middle, and the conduction rate of the third discharge transistor MN3 the largest. By setting like this, the conduction rates of the first discharge transistor MN1, the second discharge transistor MN2, and the third discharge transistor MN3 can be balanced.

[0081] In one embodiment, the transistor adopts a multi-finger structure. The multi-finger structure centered relative to the power supply pad VDD is marked as the third discharge transistor MN3, the multi-finger structures located on both sides of the third discharge transistor MN3 are marked as the second discharge transistors MN2, and the multi-finger structures located on both sides of the second discharge transistors MN2 are marked as the first discharge transistors MN1. By connecting the gates of the multi-finger structures in the middle to the second end of the second resistor R2, connecting the multi-finger structures on both sides to the second end of the first resistor R1, and connecting the multi-finger structures far from the power supply pad VDD to the second end of the monitoring capacitor C1, the conduction rate of the multi-finger structures far from the power supply pad VDD can be improved, so that the conduction rates of the multi-finger structures are more uniform, and the effect is better for the case where the finger structures of the discharge transistor with a larger size have more fingers.

[0082] It should be understood that the present application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An electrostatic protection circuit for a chip, characterized in that, The chip includes a power pad and a ground pad, and the electrostatic protection circuit includes: A monitoring unit, which is connected between the power pad and the ground pad, and is provided with a first output terminal and a second output terminal, and is used for generating a first trigger signal and a second trigger signal when there is an electrostatic pulse on the power pad; A first discharge transistor, whose control terminal is connected to the first output terminal, whose first end is connected to the power pad, and whose second end is connected to the ground pad, and is used for discharging electrostatic charges to the ground pad under the trigger of the first trigger signal; A second discharge transistor, whose control terminal is connected to the second output terminal, whose first end is connected to the power pad, and whose second end is connected to the ground pad, and is used for discharging electrostatic charges to the ground pad under the trigger of the second trigger signal; The monitoring unit includes: A monitoring capacitor, which is provided with a first end and a second end; A first resistor, which is provided with a first end and a second end, and the first end of which is connected to the second end of the monitoring capacitor to form the first output terminal of the monitoring unit; A second resistor, which is provided with a first end and a second end, and the first end of which is connected to the second end of the first resistor to form the second output terminal of the monitoring unit.

2. The electrostatic protection circuit according to claim 1, wherein The resistance value of the second resistor is greater than that of the first resistor.

3. The electrostatic protection circuit according to claim 2, characterized in that, The first discharge transistor and the second discharge transistor share a substrate, and the distance between the projection of the first discharge transistor on the substrate and the first projection of the power pad on the substrate is greater than the distance between the projection of the second discharge transistor on the substrate and the first projection.

4. The electrostatic protection circuit according to claim 3, wherein, The first discharge transistor includes a first multi-finger structure, and the second discharge transistor includes a second multi-finger structure, wherein the first multi-finger structure and the second multi-finger structure are arranged adjacent to each other.

5. The electrostatic protection circuit according to claim 1, characterized in that The first end of the monitoring capacitor is connected to the power pad, and the second end of the second resistor is connected to the ground pad.

6. The electrostatic protection circuit according to claim 5, wherein, Both the first discharge transistor and the second discharge transistor are N-type transistors, and the substrate ends of the first discharge transistor and the second discharge transistor are connected to the ground pad.

7. The electrostatic protection circuit according to claim 6, wherein When there is an electrostatic pulse on the power pad, the charging rate of the first output terminal of the monitoring unit is greater than the charging rate of the second output terminal of the monitoring unit.

8. The electrostatic protection circuit according to claim 1, characterized in that, The first end of the monitoring capacitor is connected to the ground pad, and the second end of the second resistor is connected to the power pad.

9. The electrostatic protection circuit according to claim 8, wherein Both the first discharge transistor and the second discharge transistor are P-type transistors, and the substrate ends of the first discharge transistor and the second discharge transistor are connected to the power pad.

10. The electrostatic protection circuit according to claim 9, wherein When there is an electrostatic pulse on the power pad, the discharging rate of the first output terminal of the monitoring unit is greater than the discharging rate of the second output terminal of the monitoring unit.

11. The electrostatic protection circuit according to claim 1, wherein The monitoring unit is further provided with a third output terminal, and the electrostatic protection circuit further includes: A third discharge transistor, whose control terminal is connected to the third output terminal of the monitoring unit, whose first end is connected to the power pad, and whose second end is connected to the ground pad, and is used for discharging electrostatic charges to the ground pad.

12. The electrostatic protection circuit according to claim 11, characterized in that, The monitoring unit further includes: A monitoring capacitor, which is provided with a first end and a second end; A first resistor having a first end and a second end, the first end of which is connected to the second end of the monitoring capacitor to form a first output end of the monitoring unit; A second resistor having a first end and a second end, the first end of which is connected to the second end of the first resistor to form a second output end of the monitoring unit; A third resistor having a first end and a second end, the first end of which is connected to the second end of the second resistor to form a third output end of the monitoring unit.

13. The electrostatic protection circuit according to claim 12, wherein The distance between the projection of the first discharge transistor on the substrate and the first projection of the power supply pad on the substrate is greater than the distance between the second projection of the second discharge transistor on the substrate and the first projection; The distance between the projection of the third discharge transistor on the substrate and the projection of the power supply pad on the substrate is less than the distance between the second projection and the first projection.

14. The electrostatic protection circuit according to claim 12, wherein The first discharge transistor, the second discharge transistor, and the third discharge transistor are all N-type transistors.

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