An internal ripple compensation circuit based on output voltage automatic adjustment and electronic chip

Abstract

The application discloses a kind of based on output voltage automatic regulation internal ripple compensation circuit and electronic chip, the compensation circuit includes: compensation ripple voltage generation unit, for generating out with inductance current phase same and proportional amplitude ripple voltage;Equivalent FB voltage shift unit, for the equivalent FB voltage is shifted to second node by level;Coupling unit, for the ripple voltage is coupled to the second node superposition;Reference voltage shift unit, for reference voltage is shifted to third node by level;Pulse width modulation unit, for the input of second node and third node, output pulse width modulation signal;Ripple voltage regulation unit, for the size of converter output voltage, automatically adjust the ripple voltage size generated by compensation ripple voltage generation unit.According to the embodiment of the present application, the ripple compensation amount can be automatically adjusted according to the output voltage, and the high output transient characteristics and low output stability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an internal ripple compensation circuit and an electronic chip that automatically adjusts the output voltage. Background Art

[0002] In electronic circuit design, COT (Constant-on-Time) control offers significant advantages over traditional current-mode or voltage-mode control modes, including simplified compensation and design, fast response to load changes, and automatic frequency reduction at light loads, resulting in high efficiency. However, COT control imposes certain requirements on the output capacitor's ESR (Equivalent Series Resistance). If the ESR is too low, subharmonic oscillations can occur, leading to system instability.

[0003] High-performance electronic devices currently on the market have very stringent requirements for ripple and cost of power supply chips. Low-ESR and compact ceramic capacitors are essential to meet these requirements. Therefore, the COT control mode's ESR requirements make it impossible to directly apply it to these situations.

[0004] The traditional solution is to use external ripple compensation, adding external resistors and capacitors to simulate the ripple across the ESR, allowing the use of low-ESR ceramic capacitors. However, using ripple compensation with additional components increases cost, and system stability is susceptible to variations in the external compensation components. Furthermore, as the control system output changes, the compensated ripple also varies, resulting in greater ripple compensation at higher outputs and less ripple compensation at lower outputs. Excessive ripple compensation can lead to poor transient performance, while too little can cause instability at low output voltages. Summary of the Invention

[0005] The embodiments of the present invention aim to provide a circuit and electronic chip that automatically adjusts the internal ripple compensation based on the output voltage, which can automatically adjust the ripple compensation amount according to the output voltage, improve high output transient characteristics and low output stability, and save external device costs and improve competitiveness.

[0006] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions: a circuit for automatically adjusting internal ripple compensation based on output voltage, the compensation circuit comprising: a compensation ripple voltage generating unit, a coupling unit, an equivalent FB voltage shifting unit, a reference voltage shifting unit, a pulse width modulation unit, and a ripple voltage adjusting unit; wherein:

[0007] The compensation ripple voltage generating unit is connected in series between the switch node and the ground to form a first node, and is used to generate a ripple voltage with the same phase as the inductor current and proportional to the amplitude;

[0008] The equivalent FB voltage shift unit is used to shift the equivalent FB voltage to the second node through level shifting;

[0009] The coupling unit is configured to couple and superimpose the ripple voltage onto the second node;

[0010] The reference voltage shifting unit is used to shift the reference voltage to the third node through level shifting;

[0011] The pulse width modulation unit is configured to output a pulse width modulation signal according to inputs from the second node and the third node;

[0012] The ripple voltage regulating unit is used to automatically adjust the magnitude of the ripple voltage generated by the compensation ripple voltage generating unit according to the magnitude of the converter output voltage.

[0013] Optionally, the compensation ripple voltage generating unit includes: a first resistor and a first capacitor, the first resistor and the first capacitor are connected in series between the switch node and the ground, and a ripple voltage with the same phase and proportional to the amplitude of the inductor current is generated at a first node where the first resistor and the first capacitor are connected.

[0014] Optionally, the equivalent FB voltage shifting unit includes: a first PMOS transistor and a first current source, the first current source is connected to the drain of the first PMOS transistor to provide a bias current for the first PMOS transistor; the gate of the first PMOS transistor is connected to the equivalent FB voltage terminal, the source is grounded, and the drain is also connected to the second node, and the equivalent FB voltage is level-shifted to the second node through the drain.

[0015] Optionally, the coupling unit includes a fourth capacitor, and the ripple voltage is coupled and superimposed on the second node through the fourth capacitor.

[0016] Optionally, the reference voltage shifting unit includes: a second PMOS tube and a second current source, the second current source is connected to the drain of the second PMOS tube to provide a bias current for the second PMOS tube; the gate of the second PMOS tube is connected to the reference voltage terminal, the source is grounded, and the drain is also connected to a third node, and the reference voltage is level-shifted to the third node through the drain.

[0017] Optionally, the pulse width modulation unit includes: a first comparator, wherein the positive input terminal of the first comparator is connected to the third node, the negative input terminal is connected to the second node, and the output terminal outputs the pulse width modulation signal.

[0018] Optionally, the ripple voltage regulating unit includes: a second capacitor, a first NMOS transistor and a second comparator; wherein:

[0019] The drain of the first NMOS tube is connected in series with the second capacitor and then connected to the first node, the source is grounded, and the gate is connected to the output end of the second comparator; the positive input end of the second comparator is connected to the first voltage divider signal output end of the converter output voltage, and the negative input end is connected to the second reference voltage end.

[0020] Optionally, the ripple voltage regulating unit further includes: a third capacitor, a second NMOS transistor and a third comparator; wherein:

[0021] The drain of the second NMOS tube is connected in series with the third capacitor and then connected to the first node, the source is grounded, and the gate is connected to the output end of the third comparator; the positive input end of the third comparator is connected to the second voltage-divided signal output end of the converter output voltage, and the negative input end is connected to the third reference voltage end.

[0022] To solve the above technical problems, an embodiment of the present invention further provides the following technical solution: an electronic chip, comprising an internal ripple compensation circuit that automatically adjusts based on output voltage as described in any embodiment of the present invention.

[0023] Compared with the prior art, embodiments of the present invention provide a circuit and electronic chip for automatically adjusting internal ripple based on output voltage. The compensation circuit includes: a compensation ripple voltage generating unit, a coupling unit, an equivalent FB voltage shifting unit, a reference voltage shifting unit, a pulse width modulation unit, and a ripple voltage adjustment unit. The compensation ripple voltage generating unit is connected in series between a switch node and ground to form a first node, and is configured to generate a ripple voltage having the same phase and amplitude as the inductor current; the equivalent FB voltage shifting unit is configured to level-shift the equivalent FB voltage to a second node; the coupling unit is configured to couple and superimpose the ripple voltage to the second node; the reference voltage shifting unit is configured to level-shift the reference voltage to a third node; the pulse width modulation unit is configured to output a pulse width modulation signal based on inputs from the second and third nodes; and the ripple voltage adjustment unit is configured to automatically adjust the ripple voltage generated by the compensation ripple voltage generating unit based on the output voltage of the converter. According to the embodiments of the present invention, a ripple voltage compensation generating unit is connected in series between the switch node SW and the ground GND, so that a ripple voltage having the same phase as the inductor current and proportional to the amplitude is generated at the first node N1 connected between SW and the ground GND. The ripple voltage is coupled to the equivalent FB voltage through the coupling unit and is superimposed on the equivalent FB voltage at the second node N2. This superimposes the inductor current information on the equivalent FB voltage, playing a role similar to the output ESR (equivalent series resistance), effectively preventing subharmonic oscillations in the loop. Furthermore, the ripple voltage regulation unit automatically adjusts the ripple voltage generated by the compensation ripple voltage generation unit according to the converter output voltage, automatically adjusting the ripple compensation amount based on the output voltage, improving high-output transient characteristics and low-output stability. There are no requirements for the output ESR value, and output stability can be maintained when ESR is approximately 0. This solves the problem of varying ripple compensation amounts at different outputs, namely, the problem of excessive ripple voltage affecting transient characteristics at high output and insufficient ripple voltage affecting stability at low output, thereby broadening the application range of the COT architecture. Furthermore, the compensation circuit is implemented internally on the chip, avoiding the influence of external interference, improving system stability, saving external component costs, and enhancing competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0025] Figure 1A schematic diagram of a circuit for automatically adjusting an internal ripple compensation based on output voltage according to an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of an internal ripple compensation circuit that automatically adjusts output voltage according to an embodiment of the present invention.

[0027] Figure 3 A schematic diagram of a converter output voltage VOUT circuit provided by an embodiment of the present invention.

[0028] Figure 4 A schematic structural diagram of an electronic chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] For ease of understanding of the present invention, the present invention will be described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as being "connected to" another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "bottom" etc. used in this specification is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0030] Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this invention belongs. The terms used in this specification and in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the relevant listed items.

[0031] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] In one embodiment, Figure 1As shown, the present invention provides an internal ripple compensation circuit that automatically adjusts the output voltage. The internal ripple compensation circuit 100 includes: a compensation ripple voltage generating unit 10, a coupling unit 20, an equivalent FB (FeedBack) voltage shifting unit 30, a reference voltage shifting unit 40, a pulse width modulation unit 50, and a ripple voltage adjusting unit 60; wherein:

[0033] The compensation ripple voltage generating unit 10 is connected in series between the switch node SW and the ground GND to form a first node, and is used to generate a ripple voltage with the same phase and proportional amplitude as the inductor current at the first node N1 connected between SW and GND.

[0034] The equivalent FB voltage shift unit 30 is used to level-shift the equivalent FB voltage to the second node N2.

[0035] The coupling unit 20 is configured to couple the ripple voltage generated by the compensation ripple voltage generating unit at the first node N1 to the second node N2 .

[0036] The reference voltage shift unit 40 is used to shift the reference voltage VREF to the third node N3 through level shifting.

[0037] The pulse width modulation unit 50 is configured to output a pulse width modulation signal according to inputs from the second node N2 and the third node N3.

[0038] The ripple voltage regulating unit 60 is used to automatically regulate the magnitude of the ripple voltage generated by the compensation ripple voltage generating unit 10 according to the magnitude of the converter output voltage.

[0039] In this embodiment, a ripple voltage compensation generating unit is connected in series between the switch node SW and the ground GND. A ripple voltage having the same phase as the inductor current and proportional to the amplitude thereof is generated at a first node N1 connected between SW and the ground GND. The ripple voltage is coupled to the equivalent FB voltage through a coupling unit and is superimposed on the equivalent FB voltage at a second node N2. This superimposes the inductor current information on the equivalent FB voltage, playing a role similar to the output ESR (equivalent series resistance), effectively preventing subharmonic oscillations in the loop. Furthermore, the ripple voltage regulation unit corrects the ripple voltage according to the converter output voltage, automatically adjusting the ripple voltage generated by the compensation ripple voltage generation unit. This automatically adjusts the ripple compensation amount based on the output voltage, ensuring sufficient ripple compensation across the entire output range, improving high-output transient characteristics and low-output stability. The system has no requirements for the output ESR value and can maintain output stability when ESR is approximately 0. This solves the problem of varying ripple compensation amounts at different outputs, namely, addressing the issues of excessive ripple voltage affecting transient characteristics at high output and insufficient ripple voltage affecting stability at low output, thereby broadening the application range of the COT architecture. Furthermore, the compensation circuit is internal to the chip, avoiding the influence of external interference, improving system stability, and saving external component costs, enhancing competitiveness.

[0040] In one embodiment, Figure 2 As shown, the compensation ripple voltage generating unit 10 includes: a first resistor R1 and a first capacitor C1.

[0041] The first resistor R1 and the first capacitor C1 are connected in series between SW and GND, and a ripple voltage having the same phase as the inductor current and proportional to the amplitude is generated at a first node N1 where the first resistor R1 and the first capacitor C1 are connected.

[0042] In this embodiment, if Figure 2 As shown in Figure 1, when the upper tube of the switch node (such as the BUCK circuit) is turned on, the SW node voltage is equal to the input voltage V IN At this time, the first capacitor C1 is charged, and the initial voltage of the first node N1 is V1. Then the voltage of the first node N1 is:

[0043]

[0044] When RC>>T (T is the switching period), the above formula (1) is equal to:

[0045]

[0046]

[0047] The rate of rise of the inductor current is:

[0048]

[0049] Therefore, when the inductor current increases:

[0050]

[0051] When the lower tube of the switch node is turned on, the voltage of the SW node is equal to ground. At this time, the first capacitor C1 is discharged, and the initial value of the first node N1 is V1. Then the voltage of the first node N1 is:

[0052]

[0053] When RC>>T, the above formula (6) is equal to:

[0054]

[0055] The rate of decrease of the inductor current is:

[0056]

[0057] Therefore, when the inductor current decreases:

[0058]

[0059] Therefore, during the entire switching period T, the relationship between the inductor current and the compensation ripple voltage is:

[0060]

[0061] From the above formula (10), it can be concluded that the phase of the compensation ripple voltage is in phase with the inductor current, and the amplitude is L / RC times of the inductor current, thereby replacing the effect of the ESR resistor. Superimposing this ripple voltage on the equivalent FB voltage can effectively prevent the subharmonic oscillation phenomenon of the loop.

[0062] In this embodiment, an internal ripple compensation method is employed. A first resistor R1 and a first capacitor C1 are connected in series between the switch node SW and ground GND. A ripple voltage with the same phase and amplitude as the inductor current is generated at a first node N1 where the first resistor R1 and the first capacitor C1 are connected. This ripple voltage is then coupled to the equivalent FB voltage via a coupling unit and superimposed on the equivalent FB voltage at a second node N2. This superposition of the inductor current information on the equivalent FB voltage acts similarly to an output ESR resistor, effectively preventing subharmonic oscillation in the loop, while saving costs and protecting the system from external interference.

[0063] In one embodiment, Figure 2As shown, the equivalent FB voltage shift unit 30 includes: a first PMOS transistor MP1 and a first current source IBIAS1.

[0064] The first current source IBIAS1 is connected to the drain of the first PMOS transistor MP1 to provide a bias current for the first PMOS transistor MP1; the gate of the first PMOS transistor MP1 is connected to the equivalent FB voltage terminal, the source is grounded, and the drain is also connected to the second node N2, and the equivalent FB voltage is level-shifted to the second node N2 through the drain.

[0065] The first current source IBIAS1 provides a bias current for the first PMOS transistor MP1 and must satisfy the following formula:

[0066]

[0067]

[0068] R1*C1≥10*T (13)

[0069] Wherein, Zc4 and Zc1 are the impedances of the fourth capacitor C4 and the first capacitor C1, g mp1 is the transconductance of MP1, and T is the switching period.

[0070] In this embodiment, the equivalent FB voltage shift unit 30 is described by taking a PMOS tube as an example, but is not limited to a PMOS tube. It can also be implemented by using an NMOS tube, a transistor, or other electronic components having the same or similar structure or function. Its circuit structure is the same as that of the PMOS tube, and will not be repeated here.

[0071] In one embodiment, Figure 2 As shown, the coupling unit 20 includes a fourth capacitor C4, through which the ripple voltage generated by the compensation ripple voltage generating unit at the first node N1 is coupled and superimposed on the second node N2, that is, superimposed on the voltage shifted by the equivalent FB voltage shifting unit at the second node N2.

[0072] In this embodiment, a ripple voltage with the same phase and proportional amplitude as the inductor current is coupled to the equivalent FB voltage via the fourth capacitor C4 and superimposed with the equivalent FB voltage at the second node N2. This adds inductor current information to the equivalent FB voltage, effectively preventing subharmonic oscillation in the loop.

[0073] In one embodiment, Figure 2 As shown, the reference voltage shift unit 40 includes: a second PMOS transistor MP2 and a second current source IBIAS2.

[0074] The second current source IBIAS2 is connected to the drain of the second PMOS transistor MP2 to provide a bias current for the second PMOS transistor MP2; the gate of the second PMOS transistor MP2 is connected to the reference voltage VREF terminal, the source is grounded, and the drain is also connected to the third node N3, and the reference voltage VREF is level-shifted to the third node N3 through the drain.

[0075] In this embodiment, the reference voltage shifting unit is described using a PMOS tube as an example, but is not limited to a PMOS tube. It can also be implemented using electronic components with the same or similar structure or function, such as an NMOS tube and a transistor. Its circuit structure is the same as that of the PMOS tube, and will not be repeated here.

[0076] In one embodiment, Figure 2 As shown, the pulse width modulation unit 50 includes: a first comparator COMP1, wherein the positive input terminal of the first comparator COMP1 is connected to the third node N3, the negative input terminal is connected to the second node N2, and the output terminal outputs the pulse width modulation signal PWM.

[0077] In this embodiment, by connecting the third node N3 to the positive input terminal of the first comparator COMP1 and the second node N2 to the negative input terminal of the first comparator COMP1, a pulse signal is generated at the output terminal to turn on the upper tube of the switch node (e.g., the BUCK circuit).

[0078] In one embodiment, Figure 2 As shown, the ripple voltage regulating unit 60 includes: a second capacitor C2, a third capacitor C3, a first NMOS transistor MN1, a second NMOS transistor MN2, a second comparator COMP2 and a third comparator COMP3.

[0079] The drain of the first NMOS transistor MN1 is connected in series with the second capacitor C2 and then connected to the first node N1. The source is grounded and the gate is connected to the output of the second comparator COMP2. The positive input of the second comparator COMP2 is connected to the first voltage-divided signal output terminal of the converter output voltage VOUT, the negative input is connected to the second reference voltage VREF2, and the output is connected to the gate of the first NMOS transistor MN1. The first voltage-divided signal is K2*VOUT. The converter output voltage VOUT is as follows: Figure 3 shown.

[0080] The drain of the second NMOS transistor MN2 is connected in series with the third capacitor C3 and then connected to the first node N1. The source is grounded and the gate is connected to the output of the third comparator COMP3. The positive input of the third comparator COMP3 is connected to the second voltage-divided signal output terminal of the converter output voltage VOUT, the negative input is connected to the third reference voltage VREF3, and the output is connected to the gate of the second NMOS transistor MN2. The second voltage-divided signal is K1*VOUT. The converter output voltage VOUT is as follows: Figure 3 shown.

[0081] In this embodiment, when the converter output voltage VOUT is too high, the output terminals of the second comparator COMP2 and the third comparator COMP3 output high-level signals, turning on the first NMOS transistor MN1 and the second NMOS transistor MN2, charging the second capacitor C2 and the third capacitor C3, thereby increasing the capacitance of the first node N1 and reducing the compensation ripple voltage. When the converter output voltage VOUT is too low, the output terminals of the second comparator COMP2 and the third comparator COMP3 output low-level signals, turning off the first NMOS transistor MN1 and the second NMOS transistor MN2, discharging the second capacitor C2 and the third capacitor C3, reducing the capacitance of the first node N1 and increasing the compensation ripple voltage.

[0082] Therefore, the ripple is corrected through the converter output voltage VOUT, and the ripple compensation amount is automatically adjusted according to the output voltage, so that the ripple compensation amount is sufficient in the entire output range, improving the high output transient characteristics and low output stability. There is no requirement for the output ESR resistance value, and the output can be kept stable when ESR≈0. The problem of changes in ripple compensation amount at different outputs can be solved, that is, the problem of excessive ripple voltage affecting transient characteristics at high output and too small ripple voltage affecting stability at low output can be solved, thereby broadening the application scope of the COT architecture.

[0083] In this embodiment, the ripple voltage regulation unit is described by taking an NMOS tube as an example, but is not limited to an NMOS tube. It can also be implemented by using electronic components with the same or similar structure or function, such as a PMOS tube and a transistor. Its circuit structure is the same as that of the NMOS tube, and will not be repeated here.

[0084] The following takes the BUCK circuit as an example to illustrate the actual operation of the internal ripple compensation circuit based on automatic output voltage adjustment provided by the present invention.

[0085] like Figure 1 As shown, the present invention provides an internal ripple compensation circuit based on automatic output voltage regulation. In actual operation, when the upper tube of the BUCK circuit is turned on, the voltage of the switch node SW is equal to the input voltage V INAt this time, the first capacitor C1 charges, and the voltage at the first node N1 rises. When the lower transistor of the buck circuit is turned on, the voltage at the switch node SW is equal to zero. At this time, the first capacitor C1 discharges, and the voltage at the first node N1 drops. Thus, when the buck circuit is operating, a ripple voltage proportional to the inductor current forms at the first node N1. This ripple voltage is coupled to the second node N2 via the fourth capacitor C4 and superimposed with the voltage shifted by the equivalent FB voltage at the second node N2. The reference voltage VREF is level-shifted and connected to the third node N3. The voltages at the second and third nodes N2 are connected to the first comparator COMP1, which generates a pulse signal to turn on the upper transistor of the buck circuit. The first current source IBIAS1 and the second current source IBIAS2 are matched, and the first and second PMOS transistors MP1 and MP2 are matched. The first and second current sources IBIAS1 and IBIAS2 provide bias currents for the first and second PMOS transistors MP1 and MP2, respectively.

[0086] The second capacitor C2, the third capacitor C3, the first NMOS transistor MN1, the second NMOS transistor MN2, the second comparator COMP2, and the third comparator COMP3 constitute a ripple voltage adjustment unit. When the converter output voltage VOUT is too high, the output terminals of the second comparator COMP2 and the third comparator COMP3 output high-level signals, turning on the first and second NMOS transistors MN1 and MN2, charging the second and third capacitors C2 and C3, thereby increasing the capacitance of the first node N1 and reducing the compensation ripple voltage. When the converter output voltage VOUT is too low, the output terminals of the second comparator COMP2 and the third comparator COMP3 output low-level signals, turning off the first and second NMOS transistors MN1 and MN2, discharging the second and third capacitors C2 and C3, reducing the capacitance of the first node N1 and increasing the compensation ripple voltage. Furthermore, the ripple voltage can be automatically adjusted in two levels according to the output amplitude of the output voltage of the first comparator COMP1. Therefore, the converter output voltage VOUT corrects the ripple and automatically adjusts the ripple compensation amount according to the output voltage, so that the ripple compensation amount is sufficient in the entire output range, improving the high output transient characteristics and low output stability. There is no requirement for the output ESR resistance value, and the output can be kept stable when ESR≈0. It can solve the problem of changes in ripple compensation amount at different outputs, that is, it can solve the problem of excessive ripple voltage affecting transient characteristics at high output and too small ripple voltage affecting stability at low output, thereby broadening the application scope of the COT architecture.

[0087] Based on the same concept, in one embodiment, Figure 4 As shown, the present invention provides an electronic chip, which includes an internal ripple compensation circuit 100 that automatically adjusts the output voltage based on any of the above embodiments.

[0088] In this embodiment, the internal ripple compensation circuit 100 automatically adjusting the output voltage is consistent with the internal ripple compensation circuit 100 automatically adjusting the output voltage described in any of the above embodiments. The specific structure and function can refer to the internal ripple compensation circuit 100 automatically adjusting the output voltage described in any of the above embodiments, and will not be repeated here.

[0089] In this embodiment, an internal ripple compensation method is adopted, which is achieved by connecting resistors and capacitors in series between the switch node SW and the ground GND. The compensation circuit is built into the chip, which saves costs, avoids the influence of external interference on the system, and improves the stability of the system. In addition, the converter output voltage VOUT corrects the ripple and automatically adjusts the ripple compensation amount according to the output voltage to ensure that the ripple compensation amount is sufficient in the entire output range, improves the high output transient characteristics and low output stability, has no requirements for the output ESR resistance value, can maintain output stability when ESR≈0, and can solve the problem of different output ripple compensation amount changes, that is, it can solve the problem of excessive ripple voltage affecting transient characteristics at high output and too small ripple voltage affecting stability at low output, thereby broadening the application scope of the COT architecture.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present invention as described above. For the sake of simplicity, they are not provided in detail. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit for automatically adjusting internal ripple compensation based on output voltage, characterized in that: The internal ripple compensation circuit includes: a compensation ripple voltage generating unit, a coupling unit, an equivalent FB voltage shifting unit, a reference voltage shifting unit, a pulse width modulation unit, and a ripple voltage regulating unit; wherein: The compensation ripple voltage generating unit is connected in series between the switch node and the ground to form a first node, and is used to generate a ripple voltage with the same phase as the inductor current and proportional to the amplitude; The equivalent FB voltage shift unit is used to shift the equivalent FB voltage to the second node through level shifting; The coupling unit is configured to couple and superimpose the ripple voltage onto the second node; The reference voltage shifting unit is used to shift the reference voltage to the third node through level shifting; The pulse width modulation unit is configured to output a pulse width modulation signal according to inputs from the second node and the third node; The ripple voltage regulating unit is used to automatically adjust the magnitude of the ripple voltage generated by the compensation ripple voltage generating unit according to the magnitude of the converter output voltage.

2. The internal ripple compensation circuit according to claim 1, wherein: The compensation ripple voltage generating unit includes: a first resistor and a first capacitor, wherein the first resistor and the first capacitor are connected in series between a switch node and ground, and a ripple voltage having the same phase as the inductor current and proportional to the amplitude is generated at a first node where the first resistor and the first capacitor are connected.

3. The internal ripple compensation circuit according to claim 1, wherein: The equivalent FB voltage shifting unit includes: a first PMOS transistor and a first current source, wherein the first current source is connected to the drain of the first PMOS transistor to provide a bias current for the first PMOS transistor; the gate of the first PMOS transistor is connected to the equivalent FB voltage terminal, the source is grounded, and the drain is also connected to the second node, and the equivalent FB voltage is level-shifted to the second node through the drain.

4. The internal ripple compensation circuit according to claim 1, wherein: The coupling unit includes a fourth capacitor, and the ripple voltage is coupled and superimposed on the second node through the fourth capacitor.

5. The internal ripple compensation circuit according to claim 4, characterized in that: The reference voltage shifting unit includes: a second PMOS transistor and a second current source, the second current source is connected to the drain of the second PMOS transistor to provide a bias current for the second PMOS transistor; the gate of the second PMOS transistor is connected to the reference voltage terminal, the source is grounded, and the drain is also connected to the third node, and the reference voltage is level-shifted to the third node through the drain.

6. The internal ripple compensation circuit according to claim 5, characterized in that: The pulse width modulation unit includes: a first comparator, wherein a positive input terminal of the first comparator is connected to the third node, a negative input terminal of the first comparator is connected to the second node, and an output terminal of the first comparator outputs a pulse width modulation signal.

7. The internal ripple compensation circuit according to claim 6, characterized in that: The ripple voltage regulating unit includes: a second capacitor, a first NMOS transistor and a second comparator; wherein: The drain of the first NMOS tube is connected in series with the second capacitor and then connected to the first node, the source is grounded, and the gate is connected to the output end of the second comparator; the positive input end of the second comparator is connected to the first voltage divider signal output end of the converter output voltage, and the negative input end is connected to the second reference voltage end.

8. The internal ripple compensation circuit according to claim 7, wherein: The ripple voltage regulating unit further includes: a third capacitor, a second NMOS transistor and a third comparator; wherein: The drain of the second NMOS tube is connected in series with the third capacitor and then connected to the first node, the source is grounded, and the gate is connected to the output end of the third comparator; the positive input end of the third comparator is connected to the second voltage-divided signal output end of the converter output voltage, and the negative input end is connected to the third reference voltage end.

9. An electronic chip, characterized in that: The electronic chip includes an internal ripple compensation circuit that automatically adjusts based on output voltage as described in any one of claims 1 to 8.

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