A method of encapsulating fine lines of electroplated metal

Abstract

The application discloses a method for packaging electroplated metal fine lines, and comprises the following operation steps: once inverted trapezoidal photoetching pattern production: producing a pattern on a substrate through photoetching technology; seed layer production: producing a seed layer through sputtering technology; electroplating thickening: thickening the lines through electroplating; photoresist removal: removing the first photoresist; second photoetching pattern: protecting the lines to be reserved through second photoresist; etching: removing the lines for electroplating conduction between non-fine lines and different units through wet etching technology; removing the photoresist again to form the packaging electroplated metal fine lines. The method for packaging electroplated metal fine lines has the advantages that the photoetching CD and the line finished product CD are kept consistent through second photoetching technology, additional CD compensation is not needed, the technical requirement and cost of a photoetching machine are reduced, the fine lines have no undercut, and the performance is more excellent; and the dry etching technology is not needed, so that the cost advantage is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of packaging, in particular to a method for packaging fine metal lines of electroplating. BACKGROUND

[0002] The method for packaging fine metal lines of electroplating is a scheme for providing a seed layer of electroplating to manufacture fine lines of packaging. When manufacturing fine lines of packaging, an etching method is used to prepare fine lines. With the continuous development of science and technology, people have higher and higher requirements for the manufacturing process of the method for packaging fine metal lines of electroplating.

[0003] The existing method for packaging fine metal lines of electroplating has certain disadvantages in use. First, the existing technology requires that the line width after etching be smaller than the line width after photolithography, which increases the technical requirements of the photolithography machine and the manufacturing cost, and is not conducive to the use of people. In addition, the existing technology has obvious undercut after etching, which affects the bonding force of the line and the substrate. The no-undercut technology needs to use dry etching technology, which is high in cost and brings certain disadvantages to the use of people. Therefore, we propose a method for packaging fine metal lines of electroplating. SUMMARY

[0004] (I) Technical problems solved

[0005] In view of the deficiencies of the prior art, the present application provides a method for packaging fine metal lines of electroplating. By using twice photolithography technology, the photolithography CD and the line finished product CD are kept consistent, no additional CD compensation is needed, the technical requirements of the photolithography machine and the cost are reduced, the fine line has no undercut, and the performance is more excellent. No dry etching technology is needed, which has cost advantage and can effectively solve the problems in the background art.

[0006] (II) Technical solutions

[0007] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows: a method for packaging fine metal lines of electroplating, comprising the following operation steps:

[0008] S1: One-time inverted trapezoidal photolithography pattern manufacturing: manufacturing a pattern on a substrate by photolithography technology. The pattern of photolithography is an inverted trapezoid, and the photoresist can withstand the seed layer process;

[0009] S2: Seed layer manufacturing: manufacturing a seed layer by sputtering process, and sputtering the seed layer onto the substrate to form a shape at the position of the electroplated line;

[0010] S3: Electroplating thickening: thickening the line by electroplating to meet the electrical requirements;

[0011] S4: Photoresist Removal: Remove photoresist once to ensure complete removal of photoresist from the substrate surface;

[0012] S5: Secondary photolithography pattern: Apply secondary photoresist to protect the lines that need to be preserved;

[0013] S6: Etching: Using techniques such as wet etching, remove non-fine lines used for electroplating conductivity between different units;

[0014] S7: Secondary photoresist removal: Remove the photoresist again to ensure that the photoresist on the circuit surface is completely removed, forming a fine encapsulated electroplated metal circuit.

[0015] As a preferred technical solution of this application, the process of preparing fine circuits by encapsulation electroplating metal in steps S1-S7 is as follows: first inverted trapezoidal photolithography pattern making, seed layer making, electroplating thickening, first photoresist removal, second photolithography pattern making, etching, and second photoresist removal.

[0016] As a preferred technical solution of this application, the secondary photolithography technology used in steps S1 and S5 is a process technology for fabricating fine circuits.

[0017] As a preferred technical solution of this application, the secondary photolithography technology ensures that the photolithographic CD and the finished circuit CD are consistent, without the need for additional CD compensation and without the need for dry lithography technology.

[0018] As a preferred technical solution of this application, the S4 and S7 steps employ a secondary photoresist removal process to ensure complete removal of photoresist from the circuit surface.

[0019] As a preferred technical solution of this application, the fine circuit of the encapsulated electroplated metal in step S7 has no undercut and no CD loss.

[0020] As a preferred technical solution of this application, the seed layer is formed and prepared by sputtering and electroplating processes in step S2.

[0021] As a preferred technical solution of this application, the S6 step uses wet etching technology to remove non-fine lines in the circuit.

[0022] (III) Beneficial Effects

[0023] Compared with the prior art, the present application provides a method for packaging fine lines of electroplated metal, which has the following beneficial effects: the method for packaging fine lines of electroplated metal, through secondary photolithography technology, realizes that the photolithography CD and the line finished product CD remain consistent, without the need for additional CD compensation, reduces the technical requirements and cost of the photolithography machine; the fine line has no undercut and has more excellent performance; without dry etching technology, it has cost advantages, provides a seed layer production packaging fine line scheme, solves the CD loss and line undercut problems of existing schemes, the fine line has no undercut and no CD loss, the entire method for packaging fine lines of electroplated metal has simple structure, convenient operation, and better use effect compared with the traditional way. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a structure schematic diagram of S1 step in the method for packaging fine lines of electroplated metal of the present application.

[0025] Figure 2 It is a structure schematic diagram of S2 step in the method for packaging fine lines of electroplated metal of the present application.

[0026] Figure 3 It is a structure schematic diagram of S3 step in the method for packaging fine lines of electroplated metal of the present application.

[0027] Figure 4 It is a structure schematic diagram of S4 step in the method for packaging fine lines of electroplated metal of the present application.

[0028] Figure 5 It is a structure schematic diagram of S5 step in the method for packaging fine lines of electroplated metal of the present application.

[0029] Figure 6 It is a structure schematic diagram of S6 step in the method for packaging fine lines of electroplated metal of the present application.

[0030] Figure 7 It is a structure schematic diagram of S7 step in the method for packaging fine lines of electroplated metal of the present application. DETAILED DESCRIPTION

[0031] The technical solutions of the present application will be described clearly and completely below in combination with the drawings and specific embodiments, but those skilled in the art will understand that the following described embodiments are part of the embodiments of the present application, not all the embodiments, and are only used to illustrate the present application, and should not be regarded as limiting the scope of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. The specific conditions are not specified in the embodiments, and are carried out according to the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments used are not specified by the manufacturer, and are conventional products that can be purchased on the market.

[0032] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0033] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0034] As shown in Figures 1-7 A method for packaging fine lines of electroplated metal, comprising the following operation steps:

[0035] S1: Once the inverted trapezoidal photoetching pattern is made: patterns are made on the substrate by photoetching technology, and the photoetching pattern is an inverted trapezoid, and the photoresist can withstand the seed layer process;

[0036] S2: Seed layer production: seed layer is produced by sputtering process, and the seed layer is sputtered onto the substrate to form a shape at the position of the electroplated line;

[0037] S3: Electroplating thickening: electroplating is used to thicken the line to meet the electrical requirements;

[0038] S4: photoresist removal: remove the first photoresist, ensure that the photoresist on the substrate surface is completely removed;

[0039] S5: second photoetching pattern: second photoetching protection is performed on the circuit to be retained;

[0040] S6: etching: through wet etching technology, remove the non-fine line between the different units and the line used for electroplating conductive;

[0041] S7: second photoresist removal: remove the photoresist again to ensure that the photoresist on the circuit surface is completely removed to form a fine circuit of encapsulated electroplated metal.

[0042] Further, the encapsulated electroplated metal fine circuit preparation process in steps S1-S7 is a one-time inverted trapezoidal photoetching pattern making, seed layer making, electroplating thickening, first photoresist removal, second photoetching pattern, etching, and second photoresist removal.

[0043] Further, the second photoetching technology is used in steps S1 and S5 to make fine circuit process technology.

[0044] Further, the second photoetching technology realizes that the photoetching CD and the line product CD remain consistent, without the need for additional CD compensation, and without the need for dry etching technology.

[0045] Further, the second photoresist removal process is used in steps S4 and S7 to ensure that the photoresist on the circuit surface is completely removed.

[0046] Further, the encapsulated electroplated metal fine circuit in step S7 has no undercut and no CD loss.

[0047] Further, the seed layer is formed and prepared by sputtering and electroplating process technology in step S2.

[0048] Further, the wet etching process technology is used in step S6 to remove the non-fine line in the circuit.

[0049] Embodiment:

[0050] As shown in Figure 1 : one-time inverted trapezoidal photoetching pattern making: through photoetching technology, make patterns on the substrate, the required photoetching pattern is an inverted trapezoid, and the photoresist can withstand the seed layer process;

[0051] As shown in Figure 2 : seed layer making: seed layer is made by sputtering process, and the seed layer needs to be sputtered on the substrate at the position of the electroplated line;

[0052] As shown in Figure 3As shown: Electroplating thickening: The circuit is electroplated thickened to meet electrical requirements;

[0053] like Figure 4 As shown: Photoresist removal: Removal of photoresist in one pass;

[0054] like Figure 5 As shown: Secondary photolithography pattern: secondary photoresist protection is applied to the lines that need to be preserved;

[0055] like Figure 6 As shown: Etching: Using techniques such as wet etching, the non-fine lines used for electroplating conductivity between different units are removed;

[0056] like Figure 7 As shown: Photoresist removal: removing photoresist to form circuits.

[0057] The fine circuit fabrication process employs a double photolithography technique, resulting in fine circuits with no undercut and no CD loss.

[0058] It should be noted that, in this document, relational terms such as first and second (number one, number two), etc., are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A method for encapsulating fine electroplated metal circuits, characterized in that: The following steps are included: S1: One-time inverted trapezoidal photolithography pattern fabrication: Using photolithography technology, a pattern is created on the substrate. The photolithographic pattern is an inverted trapezoid, and the photoresist is resistant to the seed layer process. S2: Seed layer fabrication: The seed layer is fabricated by sputtering. The seed layer is sputtered onto the substrate to form the electroplating circuit locations. S3: Electroplating Thickening: The circuit is thickened by electroplating to meet electrical requirements; S4: Photoresist Removal: Remove photoresist once to ensure complete removal of photoresist from the substrate surface; S5: Secondary photolithography pattern: Apply secondary photoresist to protect the lines that need to be preserved; S6: Etching: Using wet etching technology, remove the non-fine lines used for electroplating conductivity between different units; S7: Secondary photoresist removal: Remove the photoresist again to ensure that the photoresist on the circuit surface is completely removed, forming a fine encapsulated electroplated metal circuit. In steps S4 and S7, a secondary photoresist removal process is used to ensure that the photoresist on the circuit surface is completely removed.

2. The method for encapsulating electroplated metal fine circuits according to claim 1, characterized in that: The process for preparing fine metal encapsulation circuits in steps S1-S7 includes: first inverted trapezoidal photolithography pattern fabrication, seed layer fabrication, electroplating thickening, first photoresist removal, second photolithography pattern fabrication, etching, and second photoresist removal.

3. The method for encapsulating electroplated metal fine circuits according to claim 1, characterized in that: The S1 and S5 steps employ secondary photolithography as a process technology for fabricating fine circuit lines.

4. The method for encapsulating electroplated metal fine circuits according to claim 3, characterized in that: The secondary photolithography technology ensures that the photolithographic CD and the finished circuit CD are consistent, without the need for additional CD compensation and without the need for dry lithography technology.

5. The method for encapsulating fine electroplated metal circuits according to claim 1, characterized in that: In step S7, the encapsulated electroplated metal fine circuitry has no undercut and no CD loss.

6. The method for encapsulating fine electroplated metal circuits according to claim 1, characterized in that: In step S2, sputtering and electroplating processes are used to shape and prepare the seed layer.

7. The method for encapsulating electroplated metal fine circuits according to claim 1, characterized in that: In step S6, a wet etching process is used to remove non-fine lines from the circuit.

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