Method for improving read current stability in analog non-volatile memory

Abstract

The present disclosure provides a method and apparatus for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to reaching or exceeding a target threshold voltage of the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell to generate a first read current, the read voltage being less than the target threshold voltage. In response to determining that the first read current is greater than the target read current, subjecting the non-volatile memory cell to additional programming.

Description

[0001] Priority Statement

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 915,289, filed on June 29, 2020, entitled “Method of Improving ReadCurrent Stability in Analog Non-volatile Memory by Program Adjustment for Memory Cells Exhibiting Random Telegraph Noise”. Technical Field

[0003] The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations. Background Technology

[0004] Non-volatile memory devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration and is incorporated herein by reference. Specifically, this application… Figure 1 A split-gate memory cell 10 is shown, having spaced-apart source regions 14 and drain regions 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line via bit line contacts 28. A channel region 18 of the substrate is defined between the source region 14 and the drain region 16. A floating gate 20 is disposed over and insulated from (and controls the conductivity of) a first portion of the channel region 18 (and is partially located over and insulated from) the source region 14). A control gate 22 is disposed over and insulated from the floating gate 20. A select gate 24 is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18. An erase gate 26 is disposed over and insulated from the source region 14 and is laterally adjacent to the floating gate 20. Multiple such memory cells may be arranged in rows and columns to form a memory cell array.

[0005] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and / or the source region 14 / drain region 16 to program memory cells (i.e., inject electrons into the floating gate), erase memory cells (i.e., remove electrons from the floating gate), and read memory cells (i.e., measure or detect the conductivity of the channel region 18 to determine the programming state of the floating gate 20).

[0006] Memory cell 10 can be operated digitally, wherein the memory cell is set to only one of two possible states: a programming state and an erase state. The memory cell is erased by applying a high positive voltage to the erase gate 26 and optionally a negative voltage to the control gate 22, causing electrons to tunnel from the floating gate 20 to the erase gate 26 (putting the floating gate in a more positively charged state—the erase state). The memory cell 10 can be programmed by applying positive voltages to the control gate 22, the erase gate 26, the select gate 24, and the source region 14, and by applying current to the drain region 16. Electrons then flow along the channel region 18 from the drain region 16 to the source region 14, where the electrons become accelerated and heated, thereby some of them being injected into the floating gate 20 via hot electron injection (putting the floating gate in a more negatively charged state—the programming state). Memory cell 10 can be read by applying a positive voltage to select gate 24 (which turns on the channel region below select gate 24) and drain region 16 (and optionally on erase gate 26 and / or control gate 22) and sensing the current flowing through channel region 18. If floating gate 20 is positively charged (memory cell is erased), the memory cell is turned on, and current flows from source region 14 to drain region 16 (i.e., the memory cell 10 is sensed to be in its erase "1" state based on the sensed current flow). If floating gate 20 is negatively charged (memory cell is programmed), the channel region below the floating gate is turned off, thereby preventing any current flow (i.e., the memory cell 10 is sensed to be in its programmed "0" state based on the absence of current flow).

[0007] Table 1 provides non-limiting examples of erase, program, and read voltages, where Vcc is the power supply voltage or another positive voltage (such as 2.5V).

[0008] Table 1

[0009]

[0010] Memory cell 10 can optionally operate in an analog manner, wherein the memory state of the memory cell (i.e., the amount of charge on the floating gate, such as the number of electrons) can continuously change from a fully erased state (fewest electrons on the floating gate) to a fully programmed state (maximum number of electrons on the floating gate), or only a portion of that range, anywhere. This means that cell storage is analog, which allows for very precise and individual adjustments to each memory cell in the memory cell array. Alternatively, the memory can operate as an MLC (Multi-Level Cell), where it is configured to be programmed to one of many discrete values ​​(such as 16 or 64 different values). In the case of analog or MLC programming, the programming voltage is applied only for a finite time or as a series of pulses until the desired programming state is achieved. In the case of multiple programming pulses, intermediate read operations between programming pulses can be used to determine whether the desired programming state has been achieved (in which case programming stops) or has not yet been achieved (in which case programming continues).

[0011] Memory cells 10 operating in analog mode or as MLCs may be more sensitive to noise and read current instability, which can adversely affect the accuracy of the memory device. One source of read current instability in analog non-volatile memory devices is electron trapping and emission by oxide traps located at and near the interface between the gate oxide and the channel region of the memory cell. The gate oxide is an insulating layer that isolates the floating gate 20 and the channel region 18 of the substrate 12. When electrons are trapped at the interface traps, they reduce the channel conductivity during read operations and thus increase the threshold voltage Vt of the memory cell (i.e., the minimum voltage on the control gate required to turn on the channel region of the memory cell to generate a certain current level (e.g., 1 µA)). When the control gate voltage is equal to or higher than the threshold voltage, a conductive path is formed between the source and drain regions. When the control gate voltage is lower than the threshold voltage, no conductive path is formed, and any source / drain current is considered a sub-threshold or drain current. Electrons trapped in an interface trap can be emitted from the trap, thereby reducing the Vt of the memory cell and thus increasing the channel conductivity during read operations. These single-electron events of electron trapping and emission manifest as read current noise and are elsewhere referred to as random telegraph noise (RTN). Typically, the RTN generated by a single interface trap is characterized by two states: a lower Vt state (and a higher read current state) when an electron is emitted from the trap, and a higher Vt state (and a lower read current state) when an electron is trapped. As mentioned above, the instability of a memory cell during read operations can be characterized by a threshold voltage corresponding to the target current or by the memory cell current under a given read voltage condition. The preferred mode of characterizing memory cell read instability is the threshold voltage used in the specific embodiments of the present invention.

[0012] When memory cells are programmed to certain desired programming states, it is necessary to address the RTN in analog and MLC non-volatile memory devices. Summary of the Invention

[0013] The aforementioned problems and needs are addressed by a memory device comprising: a plurality of non-volatile memory cells, each non-volatile memory cell including a first gate and a controller. The controller is configured to program one of the plurality of non-volatile memory cells by: programming the non-volatile memory cell to an initial program state corresponding to reaching or exceeding a target threshold voltage of the first gate of the non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current; reading the non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell to generate a first read current, the read voltage being less than the target threshold voltage; and subjecting the non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current.

[0014] A method for programming one of a plurality of nonvolatile memory cells is also disclosed, wherein each of the plurality of nonvolatile memory cells includes a first gate. The method includes: programming the nonvolatile memory cell to an initial program state, the initial program state corresponding to reaching or exceeding a target threshold voltage of the first gate of the nonvolatile memory cell, wherein the target threshold voltage corresponds to a target read current; reading the nonvolatile memory cell in the first read operation using a read voltage applied to the first gate of the nonvolatile memory cell to generate a first read current, the read voltage being less than the target threshold voltage; and subjecting the nonvolatile memory cell to additional programming in response to determining that the first read current is greater than the target read current.

[0015] Other objects and features of the invention will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0016] Figure 1 This is a side cross-sectional view of an existing memory cell.

[0017] Figure 2 This is a diagram showing the components of a memory device.

[0018] Figure 3 This is a flowchart illustrating the steps for programming memory cells.

[0019] Figure 4 This is a flowchart illustrating the steps of a first alternative embodiment for programming a memory cell.

[0020] Figure 5 This is a flowchart illustrating the steps of a second alternative embodiment for programming a memory cell. Detailed Implementation

[0021] This invention is used for programming Figure 1 This technique involves compensating for RTN (Record-Time Negative) in memory cells of a certain type to improve read operation accuracy. The programming compensation technique involves detecting memory cells in the memory array that exhibit RTN exceeding a predetermined tolerance level, and accordingly compensating for the programming of those memory cells.

[0022] Programmable compensation techniques are implemented as part of the controller configuration of the memory array, and can be used to compensate for, for, Figure 2 This is better understood in the architecture of the exemplary memory device shown. The memory device includes an array 50 of non-volatile memory cells 10, which can be divided into two separate planes (plane A 52a and plane B 52b). The memory cells 10 can be... Figure 1 Memory cells of the type shown can be formed on a single chip and can be arranged in multiple rows and columns in semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g., XDEC 54), source line drivers (e.g., SLDRV 56), column decoders (e.g., YMUX 58), high-voltage row decoders (e.g., HVDEC 60), and bit line controllers (e.g., BLINHCTL 62), which are used to decode addresses and supply various voltages to the gates and regions of the various memory cells during read, program, and erase operations of the selected memory cells. Column decoder 58 includes a sense amplifier containing circuitry for measuring the current on the bit lines during read operations. Controller 66 (containing control circuitry) controls various device elements to perform each operation (programming, erasing, reading) on ​​the target memory cell. Charge pump CHRGPMP 64 provides various voltages for reading, programming, and erasing memory cells under the control of controller 66. Controller 66 is configured to operate the memory device to program, erase, and read memory cells 10. As part of these operations, controller 66 can be provided with access to incoming data (which is data to be programmed into memory cells), as well as programming, erasing, and reading commands provided on the same or different lines. Data read from the memory array is provided as outgoing data.

[0023] The programming compensation technique involves controller 66 implementing memory cell programming, and specifically, providing additional programming for memory cells exhibiting unacceptable levels of read current instability. This technique involves initially programming the memory cells to a specific programming state, and adjusting the memory cell threshold voltage parameter (i.e., the voltage level required to achieve a certain source / drain current level, referred to as the target current I). target The minimum voltage applied to the memory cell is measured once or multiple times. A preferred threshold voltage parameter is Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate 22. Specifically, the control gate threshold voltage Vtcg is the voltage on the control gate that, when a read potential for a read operation is applied to the select gate 24 and the drain region 16, makes the channel region a conductive path, thereby allowing a predetermined amount of read current (I0) to flow through the channel region. target The memory cell is treated as on (e.g., 1µA). The control gate threshold voltage Vtcg will vary with the programming state of the memory cell, but it is expected that any change in Vtcg over time will be less than a predetermined amount once the memory cell is programmed to a specific programming state.

[0024] Figure 3 The diagram illustrates an implementation of a programming technique that programs memory cells into a specific programming state, such that they possess a target threshold voltage Vtcg. target The technique begins in step 1, where a memory cell (e.g., having...) is... Figure 1 The memory cell 10, as shown in the configuration, is programmed. As described above, this programming operation preferably involves applying a programming voltage to the memory cell 10 for a finite time (i.e., within one or more pulses), which causes electrons to be injected into the floating gate 20. In step 2, a read operation is performed, which involves applying a read operation voltage to the memory cell 10 and measuring the current flowing through the channel region 18 of the memory cell 10. In this read operation, the voltage Vcg applied to the control gate 22 is the target threshold voltage Vtcg. target In step 3, based on the read operation in step 2, it is determined whether the threshold voltage Vtcg of the memory cell has reached or exceeded the target threshold voltage Vtcg. target (i.e., channel current I) read Is it less than or equal to the target current I? target , where I read Equal to target current I target The threshold voltage Vtcg of the instruction memory cell reaches the target threshold voltage Vtcg. target If it is determined to be no (i.e., the threshold voltage Vtcg is not greater than or equal to, that is, less than, the target threshold voltage Vtcg). targetIn step 4, optionally increase the voltage on the control gate Vcg used for programming, and then repeat step 1. Repeat steps 1-4 in sequence until the threshold voltage Vtcg of the memory cell, which was determined in step 3, has reached or exceeded the target threshold voltage Vtcg. target (i.e., channel current I) read Less than or equal to the target current I target Up to this point, the memory cell is considered to be initially programmed to its desired programming state (i.e., programmed to its target threshold voltage Vtcg). target Regular programming usually ends at this point.

[0025] However, for the purposes of this invention, the programming state achieved in steps 1-4 is merely an initial programming state that may require additional programming. Specifically, if the programmed memory cell exhibits RTN, the electrons trapped in the interface trap contribute to the measured threshold voltage Vtcg of the memory cell as part of the programming. If the electrons are emitted from the interface trap after programming is complete, or if electrons are emitted from the interface trap after programming is complete, the threshold voltage Vtcg may decrease by more than ΔVtcg. max And below the target threshold voltage Vtcg target , where ΔVtcg max This is the maximum permissible read error in terms of Vtcg variation. The threshold voltage decreases by more than ΔVtcg. max This is considered an unacceptable error during the read operation. Therefore, according to the present invention, once a read operation confirms that the target threshold voltage Vtcg has been initially reached... target (In step 3), then in step 5, the memory cell is read again, but this time the control gate voltage Vcg used is less than the target threshold voltage Vtcg used in step 2. target Specifically, the control gate voltage Vcg used for this read operation is Vtcg. target -ΔV tcg , where ΔV tcg It is a relatively small quantity and can be defined by the maximum tolerable read error. As a non-restrictive example, ΔV tcg It can be equal to ΔVtcg max And Vtcg max It also depends on the specific product and its application, and can be, for example, 20mV. In step 6, the read current I is determined according to the read operation in step 5. read Is it greater than the target read current I? target If the memory cell does not exhibit an unacceptable RTN, then a slight decrease in the control gate voltage Vcg during a read operation should reduce the read current I. read Further down to below I targetAnd the determination in step 6 should be no. In this case, the memory cell can be considered correctly programmed. However, if the memory cell does exhibit unacceptable RTN, and if interface trap electron emission exists before or during the read operation, the threshold voltage Vtcg of the memory cell will drop, causing the read current I to... read Increase. If the increase in current exceeds I... target Then the memory cell undergoes another round of programming starting from step 4, and is read again to confirm that it has been fully programmed.

[0026] The advantage of the above technique is that if a memory cell exhibits an unacceptable RTN, it will ultimately be more deeply programmed than it would have been otherwise (i.e., a higher Vtcg). This means that even if electron emission occurs, the memory cell threshold voltage Vtcg is unlikely to drop below the target threshold voltage Vtcg. target Exceeding the tolerance level ΔVtcg max This is because the deeper the memory cell is programmed, above Vtcg... target Future read operations will more accurately reflect the expected programming state of memory cells within the tolerance level of ΔVtcg variation.

[0027] The inventors have determined that, in some embodiments, better results can be obtained by repeating steps 5 and 6 if the initial determination in step 6 is negative. This increases the likelihood of identifying whether a memory cell exhibits an unacceptable RTN and therefore should undergo additional programming. Therefore, if the initial determination in step 6 based on the first read operation in step 5 is negative, steps 5 and 6 are optionally repeated in steps 7 and 8 so that the first read operation (step 5) does not result in a read current greater than I. target In this case, use Vcg = Vtcg target - ΔVtcg reads the memory cell a second time (step 7), and if I is determined in step 8 read More than I target Then return to programming. If less than Vtcg is used twice... target Vcg reads the memory unit and I read Both times remained at I target The memory cell is then assumed to be correctly programmed to the target voltage Vtcg. target And the programming was completed. Furthermore, although... Figure 3 The diagram shows a single repetition of steps 5 and 6, but in some implementations, even further improvements can be achieved if steps 5 and 6 are repeated as many times as the user decides to perform them, thus if Vcg = Vtcg is used. targetAny single read operation of -ΔVtcg causes the read current I to be... read More than I target Then the memory cell undergoes further programming.

[0028] Figure 4 A first alternative embodiment is shown, which is consistent with the description above and Figure 3 The method shown is the same, except that step 3A is added after step 3. Specifically, once the memory cell is initially programmed to reach its target threshold voltage Vtcg... target (Upon confirmation in step 3), a negative voltage is applied to the memory cell (e.g., to the control gate, erase gate, and / or select gate). This negative voltage applied to the memory cell induces an electric field stress on the gate oxide of the memory cell, thereby stimulating electrons to detach from the oxide traps at and near the interface (emission). Preferably, the negative voltage is applied to the control gate, but additionally or alternatively, the negative voltage can be applied to any gate or terminal capacitively coupled to the floating gate. Thus, for a memory cell with oxide traps that generate RTN, the negative voltage will stimulate electron detachment, setting the threshold voltage Vtcg to a lower Vt state, and increasing the likelihood that the confirmation in step 6 will be positive (and therefore the memory cell will undergo additional programming). Due to the unstable behavior of RTN, a defective memory cell may remain in a Vtcg state during all read operations, thus making it impossible to correctly identify whether it has undergone additional programming. Therefore, applying a negative voltage (e.g., -1V to -7V) before the read operation in step 5 will stimulate the memory cell with RTN to exhibit a lower Vt state, which will then be identified in step 6 for additional programming, thereby improving programming efficiency and accuracy. There are characteristic times during which the memory cell “retains” its Vt state acquired under the applied voltage stress after the applied voltage stress is removed. Therefore, the delay between the application of the negative voltage in step 3A and the read operation in step 5 should preferably not be longer than the typical electron capture and emission time (e.g., 100 ms at room temperature), otherwise applying a negative voltage before the read operation may be less effective.

[0029] Figure 5 A second alternative embodiment is shown, which is similar to the one described above and Figure 4 The method of the first alternative embodiment shown is the same, except that a negative voltage is applied not only immediately before the initial read operation in step 5, but also again before each repeated read operation in step 5 (see step 7, which repeats steps 3A and 5, instead of as shown). Figure 4 The diagram shows only the repetition of step 5.

[0030] It should be understood that the invention is not limited to the embodiments described above and shown herein, but covers any and all variations falling within the scope of any of the claims. For example, references to the invention herein are not intended to limit the scope of any claims or claim terminology, but only to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and numerical values ​​described above are merely exemplary and should not be construed as limiting the claims. Furthermore, as will be apparent from the claims and description, not all method steps need to be performed in the specific order shown or required (unless otherwise stated). A single layer of material may be formed as multiple layers of such or similar materials, and vice versa. As used herein, the terms “forming” and “formed” should include material deposition, material growth, or any other technique used to provide the disclosed or claimed material. An example of the threshold voltage Vt used in the above techniques is Vtcg, which is the threshold voltage of a memory cell viewed from control gate 22. However, the above techniques may be implemented relative to the threshold voltage Vt when viewed from any one or more non-floating gates in the memory cell. Finally, the invention can be implemented with a higher threshold voltage Vt than… Figure 1 It is implemented in memory cell arrays with fewer gates (e.g., no erase gate and / or control gate combined with select gate).

Claims

1. A memory device comprising: a plurality of non-volatile memory cells, each non-volatile memory cell comprising a first gate; and a controller configured to program one of the plurality of non-volatile memory cells by: programming the one non-volatile memory cell to an initial program state, the initial program state corresponding to reaching or exceeding a target threshold voltage of the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell to generate a first read current, the read voltage being less than the target threshold voltage, in response to determining that the first read current is greater than the target read current, subjecting the one non-volatile memory cell to additional programming; in response to determining that the first read current is not greater than the target read current in the first read operation, reading the one non-volatile memory cell in a second read operation using a read voltage applied to the first gate of the one non-volatile memory cell to generate a second read current, the read voltage being less than the target threshold voltage, and in response to determining that the second read current is greater than the target read current, subjecting the one non-volatile memory cell to additional programming.

2. The device of claim 1, wherein each of the plurality of non-volatile memory cells further comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending between the source and drain regions; a floating gate disposed vertically above and insulated from a first portion of the channel region; and a select gate disposed vertically above and insulated from a second portion of the channel region; wherein for each of the plurality of non-volatile memory cells, the first gate is disposed vertically above and insulated from the floating gate.

3. The device of claim 2, wherein each of the plurality of non-volatile memory cells further comprises: an erase gate disposed above and insulated from the source region.

4. The device of claim 1, wherein the controller is configured to perform programming the one non-volatile memory cell to the initial program state by: applying at least one first program voltage pulse to the one non-volatile memory cell; reading the one non-volatile memory cell using a read voltage applied to the first gate of the one non-volatile memory cell to generate a second read current, the read voltage being equal to the target threshold voltage; and and applying at least one second program voltage pulse to the one non-volatile memory cell in response to determining that the second read current is greater than the target read current.

5. The apparatus of claim 4, wherein a voltage applied to the first gate as part of the second program voltage pulse is greater than a voltage applied to the first gate as part of the first program voltage pulse.

6. The apparatus of claim 1, wherein each non-volatile memory cell of the plurality of non-volatile memory cells includes a second gate, and wherein the controller is further configured to apply a negative voltage to the second gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation.

7. The apparatus of claim 1, wherein the controller is further configured to apply a negative voltage to the first gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation.

8. The apparatus of claim 1, wherein each non-volatile memory cell of the plurality of non-volatile memory cells includes a second gate, and wherein the controller is further configured to: apply a negative voltage to the second gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation; and apply a negative voltage to the second gate of the one non-volatile memory cell after determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

9. The apparatus of claim 1, wherein the controller is further configured to: apply a negative voltage to the first gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation; and apply a negative voltage to the first gate of the one non-volatile memory cell after determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

10. A method of programming one non-volatile memory cell of a plurality of non-volatile memory cells, wherein each non-volatile memory cell of the plurality of non-volatile memory cells includes a first gate, the method comprising: programming the one non-volatile memory cell to an initial program state, the initial program state corresponding to reaching or exceeding a target threshold voltage of the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell to generate a first read current, the read voltage being less than the target threshold voltage, reading the one non-volatile memory cell in a second read operation using a second read voltage applied to the first gate of the one non-volatile memory cell to generate a second read current, the second read voltage being greater than the target threshold voltage, and subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current, reading the one non-volatile memory cell in a second read operation using a read voltage applied to the first gate of the one non-volatile memory cell to generate a second read current in response to determining that the first read current is not greater than the target read current in the first read operation, the read voltage being less than the target threshold voltage, and subjecting the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current.

11. The method of claim 10, wherein each non-volatile memory cell of the plurality of non-volatile memory cells further comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending between the source and drain regions; a floating gate disposed vertically above and insulated from a first portion of the channel region; and a select gate disposed vertically above and insulated from a second portion of the channel region; wherein for each non-volatile memory cell of the plurality of non-volatile memory cells, the first gate is disposed vertically above and insulated from the floating gate.

12. The method of claim 11, wherein each non-volatile memory cell of the plurality of non-volatile memory cells further comprises: an erase gate disposed above and insulated from the source region.

13. The method of claim 10, wherein programming the one non-volatile memory cell to the initial program state comprises: applying at least one first program voltage pulse to the one non-volatile memory cell; reading the one non-volatile memory cell using a read voltage applied to the first gate of the one non-volatile memory cell to generate a second read current, the read voltage being equal to the target threshold voltage; and in response to determining that the second read current is greater than the target read current, applying at least one second program voltage pulse to the one non-volatile memory cell.

14. The method of claim 13, wherein a voltage applied to the first gate as part of the second program voltage pulse is greater than a voltage applied to the first gate as part of the first program voltage pulse.

15. The method of claim 10, wherein each non-volatile memory cell of the plurality of non-volatile memory cells comprises a second gate, the method further comprising: applying a negative voltage to the second gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and prior to the first read operation.

16. The method of claim 10, further comprising: ​ applying a negative voltage to the first gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation.

17. The method of claim 10, wherein each non-volatile memory cell of the plurality of non-volatile memory cells includes a second gate, the method further comprising: applying a negative voltage to the second gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation; and applying a negative voltage to the second gate of the one non-volatile memory cell after determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

18. The method of claim 10, further comprising: applying a negative voltage to the first gate of the one non-volatile memory cell after programming the one non-volatile memory cell to the initial program state and before the first read operation; and applying a negative voltage to the first gate of the one non-volatile memory cell after determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

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