Division operation method, divider, storage medium and electronic device

Abstract

The embodiment of the application discloses a division operation method, a divider, a storage medium and an electronic device, and relates to the field of numerical operation. In the process of performing the division operation, multiple quotient bits are generated in each iteration, a divisor reference table is configured according to the quotient bits of each iteration and the divisor, and the final quotient is obtained by iterating the dividend according to the divisor reference table. Compared with the prior art in which one quotient bit is generated in each iteration, the embodiment of the application can realize the effect that the larger the number of quotient bits is, the smaller the amount of calculation is, and therefore the speed and efficiency of the division operation can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of numerical operation, in particular to a division operation method, a divider, a storage medium and an electronic device. BACKGROUND

[0002] In the current chip design, division operation is inevitable. Most self-designed dividers are based on the consideration of timing, area and performance, and usually adopt a cycle algorithm based on subtraction. The characteristic of this algorithm is that one quotient bit is generated each cycle, and the number of cycles is determined by the number of operation bits of the division. For example: to perform a 64-bit division, 64 iterations of subtraction operation are required to obtain the final quotient. The number of operations is too large, which increases the operation time and consumes computing resources. SUMMARY

[0003] The embodiments of the present application provide a division operation method, a divider, a storage medium and an electronic device, which can solve the problem of low efficiency caused by too many division operations in the prior art. The technical solution is as follows:

[0004] In a first aspect, the embodiments of the present application provide a division operation method, which comprises:

[0005] obtaining a dividend X and a divisor Y; wherein the number of bits of the dividend is M, the number of bits of the divisor is N, Z quotient bits are generated each iteration, and Z=2 n , n is an integer greater than 1;

[0006] If M is not an integer multiple of Z, the highest bit of X is padded with 0 until the number of bits is an integer multiple of Z; wherein the number of bits of the dividend after padding with 0 is P, and P is an integer greater than 2;

[0007] generating a divisor reference table by preprocessing the divisor Y according to Z; wherein the divisor reference table comprises n+1 reference numbers; wherein the n+1 reference numbers are Y0=Y*0, Y1=Y*1, Y2=Y*2, …, Y n-1 =(2 Z -1)*Y, Y n =(2 Z *Y;

[0008] configuring a counter; wherein the maximum value of the counter is P / Z, and the initial value of the counter is A, A=P / Z;

[0009] For the P-bit dividend X, multiple iteration calculations are performed according to the following process:

[0010] In the execution of the current iteration calculation, the dividend updated in the last iteration calculation is taken as the current dividend;

[0011] intercept [P-1, (A-1)*Z] bits of the current dividend as the current intercept B;

[0012] find i value satisfying Y i ≤B<Y i+1 in the divisor reference table according to the current intercept, convert the i value into binary number and assign it to [(A*Z-1), ((A-1)*Z)] bits of the temporary quotient, and determine the remainder R of the current dividend according to the i value, R=B-Y i ;

[0013] decrement the current count value of the counter by 1;

[0014] if the updated count value is equal to 0, end the iterative calculation;

[0015] if the updated count value is not equal to 0, replace [P-1, A*Z] bits of the current dividend X with the value of the current remainder R to obtain the next dividend;

[0016] after the iterative calculation is completed, take the quotient and the remainder obtained in the last iterative calculation as the final quotient and the final remainder of X / Y.

[0017] In the second aspect, the embodiments of the present application provide a divider, the device comprises:

[0018] an obtaining unit, configured to obtain a dividend X and a divisor Y; wherein the bit number of the dividend is M, the bit number of the divisor is N, Z=2 n bits of quotient are generated in each iterative calculation, n is an integer greater than 1;

[0019] a padding unit, configured to pad the highest bit of X with 0 until the bit number is an integer multiple of Z if M is not an integer multiple of Z; wherein the bit number of the dividend after padding with 0 is P, P is an integer greater than 2;

[0020] a generating unit, configured to generate a divisor reference table according to pre-processing of the divisor Y according to Z; wherein the divisor reference table comprises n+1 reference numbers; wherein the n+1 reference numbers are Y0=Y*0, Y1=Y*1, Y2=Y*2, …, Y n-1 =(2 Z -1)*Y, Y n =(2 Z *Y respectively.

[0021] a configuring unit, configured to configure a counter; wherein the maximum value of the counter is P / Z, and the initial value of the counter is A, A=P / Z;

[0022] an iterative unit, configured to perform multiple iterative calculations on the P-bit dividend X according to the following process:

[0023] In the execution of the present iteration calculation, the last iteration calculation updated dividend is taken as the current dividend;

[0024] The [P-1, (A-1)*Z] bits of the current dividend are taken as the current intercept B;

[0025] According to the current intercept, the i value satisfying Y i ≤B<Y i+1 is found in the divisor reference table, the i value is converted into a binary number and assigned to the [(A*Z-1), ((A-1)*Z)] bits of the temporary quotient, and the remainder R of the current dividend is determined according to the i value, i.e., R=B-Y i ;

[0026] The current count value of the counter is reduced by 1;

[0027] If the updated count value is equal to 0, the iteration calculation is ended;

[0028] If the updated count value is not equal to 0, the value of the current remainder R is replaced with the [P-1, A*Z] bits of the current dividend X to obtain the next dividend;

[0029] The output unit is used to output the quotient and the remainder obtained in the last iteration calculation as the final quotient and the final remainder of X / Y after the iteration calculation is completed.

[0030] In a third aspect, the embodiments of the present application provide a computer storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and performing the method steps described above.

[0031] In a fourth aspect, the embodiments of the present application provide an electronic device, which can include a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and performing the method steps described above.

[0032] The technical solutions provided by some embodiments of the present application have at least the following beneficial effects:

[0033] Each iteration generates a plurality of quotient bits, the divisor reference table is configured according to the quotient bits of each iteration and the divisor, and the final quotient is obtained by iterating the dividend according to the divisor reference table. Compared with the prior art in which one quotient bit is generated in each iteration, the present application can achieve the effect that the larger the number of quotient bits is, the less the calculation amount is, and thus the speed and efficiency of the starting operation can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0035] Figure 1 is a flowchart of a division operation method provided by an embodiment of the present application;

[0036] Figure 2 is a flowchart of iterative calculation provided by an embodiment of the present application;

[0037] Figure 3 is a structural diagram of a divider provided by the present application;

[0038] Figure 4 is a structural diagram of a divider provided by the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0040] The following will combine the drawings to describe the embodiments of the present application in detail. Figure 1 The division operation method provided by the embodiments of the present application will be described in detail.

[0041] Please refer to Figure 1 The present application provides a flowchart of a division operation method. As shown in Figure 2 , the method of the present application can include the following steps:

[0042] S101, obtaining a dividend X and a divisor Y.

[0043] Wherein, the dividend X and the divisor Y are converted into binary numbers, the bit number of the dividend is M, the bit number of the divisor is N, Z bits of quotient are generated by each iteration, and Z = 2 n , n is an integer greater than 1. When performing the division operation of the present application, multiple iterations are needed to obtain the final quotient, and the number of Z can be set according to the performance and speed requirements of the divider. Further, the bit number of the dividend X and the divisor Y in the embodiments of the present application can be configured according to actual requirements.

[0044] S102, if M is not an integer multiple of Z, the highest bit of X is padded with 0 until the bit number is an integer multiple of Z.

[0045] Wherein, the bit number of the complemented dividend is P, P is an integer greater than 2; if M is an integer of Z, the complemented dividend is not complemented, and the M-bit dividend is directly used for the division operation.

[0046] S103, generating a divisor reference table according to the pre-processing of the divisor Y according to Z.

[0047] Wherein, the divisor reference table includes n+1 reference numbers, and the n+1 reference numbers are respectively Y0=Y*0, Y1=Y*1, Y2=Y*2, …, Y n-1 = Y*(2 Z -1), Y n = Y*2 Z .

[0048] For example, when Z=2, two quotient bits are generated each time, and the pre-configured divisor reference table is shown in Table 1:

[0049] [B-Y0] just just just just [B-Y1] just just just burden [B-Y2] just just burden burden [B-Y3] just burden burden burden [B-Y4] burden burden burden burden Commercial output 11 10 01 00 New dividend X [B-Y3] [B-Y2] [B-Y1] [B-Y0]

[0050] Table 1 When Z=4, four quotient bits are generated each time, and the pre-configured divisor reference table is shown in Table 2:

[0051] [B-Y0] just just just just just just just just just just just just just just just just [B-Y1] just just just just just just just just just just just just just just just burden [B-Y2] just just just just just just just just just just just just just just burden burden [B-Y3] just just just just just just just just just just just just just burden burden burden [B-Y4] just just just just just just just just just just just just burden burden burden burden [B-Y5] just just just just just just just just just just just burden burden burden burden burden [B-Y6] just just just just just just just just just just burden burden burden burden burden burden [B-Y7] just just just just just just just just just burden burden burden burden burden burden burden [B-Y8] just just just just just just just just burden burden burden burden burden burden burden burden [B-Y9] just just just just just just just burden burden burden burden burden burden burden burden burden B-Y 10 ]] just just just just just just burden burden burden burden burden burden burden burden burden burden B-Y 11 ]]> just just just just just burden burden burden burden burden burden burden burden burden burden burden B-Y 12 ]] just just just just burden burden burden burden burden burden burden burden burden burden burden burden B-Y 13 ]] just just just burden burden burden burden burden burden burden burden burden burden burden burden burden B-Y 14 ]] just just burden burden burden burden burden burden burden burden burden burden burden burden burden burden B-Y 15 ]]> just burden burden burden burden burden burden burden burden burden burden burden burden burden burden burden Commercial output 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 dividend B-Y 15 ]]> B-Y 14 ]]> B-Y 13 ]] B-Y 12 ]]> B-Y 11 ]]> B-Y 10 ]]> [B-Y9] [B-Y8] [B-Y7] [B-Y6] [B-Y5] [B-Y4] [B-Y3] [B-Y2] [B-Y1] [B-Y0]

[0052] Table 2

[0053] S104, configuring a counter.

[0054] Wherein, the maximum value of the counter is P / Z, and the initial value of the counter is A, A=P / Z;

[0055] S105, for the P-bit dividend X, performing multiple iteration calculations.

[0056] Wherein, the iteration process is shown in Figure 3 :

[0057] S1051, taking the updated dividend of the last iteration calculation as the current dividend.

[0058] Wherein, in the first iteration calculation, the current dividend is the complemented P-bit dividend.

[0059] S1052, taking [P-1, (A-1)*Z] bits of the current dividend as the current intercept number B;

[0060] S1053, according to the current intercept number, finding out the reference number Y i ≤B<Y i+1the i value is converted into a binary number and assigned to the [(A*Z-1), ((A-1)*Z)] bit of the temporary quotient, and the remainder R of the current dividend is determined according to the i value i .

[0061] S1054, the current count value of the counter is reduced by 1.

[0062] S1055, it is judged whether the updated count value is equal to 0.

[0063] If the judgment result is no, S1056 is executed; if the judgment result is yes, S1057 is executed.

[0064] S1056, the value of the current remainder R is replaced with the [P-1, A*Z] bit of the current dividend X to obtain the next dividend.

[0065] S1057, the iterative calculation is ended.

[0066] S106, after the iterative calculation is completed, the quotient and the remainder obtained by the last iterative calculation are taken as the final quotient and the final remainder of X / Y.

[0067] The division operation process of the present application is described below with two specific examples:

[0068] Example 1: assuming that the dividend is 010011011 and the divisor is 0111, 2 quotient bits are generated by each iterative calculation.

[0069] Preprocessing: the dividend X has M=9 bits and the divisor Y has N=4 bits, and Z=2 quotient bits are generated by each iterative calculation. For the 9 bits of the dividend X, which is not a multiple of 2, the highest bit of X is padded with 0 to the multiple of Z, and the new dividend X has P=10 bits. According to the value of Z, the divisor Y is preprocessed to generate a divisor reference table (Y0=Y*0=0, Y1=Y*1=0111, Y2=Y*2=1110, Y3=Y*((2^Z)-1)=Y*3=10101, Y4=Y*(2^Z)=11100), which can be obtained by means of shifting addition. A counter is set, and the maximum value of the counter is P / Z=10 / 2=5, and the initial value A=P / Z=5.

[0070] The first iterative calculation includes:

[0071] Taking the number: for the P-bit dividend X, [P-1, (A-1)*Z]=[9, 8] bits of the dividend are taken as B, and B=00.

[0072] Compare: Compare B to the divisor reference table to get Y0≤B<Y1, i.e., i=0, which in binary is 00. Set the quotient's [(A*Z-1),((A-1)*Z)] = [9:8] to 00, and the remainder R is B-Y0 = 00.

[0073] Count: Subtract 1 from the counter to get a new A value of 4. Since the updated A value is not equal to 0, replace the divisor's [P-1,A*Z] = [9:8] bits with the value of the remainder R to get a new divisor X = 0010011011. Perform a 2nd iteration.

[0074] 2nd iteration includes:

[0075] Fetch: For a P-bit divisor X, fetch the divisor's [P-1,(A-1)*Z] = [9,6] bits as B, B = 0010

[0076] Compare: Compare B to the divisor reference table to get Y0≤B<Y1, i.e., i=1, which in binary is 00. Set the quotient's [(A*Z-1),((A-1)*Z)] = [7:6] to 00, and the remainder R is B-Y0 = 0010.

[0077] Count: Subtract 1 from the counter to get a new A value of 3. Since the updated A is not equal to 0, replace the divisor's [P-1,A*Z] = [9:6] bits with the value of the remainder R to get a new divisor X = 0010011011. Perform a 3rd iteration.

[0078] 3rd iteration includes:

[0079] Fetch: For a P-bit divisor X, fetch the divisor's [P-1,(A-1)*Z] = [9,4] bits as B, B = 001001.

[0080] Compare: Compare B to the divisor reference table to get Y1≤B<Y2, i.e., i=1, which in binary is 01. Set the quotient's [(A*Z-1),((A-1)*Z)] = [5:4] to 01, and the remainder R is B-Y1 = 000010.

[0081] Count: Subtract 1 from the counter to get a new A value of 2. Since the updated A is not equal to 0, replace the divisor's [P-1,A*Z] = [9:4] bits with the value of the remainder R to get a new divisor X = 0000101011. Perform a 4th iteration.

[0082] 4th iteration includes:

[0083] Take: For P-bit dividend X, take out [P-1, (A-1)*Z] = [9, 2] bits of the dividend as B, B = 00001010

[0084] Compare: Compare the value of B with the divisor reference table, get Y1≤B<Y2, that is, i = 1, converted to binary number is 01, at this time [(A*Z-1), ((A-1)*Z)] = [3:2] of quotient Q is assigned to 01, the remainder R is B-Y1 = 00000011.

[0085] Count: The value of the counter is reduced by 1 to get a new A value of 1, the updated A is not equal to 0, the value of the remainder R replaces [P-1, A*Z] = [9:2] bits of the dividend X to get a new dividend X = 0000001111, and the 5th iteration calculation is performed.

[0086] The 5th iteration calculation includes:

[0087] Take: For P-bit dividend X, take out [P-1, (A-1)*Z] = [9, 0] bits of the dividend as B, B = 0000001111

[0088] Compare: Compare the value of B with the divisor reference table, get Y2≤B<Y3, that is, i = 2, converted to binary number is 10, at this time [(A*Z-1), ((A-1)*Z)] = [1:0] of quotient Q is assigned to 10, the remainder R is B-Y2 = 0000000001.

[0089] Count: The value of the counter is reduced by 1 to get a new A value of 0, the updated A is equal to 0, and the iteration calculation is ended.

[0090] Output result: When the iteration calculation is ended, the quotient Q = 00010110 and the remainder R = 00000001 at this time are the results of X / Y.

[0091] Example 2: Assuming the dividend is 010011011 and the divisor is 0111, 4 quotient bits are generated each time.

[0092] Preprocessing: The dividend X has M = 9 bits, the divisor Y has N = 4 bits, and Z = 4 quotient bits are generated each time. For the 9 bits of the dividend X, which is not a multiple of 4, the highest bit of X needs to be padded with 0 to a multiple of Z, and the new dividend X has P = 12 bits. According to the value of Z, the divisor Y is preprocessed to generate the divisor reference table (Y0 = Y*0 = 0, Y1 = Y*1 = 0111, Y2 = Y*2 = 1110, Y3 = Y*3 = 10101, Y4 = Y*4 = 11100, Y5 = Y*5 = 100011, Y6 = Y*6 = 101010, Y7 = Y*7 = 110001, Y8 = Y*8 = 111000, Y9 = Y*9 = 111111, Y10 = Y * 10 = 1000110, Y 11 = Y * 11 = 1001101, Y 12 = Y * 12 = 1010100, Y 13 = Y * 13 = 1011011, Y 14 = Y * 14 = 1100010, Y 15 = Y * (2 4 - 1) = Y * 15 = 1101001, Y 16 = Y * 2 4 = 1110000), the reference table can be obtained by means of shift addition. Set a counter, the maximum value of the counter is P / Z = 12 / 4 = 3, the current value is A, and A = P / Z = 3 initially.

[0093] First iteration calculation:

[0094] Taking number: for the P-bit dividend X, take out the [P-1, (A-1)*Z] = [11, 8] bits of the dividend as B, B = 0000.

[0095] Comparison: compare the B value with the divisor reference table to obtain Y0≤B<Y1, that is, i = 0, converted into a binary number is 0000, at this time the [(A*Z-1), ((A-1)*Z)] = [11:8] of the quotient Q is assigned as 0000, and the remainder R is B-Y0 = 0000.

[0096] Counting: subtract 1 from the value of the counter to obtain the new A value as 2, and the updated A is not equal to 0, the value of the remainder R replaces the [P-1, A*Z] = [11:8] bits of the dividend X to obtain the new dividend X = 000010011011, and the second iteration calculation is performed.

[0097] Second iteration calculation:

[0098] Taking number: for the P-bit dividend X, take out the [P-1, (A-1)*Z] = [11, 4] bits of the dividend as B, B = 00001001.

[0099] Comparison: compare the B value with the divisor reference table to obtain Y1≤B<Y2, that is, i = 1, converted into a binary number is 0001, at this time the [(A*Z-1), ((A-1)*Z)] = [7:4] of the quotient Q is assigned as 0001, and the remainder R is B-Y1 = 00000010.

[0100] Counting: the value of the counter is reduced by 1 to obtain a new A value of 1, if A is equal to 0, jump to step 5, if A is not equal to 0, replace the value of the remainder R with [P-1, A*Z] = [11:4] bits of the dividend X to obtain a new dividend X = 000000101011, and perform the third iteration calculation.

[0101] Third iteration calculation:

[0102] Taking data: for the P-bit dividend X, take out [P-1, (A-1)*Z] = [11, 0] bits of the dividend as B, B = 000000101011.

[0103] Comparison: compare the value of B with the divisor reference table to obtain Y6≤B<Y7, i-6, converted to binary number is 0110, at this time [(A*Z-1), ((A-1)*Z)] = [3:0] of quotient Q is assigned to 0110, and the remainder R is B-Y6 = 000000000001.

[0104] Counting: the value of the counter is reduced by 1 to obtain a new A value of 0, and the updated A is equal to 0, ending the iteration calculation.

[0105] Output result: when the iteration calculation is finished, the quotient Q = 00010110 and the remainder R = 00000001 at this time are the results of X / Y.

[0106] In one or more possible embodiments, the i value satisfying Y i ≤B<Y i+1 in the divisor reference table according to the current intercept is determined by:

[0107] Calculate the difference values of B-Y0, B-Y1, B-Y2, …, B-Y n in turn; when the calculated difference value is less than 0, stop calculating the subsequent difference values, and determine the i value according to the serial number of the difference value less than 0, so as to avoid calculating all the difference values, and improve the calculation speed.

[0108] Further, the method further comprises:

[0109] Loading the divisor reference table into the memory, and the processor directly queries the divisor reference table in the memory when performing the division operation of the application, which can improve the query speed and efficiency.

[0110] Further, before triggering the operation by using the dividend X and the divisor Y, it is determined that the dividend is not equal to 0 and the dividend is greater than the divisor, so as to avoid inputting incorrect numerical values.

[0111] Further, if the dividend is equal to 0 or the divisor Y is greater than the output X, an error prompt is given to prompt the user that the divisor is invalid.

[0112] Further, for each division operation, the iteration number, operation time, memory occupation rate, and CPU occupation rate are counted, and a log file is generated and saved according to the counting results, so as to subsequently locate and optimize the bottleneck of the division operation by using the log file.

[0113] Embodiments of the present application provide an unsigned divider, which generates a plurality of quotient bits in each iteration, configures a divisor reference table according to the quotient bits in each iteration and the divisor, and iterates the dividend according to the divisor reference table to obtain a final quotient. Compared with the prior art in which one quotient bit is generated in each iteration, the present application can achieve the effect that the more the quotient bits, the less the calculation amount, and thus the speed and efficiency of the operation can be improved.

[0114] The following is an apparatus embodiment of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the apparatus embodiments of the present application, refer to the method embodiments of the present application.

[0115] Please refer to Figure 3 which shows a structure diagram of a divider provided by an exemplary embodiment of the present application, hereinafter referred to as apparatus 3. The apparatus 3 can be realized by software, hardware or a combination of both to become all or part of the divider. The apparatus 3 comprises an acquisition unit 301, a padding unit 302, a generation unit 303, a configuration unit 304, an iteration unit 305 and an output unit 306.

[0116] The acquisition unit 301 is configured to acquire a dividend X and a divisor Y; wherein the bit number of the dividend is M, the bit number of the divisor is N, Z quotient bits are generated in each iteration calculation, and Z = 2 n n is an integer greater than 1;

[0117] The padding unit 302 is configured to pad the highest bit of X with 0 until the bit number is an integer multiple of Z if M is not an integer multiple of Z; wherein the bit number of the dividend after padding with 0 is P, and P is an integer greater than 2.

[0118] The generation unit 303 is configured to generate a divisor reference table by preprocessing the divisor Y according to Z; wherein the divisor reference table comprises n+1 reference numbers; wherein the n+1 reference numbers are Y0=Y*0, Y1=Y*1, Y2=Y*2, …, Y n-1 = Y*(2 Z -1), Y n = Y*2 Z , respectively.

[0119] The configuration unit 304 is configured to configure a counter, wherein a maximum value of the counter is P / Z, and an initial value of the counter is A, A=P / Z.

[0120] The iteration unit 305 is configured to perform multiple iteration calculations on the divisor X of P bits according to the following process:

[0121] In performing the current iteration calculation, the divisor updated in the last iteration calculation is taken as a current divisor;

[0122] The [P-1, (A-1)*Z] bits of the current divisor are taken as a current intercept B;

[0123] An i value satisfying Y i ≤B<Y i+1 is found in the divisor reference table according to the current intercept, the i value is converted into a binary number and assigned to the [(A*Z-1), ((A-1)*Z)] bits of the temporary quotient, and a remainder R=B-Y i of the current divisor is determined according to the i value;

[0124] The current count value of the counter is reduced by 1;

[0125] If the updated count value is equal to 0, the iteration calculation is ended;

[0126] If the updated count value is not equal to 0, the [P-1, A*Z] bits of the current divisor X are replaced by the value of the current remainder R, and a next divisor is obtained;

[0127] The output unit 306 is configured to take the quotient and the remainder obtained in the last iteration calculation as the final quotient and the final remainder of X / Y after completing the multiple iteration calculations.

[0128] In one or more possible embodiments, n=1 or 2.

[0129] In one or more possible embodiments, the i value satisfying Y i ≤B<Y i+1 is found in the divisor reference table according to the current intercept, including:

[0130] The differences B-Y0, B-Y1, B-Y2, …, B-Y n are calculated in sequence;

[0131] When the calculated difference is less than 0, the subsequent difference is stopped from being calculated, and the i value is determined according to the serial number of the difference less than 0.

[0132] In one or more possible embodiments, the pre-processing of the divisor Y according to Z to generate the divisor reference table further includes:

[0133] The divisor reference table is loaded into memory.

[0134] In one or more possible embodiments, the acquisition unit 301 is further configured to:

[0135] It is determined that the dividend is not equal to 0 and that the dividend is greater than the divisor.

[0136] In one or more possible embodiments, the acquisition unit 301 is further configured to:

[0137] If the dividend is equal to 0, an error message will be displayed.

[0138] In one or more possible embodiments, it also includes:

[0139] The statistics unit is used to track the number of iterations, computation time, memory usage, and CPU usage for each division operation.

[0140] Generate a log file based on the statistical results, and save the log file.

[0141] It should be noted that the device 3 provided in the above embodiments is only illustrated by the division of the above functional modules when performing the division operation method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the above functions. In addition, the divider and the division operation method embodiments provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiments, which will not be repeated here.

[0142] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0143] This application also provides a computer storage medium that can store multiple instructions, which are adapted to be loaded and executed by a processor as described above. Figure 1 The method steps of the illustrated embodiment can be found in the following documentation for detailed execution. Figure 1 The specific details of the illustrated embodiments will not be elaborated here.

[0144] This application also provides a computer program product that stores at least one instruction, which is loaded and executed by the processor to implement the division operation method as described in the above embodiments.

[0145] Please see Figure 4 The diagram below provides a structural schematic of a divider according to an embodiment of this application. Figure 4As shown, the divider 400 can include at least one processor 401, at least one communication interface 404, a counter 403, a memory 405, at least one communication bus 402.

[0146] The communication bus 402 is configured to realize the connection and communication between the components.

[0147] The counter 403 is configured to configure a maximum count value and an initial count value.

[0148] The communication interface 404 is configured to communicate with external units, devices or equipment, and can include standard wired interfaces, wireless interfaces (such as WI-FI interfaces).

[0149] The processor 401 can include one or more processing cores. The processor 401 connects various parts in the divider 400 through various interfaces and lines, executes various functions of the divider 400 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 405, and calling data stored in the memory 405. Optionally, the processor 401 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 401 can be integrated with a combination of one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU is mainly used to process operating systems, user interfaces and application programs; the GPU is used to render and draw the content to be displayed on the display screen; and the modem is used to process wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor 401, but can be realized by a separate chip.

[0150] The memory 405 may include random access memory (RAM) or read-only memory. Optionally, the memory 405 may include a non-transitory computer-readable storage medium. The memory 405 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 405 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 405 may also be at least one storage device located remotely from the aforementioned processor 401. Figure 4 As shown, the memory 405, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.

[0151] exist Figure 4 In the divider 400 shown, the user interface 403 is mainly used to provide an input interface for the user and obtain the user input data; while the processor 401 can be used to call the application program stored in the memory 405 and specifically execute, such as Figure 1 The method shown can be referred to for details. Figure 1 As shown, it will not be elaborated further here.

[0152] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0153] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A method of division operation applied in a divider, the divider being implemented by hardware, characterized in that, comprises: obtaining a dividend X and a divisor Y; wherein the number of bits of the dividend is M, the number of bits of the divisor is N, and each iteration produces Z quotient bits, Z = 2 n , n is an integer greater than or equal to 1; if M is not an integer multiple of Z, padding the highest bits of X with 0 until the number of bits is an integer multiple of Z; wherein the number of bits of the padded dividend is P, and P is an integer greater than 2; A divisor reference table is generated by preprocessing the divisor Y based on Z; wherein the divisor reference table includes 2 Z +1 reference number; wherein, the 2 Z +1 reference numbers are: Y0=Y*0, Y1=Y*1, Y2=Y*2, ..., Y n-1 =Y*(2 Z -1)Y n =Y*2 Z ; configuring a counter; wherein the maximum value of the counter is P / Z, and the initial value of the counter is A, A=P / Z; for a P-bit dividend X, performing multiple iteration calculations according to the following process: in performing the current iteration calculation, taking the dividend updated in the last iteration calculation as the current dividend; extracting [P-1, (A-1)*Z] bits of the current dividend as the current extraction B; According to the current intercept number, find the i value satisfying Y i ≤ B < Y in the divisor reference table, convert the i value to a binary number and assign it to the [(A*Z-1), ((A-1)*Z)] bit of the temporary quotient, and determine the remainder R = B-Y of the current dividend according to the i value i+1 i ;​ decrementing the current count value of the counter by 1; if the updated count value is equal to 0, ending the iteration calculation; if the updated count value is not equal to 0, replacing [P-1, A*Z] bits of the current dividend X with the value of the current remainder R to obtain the next dividend; after completing the multiple iteration calculations, taking the quotient and the remainder obtained in the last iteration calculation as the final quotient and the final remainder of X / Y.

2. The method of claim 1, wherein, n=1 or 2.

3. The method according to claim 1 or 2, characterized in that, The step of querying the divisor reference table according to the current intercept number to obtain an i value satisfying Y i ≤ B < Y i+1 includes: B-Y0, B-Y1, B-Y2,..., B-Y n the difference values; When the calculated difference value is less than 0, stop calculating subsequent difference values, and determine the value of i according to the serial number of the difference value less than 0.

4. The method of claim 3, wherein, The pre-processing of the divisor Y according to Z to generate the divisor reference table further comprises: loading the divisor reference table into the memory.

5. The method according to claim 1 or 2 or 4, characterized in that, Further comprising: determining that the dividend is not equal to 0 and the dividend is greater than the divisor.

6. The method of claim 5, wherein, Further comprising: if the dividend is equal to 0, an error prompt is performed.

7. The method according to claim 1 or 2 or 4 or 6, characterized in that, Further comprising: statistically counting the iteration number, operation time, memory occupancy rate, and CPU occupancy rate of each division operation; generating a log file according to the statistical results, and saving the log file.

8. A divider implemented in hardware, characterized by comprises: An acquisition unit is configured to acquire a dividend X and a divisor Y; wherein the number of bits of the dividend is M, the number of bits of the divisor is N, and each iteration calculation produces Z quotient bits, Z=2 n , n is an integer greater than or equal to 1. a padding unit, configured to pad the highest bits of X with 0 until the number of bits is an integer multiple of Z if M is not an integer multiple of Z; wherein the number of bits of the padded dividend is P, and P is an integer greater than 2; The generating unit is configured to generate a divisor reference table according to Z and pre-process the divisor Y; wherein the divisor reference table includes 2 Z +1 reference numbers; wherein the 2 Z +1 reference numbers are respectively Y0=Y*0, Y1=Y*1, Y2=Y*2, …, Y n-1 =(Y*2 Z -1), Y n =(Y*2 Z ). a configuration unit, configured to configure a counter; wherein the maximum value of the counter is P / Z, and the initial value of the counter is A, A=P / Z; an iteration unit, configured to perform multiple iteration calculations for a P-bit dividend X according to the following process: in performing the current iteration calculation, taking the dividend updated in the last iteration calculation as the current dividend; extracting [P-1, (A-1)*Z] bits of the current dividend as the current extraction B; According to the current intercept number, find the i value satisfying Y i ≤B<Y i+1 in the divisor reference table, convert the i value to a binary number and assign it to the [(A*Z-1), ((A-1)*Z)] bit of the temporary quotient, and determine the remainder R=B-Y i of the current dividend according to the i value. decrementing the current count value of the counter by 1; if the updated count value is equal to 0, ending the iteration calculation; if the updated count value is not equal to 0, replacing [P-1, A*Z] bits of the current dividend X with the value of the current remainder R to obtain the next dividend; an output unit, configured to take the quotient and the remainder obtained in the last iteration calculation as the final quotient and the final remainder of X / Y after completing the multiple iteration calculations.

9. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions, which are suitable for being loaded and executed by the processor, and perform the method steps of any one of claims 1-7.

10. An electronic device, comprising: comprises: a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded and executed by the processor, and performs the method steps of any one of claims 1-7.

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