Memory subsystem address mapping

Abstract

This application relates to memory subsystem address mapping. A method includes accessing a first memory component of a memory subsystem via a first interface, accessing a second memory component of the memory subsystem via a second interface, and transferring data between the first memory component and the second memory component via the first interface. The method further includes initially writing data to the first memory component via a first address window, and accessing data in the second memory component via a second address window in response to caching the data in the first memory component to the second memory component, wherein caching the data in the first memory component to the second component includes changing an address of the data from the first address window to the second address window.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory subsystem address mapping. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a method comprising: accessing a first memory component of a memory subsystem via a first interface; accessing a second memory component of the memory subsystem via a second interface; and transferring data between the first memory component and the second memory component via the first interface.

[0004] Another aspect of this disclosure provides an apparatus comprising: a memory subsystem address mapping component configured to: access data located in a first address window at a first memory component of the memory subsystem via a first interface; access data located in a second address window at a second memory component of the memory subsystem via a second interface; and access data located in the second address window at the first memory component of the memory subsystem via the first interface.

[0005] Another aspect of this disclosure provides an apparatus comprising: a memory subsystem address mapping component configured to: write data in a first address window to a first memory component of the memory subsystem via a first interface; wherein, in response to data in a second address window being associated with a lower performance attribute, the data is held in the first address window on the first memory component; and wherein, in response to data in the first address window being associated with a higher performance attribute, the data is remapped to a second address window. Attached Figure Description

[0006] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0009] Figure 3This is a block diagram of an instance address window for memory subsystem address mapping according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of an instance address window for memory subsystem address mapping according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart corresponding to a method for memory subsystem address mapping according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to memory subsystem data address mapping, and more specifically, to a memory subsystem including a memory subsystem address mapping component. The memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). The following is combined with… Figure 1 And other examples describing storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0014] The memory subsystem may comprise several layers of memory, such as a first layer containing volatile memory (e.g., DRAM on an RDIMM module) and a second layer containing non-volatile memory (e.g., storage class memory (SCM)). The first layer of memory can be used in kernel space, first-level user space, and as a cache for the second-level memory. The second-level memory can be used in second-level user space that can be cached in the first-level memory.

[0015] The second-level memory can store applications with lower performance attributes (e.g., latency and bandwidth requirements), while the first-level memory can store applications with higher performance attributes. The first-level memory is coupled to the second-level memory via a first interface, and the first-level memory is coupled to the host system via a second interface. The second interface that couples the first-level memory to the host system is configured to accommodate the higher performance attributes of the data stored in the first-level memory. The host system can access the second-level memory, which stores data with lower performance attributes, via the first-level memory. However, these accesses use the second interface adapted for higher performance, which is inefficient because access to the second-level memory stores data with lower performance attributes and does not require the higher performance provided by the second interface.

[0016] This disclosure addresses the above and other shortcomings by providing the host system with access to the second-level memory via a first interface. The memory subsystem includes direct access to the second-level memory via several channels on the first interface. The first interface is configured to accommodate the lower performance characteristics of data stored in the second-level memory, while allowing the host to access the first-level memory using only the second interface.

[0017] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, compute fast link (CXL) attachments, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes, for example, electrical connections, optical connections, magnetic connections, etc.

[0021] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0022] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0023] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] While non-volatile memory components, such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory devices 130 and / or 140.

[0032] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] Memory subsystem 110 may include address mapping component 113. Although Figure 1Not shown, but for the sake of clarity, address mapping component 113 may include various circuitry systems to facilitate address mapping of memory subsystems and / or components of memory subsystems, determine the location of accessing and storing data in memory subsystems and / or components of memory subsystems based on performance attributes of data in memory subsystems and / or components of memory subsystems, and / or control address mapping of memory subsystems and / or components of memory subsystems. In some embodiments, address mapping component 113 may include dedicated circuitry systems in the form of ASICs, FPGAs, state machines, and / or other logic circuitry systems that allow address mapping component 113 to arrange and / or perform operations based on performance attributes of data in memory subsystems and / or components of memory subsystems to selectively perform address mapping operations for memory devices 130 and / or memory devices 140.

[0034] In some embodiments, the memory subsystem controller 115 includes at least a portion of the address mapping component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the address mapping component 113 is part of the host system 110, an application program, or an operating system.

[0035] In a non-limiting example, the device (e.g., computing system 100) may include a memory subsystem address mapping component 113. The memory subsystem address mapping component 113 may reside on a memory subsystem 110. As used herein, the term "resides on" means that something is physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry including the memory subsystem address mapping component 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0036] The memory subsystem address mapping component 113 can be configured to map data accessible only by the host system to a first address window via a first interface, and to map data accessible by the host system to a second address window via either the first or second interface. The address mapping component 113 can be configured to map data to the first address window when the data is stored only in the second-level memory, thus allowing the host system to directly access the data from the second-level memory via the first interface. The address mapping component 113 can also be configured to map data to the second address window when the data can be stored in either the first or second-level memory, thus allowing data to be accessed directly from the second-level memory via the first interface or directly from the first-level memory via the second interface.

[0037] The memory subsystem 115 may include a memory device 140 that can be a first-level memory and a memory device 130 that can be a second-level memory. The first-level memory of the memory device 140 can be used in kernel space, a first-level user space, and as a cache for the second-level memory. The second-level memory of the memory device 130 can be used in a second-level user space that can be cached in the first-level memory.

[0038] The second-level memory of memory device 130 can store applications with lower performance attributes (e.g., latency and bandwidth requirements), while the first-level memory of memory device 140 can store applications with higher performance attributes. The first-level memory of memory device 140 can be coupled to the second-level memory of memory device 130 via a first interface, and the first-level memory of memory device 140 can be coupled to a host system (e.g., [missing information]) via a second interface. Figure 2 (As shown in the diagram). A second interface coupling the first layer of memory of memory device 140 to host system 120 is configured to accommodate the higher performance attributes of data stored in the first layer of memory of memory device 140, while the first interface can provide host system 120 with direct access to the second layer of memory of memory device 130 to accommodate the lower performance attributes of data stored in the second layer of memory of memory device 130.

[0039] The memory subsystem address mapping component 113 is configured to allow the memory subsystem 110 to access data located in a first address window at the second-level memory of the memory device 130 via a first interface, access data located in a second address window at the first-level memory of the memory device 140 via a second interface, and access data located in the second address window at the second-level memory of the memory device 130 via the first interface. Data located in the first window can only be accessed in the second-level memory of the memory device 130 via the first interface. A portion of the first-level memory of the memory device 140 can be configured to cache data stored in the second-level memory of the memory device 130, and the memory subsystem address mapping component 113 can be configured to allow data located in the second address window to be transferred between the second-level memory of the memory device 130 and the first-level memory of the memory device 140 via the first interface.

[0040] The memory subsystem address mapping component 113 can be configured to check the first-level memory of the memory device 140 to determine whether data in a second address window that has been accessed by the first interface in the second-level memory of the memory device 130 is also stored in the first-level memory of the memory device 140. The memory subsystem address mapping component 113 can be configured to, in response to receiving a command to access data in the second address window of the second-level memory of the memory device 130 when data is also stored in the first-level memory of the memory device 140, refresh the data from the first-level memory of the memory device 140 to the second-level memory of the memory device 130.

[0041] The memory subsystem address mapping component 113 is configured to write data in the first address window to the second level memory of the memory device 130 via the first interface. In response to data being associated with a lower performance attribute compared to data in the second address window, the data remains in the first address window on the second level memory of the memory device 130, and in response to data being associated with a higher performance attribute compared to data in the first address window, the data is remapped to the second address window. In response to the data being remapped to the second address window, the data can be cached in the first level memory of the memory device 140 via the first interface, and the data in the second address window can be accessed on the first level memory of the memory device 140 via the second interface.

[0042] Address mapping component 113 can be configured to access data in a first address window of memory device 130 without interacting with the first layer of memory of memory device 140. Address mapping component 113 can also be configured to access data in a second address window of memory device 130 after data in a second address window of memory device 140 has been flushed to the second layer of memory of memory device 130. Address mapping component 113 can further be configured to access data in a second address window of memory device 130 in response to determining that data in the second address window is not located in the first layer of memory of memory device 140.

[0043] Figure 2 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure. Figure 2The system includes several interfaces 244-1, 244-2, 244-3, 244-4, 244-5, and 244-6, which couple components of the computing system together and allow the components of the computing system to transfer and access data through the interfaces 244-1, 244-2, 244-3, 244-4, 244-5, and 244-6. Interfaces 244-1, 244-2, 244-3, and 244-4 can couple memory device 230 to memory device 240, and interfaces 244-5 and 244-6 can couple host system 220 to memory device 230. The interfaces 244-1, 244-2, 244-3, 244-4, 244-5, and 244-6 may be compute fast link (CXL) interfaces. The computing system may be a compute fast link (CXL) compatible memory system (e.g., the memory system may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to enhance the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost.

[0044] With the increasing use of accelerators to supplement CPUs to support emerging applications such as artificial intelligence and machine learning, CXL is designed as an industry-open standard interface for high-speed communications. Built on the Peripheral Component Interconnect High Speed ​​(PCIe) infrastructure, CXL technology utilizes PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host to share memory with the accelerator), and coherence interfaces.

[0045] Figure 2The system includes several interfaces 246-1, 246-2, 246-3, and 246-4, which couple components of the computing system together and allow these components to transfer and access data through these interfaces. Interfaces 246-1, 246-2, 246-3, and 246-4 can couple host system 220 to memory device 240. Memory device 240 can be on dual in-line memory module (DIMM) 242. Interfaces 246-1, 246-2, 246-3, and 246-4 can be, for example, NVDIMM-P interfaces. Interfaces 244-1 and 246-1 may correspond to the first channel, interfaces 244-2 and 246-2 may correspond to the second channel, interfaces 244-3 and 246-3 may correspond to the third channel, interfaces 244-4 and 246-4 may correspond to the fourth channel, interface 244-5 may correspond to the fifth channel, and interface 244-6 may correspond to the sixth channel. Embodiments may include any number of interfaces (interfaces 244 and 246) and / or channels.

[0046] Memory device 230 is configured to store data accessible by host system 220 via interfaces 244-5 and 244-6 in a first address window. Interfaces 244-5 and 244-6 may be CXL interfaces and provide performance attributes corresponding to the latency and bandwidth requirements of the data stored in memory device 230. Memory devices 230 and 240 are configured to store data in a second address window, which may be accessed via interfaces 246-1, 246-2, 246-3, and 246-4 when located on memory device 240, or via interfaces 244-5 and 244-6 when located on memory device 230. Memory 240 is configured to cache data stored in memory device 230, and interfaces 244-1, 244-2, 244-3, and 233-4 are configured to transfer data between memory devices 230 and 240.

[0047] When accessing data in the first address window, the host system 220 can directly access the data from the memory device 230 via interfaces 244-5 and 244-6. When accessing data in the first address window, the address mapping components of the host system 220 and the memory system do not necessarily interact with the memory device 240, because the data in the first address window can be stored only in the memory device 230 and cannot be stored in the memory device 240.

[0048] When accessing data in the second address window, the host system 220 can access the data from the memory device 230 via interfaces 244-5 and 244-6, and can access the data from the memory device 240 via interfaces 246-1, 246-2, 246-3, and 246-4. The data in the second address window can be stored in both memory device 230 and memory device 240. Therefore, when accessing data in the second address window on memory device 230 via interfaces 244-5 and 244-6, the address mapping component can check whether the data is also located in memory device 240, and if the data is located in memory device 240, then the data is refreshed from memory device 240 to memory device 230. Furthermore, whenever data in the second address window is accessed by the host system 220 via interfaces 244-5 and 244-6, the data can be refreshed from memory device 240 to memory device 230.

[0049] The data stored in the second address window in memory device 230 may also include cache indicators (e.g., bits in metadata) indicating whether the data is cached in memory device 240. Therefore, when the data in the second address window of memory device 230 is accessed by host system 220 via interfaces 244-5 and 244-6, the cache indicators can be checked to determine whether the data needs to be refreshed from memory device 240 before being sent from memory device 230 to host system 220. If the data is cached in memory device 240, then memory device 240 can refresh the data to memory device 230 before sending it to host system 220. If the data is not cached in memory device 240, then memory device 230 can send the data to host system 220 without interacting with memory device 240.

[0050] When data is first written to memory device 230, it is initially written to a first address window. If the data is associated with a lower performance attribute, the address mapping remains unchanged because the data will not be cached in memory device 240, and the data can be accessed by host system 220 in the first address window only via interfaces 244-5 and 244-6. If the data is associated with a higher performance attribute, the address mapping is updated to a second address window because the data can be cached in memory device 240, and the data can be accessed by host system 220 in the second address window on memory device 230 via interfaces 244-5 and 244-6, or accessed on memory device 240 via interfaces 246-1, 246-2, 246-3, and 246-4 when cached in memory device 240.

[0051] Figure 3This is a block diagram of an instance address window for memory subsystem address mapping according to some embodiments of the present disclosure. Figure 3 A first address window 350 is shown. The first address window 350 is used when data is first written to memory device 330. Data in the first address window 350 can be stored only in memory device 330 and cannot be cached in another memory device, for example... Figure 2 The data in the first address window 350 can be accessed on the memory device 240 via the interface 344.

[0052] Figure 4 This is a block diagram of an instance address window for memory subsystem address mapping according to some embodiments of the present disclosure. Figure 4 A second address window 460 is shown. The second address window 460 can be used when data cacheable in memory device 440 is written to and / or accessed in memory device 430, or when data is written to and / or accessed in memory device 440 (e.g., kernel and / or user data in memory device 440 or data cached in memory device 440 from memory device 430). Data initially in the first address window and cacheable in memory device 440 can be remapped to the second address window 460. Data in the second address window 460 can be accessed on memory device 430 via interface 444, or the data can be accessed on memory device 440 via interface 446.

[0053] Figure 5 This is a flowchart corresponding to a method 570 for address mapping according to some embodiments of the present disclosure. Method 570 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 570 is performed by… Figure 1 The address mapping component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other process flows are possible.

[0054] At operation 572, a first memory component of the memory subsystem can be accessed via a first interface. In some embodiments, the memory subsystem may be similar to... Figure 1 The memory subsystem 110 shown is illustrated.

[0055] At operation 574, the second memory component of the memory subsystem can be accessed via the second interface. At operation 576, data can be transferred between the first memory component and the second memory component via the first interface.

[0056] In some embodiments, method 570 may include initially writing data to a first memory component via a first address window. Method 570 may include accessing data in a second memory component via a second address window in response to caching data in the first memory component to a second memory component, wherein caching data in the first memory component to the second component includes changing the address of the data from the first address window to the second address window. Method 570 may include checking the second memory component to determine whether the data is also stored in the second memory component in response to receiving a command to access data located in the first address window of the first memory component, and if the data is also stored in the second memory component, flushing the data from the second memory component to the first memory component in response to receiving a command to access data in the first memory component.

[0057] Figure 6 This is a block diagram of an example computer system 600 in which embodiments of the present disclosure may operate. For example, Figure 6 An example machine of computer system 600 is shown, wherein a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 The operation of address mapping component 113. In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0058] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute (one or more sets of) instructions to perform any one or more of the methods discussed herein.

[0059] The example computer system 600 includes a processing device 602 that communicates with each other via a bus 630, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618.

[0060] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication on network 620.

[0061] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein are stored. The instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, the main memory 604 and processing device 602 also constituting the machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0062] In one embodiment, instruction 626 includes instructions for implementing the address mapping component 613 (e.g., Figure 1 The address mapping component 113) contains instructions for the function of the machine-readable storage medium 624. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions that are executed by a machine and causing a machine to perform any one or more of the methods disclosed herein. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0063] Some parts of the previously described algorithms and symbolic representations of operations on data bits in computer memory have been presented. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for common use, it has proven convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0064] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage systems of a computer system.

[0065] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0066] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to execute the methods. Structures for various such systems will be presented as described below. Furthermore, embodiments of this disclosure are described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0067] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0068] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method comprising: initially writing a first portion of data and a second portion of data to a first memory component of a memory sub-system in a first address window; in response to the second portion of data being cacheable in a second memory component of the memory sub-system, changing an address mapping of the second portion of data from the first address window to a second address window; caching the second portion of data by transferring the second portion of data between the first memory component and the second memory component via a first interface; directly accessing the first portion of data and the second portion of data in the first memory component of the memory sub-system via the first interface; and directly accessing the second portion of data in the second memory component of the memory sub-system via a second interface.

2. The method of claim 1, further comprising accessing the second portion of data in the second memory component via the second address window in response to caching the second portion of data initially located in the first memory component to the second memory component.

3. The method of claim 1, further comprising in response to receiving a command to access the first portion of data located in the first address window in the first memory component, checking the second memory component to determine if the first portion of data is also stored in the second memory component.

4. The method of claim 3, further comprising flushing data from the second memory component to the first memory component in response to receiving the command to access the first portion of data in the first memory component when the first portion of data is also stored in the second memory component.

5. An apparatus comprising: a memory sub-system address mapping component configured to: initially write a first portion of data and a second portion of data to a first memory component of a memory sub-system in a first address window; in response to the second portion of data being cacheable in a second memory component of the memory sub-system, change an address mapping of the second portion of data from the first address window to a second address window; directly access the first portion of data located in the first address window at the first memory component of the memory sub-system via a first interface; in response to the second portion of data being cacheable in the second memory component, directly access the second portion of data located in the second address window at the second memory component of the memory sub-system via a second interface; and directly access the second portion of data located in the second address window at the first memory component of the memory sub-system via the first interface.

6. The apparatus of claim 5, wherein the memory sub-system address mapping component is configured to transfer data located in the second address window between the first memory component and the second memory component via the first interface. ​ ​ 7. The apparatus of claim 5, wherein the memory subsystem address mapping component is configured to check the second memory component to determine if data in the second address window that has been accessed in the first memory component by the first interface is also stored in the second memory component.

8. The apparatus of claim 7, wherein the memory subsystem address mapping component is configured to flush data from the second memory component to the first memory component in response to receiving a command to access data in the second address window in the first memory component when the data is also stored in the second memory component.

9. The apparatus of claim 5, wherein a portion of the second memory component is configured to cache data stored in the first memory component.

10. The apparatus of any one of claims 5-9, wherein data located in the second address window is associated with an application having a higher performance attribute than data located in the first address window.

11. The apparatus of any one of claims 5-9, wherein data located in the first window is accessed only at the first memory component via the first interface.

12. An apparatus comprising: a memory subsystem address mapping component configured to: write data to a first memory component of a memory subsystem in a first address window; wherein in response to the data being associated with a lower performance attribute than data in a second address window, the data remains in the first address window on the first memory component; wherein the data in the first address window is directly accessed on the first memory component via a first interface; wherein in response to the data being associated with a higher performance attribute than data in the first address window, the data is remapped to the second address window; wherein in response to the data being remapped to the second address window, the data is cached in a second memory component; and wherein data in the second address window is directly accessed on the second memory component via a second interface.

13. The apparatus of claim 12, wherein the address mapping component is configured to access the data in the first address window on the first memory component without interacting with the second memory component.

14. The apparatus of claim 12, wherein the address mapping component is configured to access the data in the second address window on the second memory component after the data in the second address window on the second memory component is flushed to the first memory component.

15. The apparatus of claim 12, wherein the address mapping component is configured to access the data in the second address window on the first memory component in response to determining that the data in the second address window is not located on a second memory component.

16. The apparatus of claim 12, wherein the performance attribute includes latency and bandwidth.

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