Bit line pre-charge circuit and chip for ultra-high speed NVM read access

Abstract

The application discloses a bit line pre-charge circuit and chip for super-speed NVM reading channel, which comprises a full pull-up pre-charge circuit connected with a bit line, a pull-up circuit and a potential equalization circuit; the full pull-up pre-charge circuit is used for charging the bit line to a pre-charge voltage in a pre-charge stage; the pull-up circuit is used for pulling up the bit line to the pre-charge voltage in a non-reading operation; the potential equalization circuit is arranged between a first bit line and a second bit line, and is used for controlling the first bit line voltage and the second bit line voltage to keep equal during the charging process of the full pull-up pre-charge circuit to the bit line; the first bit line is a bit line of a selected storage unit, and the second bit line is a bit line of a corresponding reference storage unit. By using the application, the bit line can be quickly charged, the reading period is shortened, and the high-speed reading application requirement of the super-speed NVM is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a bit line pre-charge circuit for super-speed NVM read path and a chip. BACKGROUND

[0002] With the rapid development of mobile Internet, super-speed non-volatile memory (NVM) has become the direction of customer consumption needs. More and more application fields require the read speed of embedded flash (eFlash) to be less than 10ns, for example, the application in the field of automotive electronics usually requires high-speed reading of 7ns-10ns.

[0003] The read operation of NVM such as flash memory generally consists of four processes: (1) address decoding; (2) bit line pre-charge; (3) bit line differentiation process; (4) read amplification and output. Among them, the proportion of (1) and (4) is not large, (2) and (3) often account for most of the proportion, so optimizing (2) and (3) stages can speed up the readout speed.

[0004] The speed of bit line pre-charge is the key to determine the speed of bit line differentiation process. In order to achieve the fastest bit line differentiation process, the bit line usually selects a high voltage state to increase the current of the storage unit, for example, the bit line selects a logic level of 1.2V (i.e. VDD12) instead of a medium pre-charge voltage value of 0.4V-0.6V. Because the bit line voltage is high, the traditional bit line pre-charge circuit structure cannot complete the full pre-charge process in a very short time. SUMMARY

[0005] The embodiment of the present application provides a bit line pre-charge circuit for super-speed NVM read path and a chip, so as to realize the rapid charging of the bit line, shorten the time of read cycle, and meet the application demand of high-speed reading of super-speed NVM.

[0006] To this end, the embodiment of the present application provides the following technical scheme:

[0007] On the one hand, the embodiment of the present application provides a bit line pre-charge circuit for super-speed NVM read path, which comprises: a full pull-up pre-charge circuit connected with a bit line, a pull-up circuit, and a potential equalization circuit; the bit line is selected by a column selection circuit in a pre-charge stage;

[0008] The full pull-up pre-charge circuit is used for charging the bit line to a pre-charge voltage in the pre-charge stage;

[0009] The pull-up circuit is used for pulling up the bit line to the pre-charge voltage in a non-reading operation;

[0010] The potential equalization circuit is arranged between the first bit line and the second bit line, and is configured to control the first bit line voltage and the second bit line voltage to be equal during the charging of the bit line by the full pull-up pre-charge circuit, the first bit line being a bit line of a selected memory cell, and the second bit line being a bit line of a corresponding reference memory cell.

[0011] Optionally, the column selection circuit comprises a single-stage low-voltage PMOS transistor.

[0012] Optionally, the column selection circuit is controlled by a column address decoding signal YENB_B, the full pull-up pre-charge circuit is controlled by a pre-charge timing control signal ATD_B, and the pull-up circuit is controlled by a pull-up control signal SENB.

[0013] Optionally, the circuit further comprises a pull-down circuit configured to pull down the bit line to 0 voltage after the read operation is completed.

[0014] Optionally, the pull-down circuit is controlled by the column address decoding signal YENB_B.

[0015] Optionally, the full pull-up pre-charge circuit is a PMOS transistor, a source of the PMOS transistor is connected to a pre-charge voltage source, a gate of the PMOS transistor inputs the pre-charge timing control signal ATD_B, and a drain of the PMOS transistor is connected to the bit line as a voltage output end of the bit line.

[0016] Optionally, the pull-up circuit is a PMOS transistor, a source of the PMOS transistor is connected to the pre-charge voltage source, a gate of the PMOS transistor inputs the pull-up control signal SENB, and a drain of the PMOS transistor is connected to the voltage output end of the bit line.

[0017] Optionally, the potential equalization circuit is a PMOS transistor, a gate of the PMOS transistor inputs the pre-charge timing control signal ATD_B, a drain of the PMOS transistor is connected to the voltage output end INA of the first bit line, and a source of the PMOS transistor is connected to the voltage output end INB of the second bit line.

[0018] Optionally, the pull-down circuit is an NMOS transistor, a gate of the NMOS transistor inputs the column address decoding signal YENB_B, a source of the NMOS transistor is grounded, and a drain of the NMOS transistor is connected to a drain of a single-stage low-voltage PMOS transistor in the column selection circuit of the same bit line.

[0019] Optionally, the pull-up control signal SENB is high during a read operation period and is low during a non-read operation.

[0020] Optionally, the pre-charge voltage is 1.2 V.

[0021] Optionally, the pre-charge voltage source is a logic voltage source.

[0022] In another aspect, the embodiments of the present application also provide a chip comprising the bit line pre-charge circuit for super-speed NVM read path as described above.

[0023] The bit line pre-charge circuit for super-speed NVM read path and the chip provided by the embodiments of the present application can pull up the bit line voltage to the pre-charge voltage by the pull-up circuit during the non-reading operation, charge the bit line by the full pull-up pre-charge circuit during the pre-charge phase, and control the first bit line voltage and the second bit line voltage to keep equal by the potential equalization circuit arranged between the first bit line and the second bit line. By the pull-up circuit, the bit line can be pulled up to the pre-charge voltage in advance, so that a larger storage cell read current can be obtained by using a higher pre-charge voltage, the bit line differentiation speed is improved, and the storage cell read speed is further improved.

[0024] Further, based on the above structure, in the bit line pre-charge circuit provided by the embodiments of the present application, the column selection circuit can adopt a single-stage low-voltage PMOS. Compared with the multi-stage column selection circuit composed of medium-voltage tubes or even high-voltage tubes in the traditional bit line pre-charge circuit, the parasitic capacitance of the column selection circuit is smaller, so that the overall capacitance load on the pre-charge path is reduced, and because the decoding signal does not need to undergo level conversion, a faster bit line pre-charge speed can be achieved.

[0025] The bit line pre-charge circuit for super-speed NVM read path and the chip provided by the embodiments of the present application have simple circuit design and do not require complex timing control requirements, and have high working reliability. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a schematic diagram of a traditional bit line pre-charge circuit structure;

[0027] Figure 2 is a principle block diagram of the bit line pre-charge circuit for super-speed NVM read path provided by the embodiments of the present application;

[0028] Figure 3 is a specific structure diagram of the bit line pre-charge circuit for super-speed NVM read path provided by the embodiments of the present application;

[0029] Figure 4 is a dynamic comparator auxiliary pre-charge circuit structure diagram provided by the embodiments of the present application;

[0030] Figure 5 is Figure 2 , Figure 3 and Figure 4 involved in each signal timing diagram. DETAILED DESCRIPTION

[0031] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following provides a detailed description of specific embodiments of the present invention with reference to the accompanying drawings.

[0032] First, a brief description of the traditional bit-line precharge circuit is given below. As Figure 1 shown, the structure of the traditional bit-line precharge circuit is as Figure 1 shown. Among them, BL is the bit line, which has a large parasitic capacitance. The precharge process is the process of charging the capacitance on the bit line to a set potential. The bit selection circuit 101 is composed of two or three stages of N-type transmission devices. ATD is a timing control signal. During the precharge stage, the bit-line precharge circuit 102 is turned on, and the bit line is charged by the precharge voltage source 120. At the end of the precharge stage, the bit-line precharge circuit 102 is turned off, and then a read operation is performed. The reference current source 104 is used to compare with the current of the selected storage unit to distinguish between data 0 and 1. After the complete read operation is completed, the IO pull-down circuit 103 is turned on to pull down BL to the 0 potential.

[0033] For ultra-high-speed Flash specifications (such as on the order of 10 ns or even faster), it is necessary to complete a sufficient precharge process within an extremely short time, while the traditional precharge structure cannot meet this requirement. The main reasons are as follows:

[0034] First, on the precharge path, from the input end of the storage unit to the input end of the bit-line differential comparator of the readout circuit, the default state is 0 level (VSS). Therefore, it takes a long charging time from the VSS state to VDD12 (+1.2V), including the charging of the bit line itself, the turning on and conduction of the bit selection circuit, etc.

[0035] Second, when using, for example, 1.8V N-type medium-voltage transistors, such as N-channel field-effect transistors (NFETs), to form the bit selection circuit, affected by the device threshold voltage Vth, the transmission path cannot effectively charge the bit line to a higher state, 1.8V - Vth < VDD12. If the VDD12 voltage is to be effectively transmitted, the bit selection circuit needs to use medium-voltage or high-voltage transistors and raise the gate control voltage to a higher level. In this case, a level shifter (LS) must be preposed, and the presence of LS reduces the decoding speed of the bit selection circuit. Based on the traditional design of the bit selection circuit, in the fastest case of the precharge process, the decoding speed of the bit selection circuit is at least above 3 ns.

[0036] Therefore, Figure 1 the structure of the traditional bit-line precharge circuit shown cannot meet the design requirements of ultra-high-speed Flash.

[0037] Considering that bit line fast charging is a key factor restricting the overall fast read speed of NVM, and the problems existing in the structure of the existing bit line pre-charge circuit, this embodiment of the invention provides a bit line pre-charge circuit for ultra-high speed NVM read path, which can obtain a larger memory cell read current by using a higher pre-charge voltage, improve bit line differentiation speed, and thus improve memory cell read speed.

[0038] like Figure 2 The diagram shown is a schematic block diagram of the bit line precharge circuit for an ultra-high-speed NVM read path according to an embodiment of the present invention.

[0039] The bit line pre-charge circuit includes: a full pull-up pre-charge circuit, a pull-up circuit, and a potential equalization circuit connected to the bit line; the bit line is selected by a column selection circuit during the pre-charge phase. Wherein:

[0040] The full pull-up pre-charge circuit is used to charge the bit line to the pre-charge voltage during the pre-charge phase.

[0041] The pull-up circuit is used to pull the bit line to the pre-charge voltage during non-read operations.

[0042] The potential equalization circuit, located between the first bit line BL and the second bit line REFBL, is used to control the voltage of the first bit line (i.e., REFBL) during the charging process of the bit line by the full pull-up pre-charge circuit. Figure 2 The voltage at the INA terminal and the second bit line voltage (i.e., Figure 2 The voltage at the INB terminal remains equal. The first bit line BL is the bit line of the selected memory cell, and the second bit line REFBL is the bit line of the corresponding reference memory cell.

[0043] In this embodiment, the target pre-charge voltage value for the bit line is VDD, which is the aforementioned pre-charge voltage. In specific applications, VDD can be greater than or equal to 1.2V.

[0044] like Figure 2 As shown, the column selection circuit is controlled by the column address decoding signal YENB_B, the full pull-up precharge circuit is controlled by the precharge timing control signal ATD_B, and the pull-up circuit is controlled by the pull-up control signal SENB. The timing of these signals is referenced... Figure 5 As shown.

[0045] Throughout the entire read cycle, for selected bit lines, the corresponding column address decoding signal YENB_B is low, enabling the pre-charge voltage to be transmitted on the bit lines; for unselected bit lines, the corresponding column address decoding signal YENB_B is high.

[0046] During the whole read cycle, the pull-up control signal SENB is high, so that the pull-up path is turned off; during the non-reading operation, the pull-up control signal SENB is low, so that the default state of the first bit line voltage and the second bit line voltage is pulled to the pre-charge target voltage value VDD.

[0047] During the pre-charge phase, the pre-charge timing control signal ATD_B is low, so that the full pull-up pre-charge circuit is turned on to charge the bit line; after the pre-charge phase ends, the pre-charge timing control signal ATD_B becomes high, so that the full pull-up pre-charge circuit is turned off.

[0048] In the bit line pre-charge circuit of the embodiment, the bit line can be pulled up to the pre-charge voltage in advance through the pull-up circuit, so that a larger storage unit read current can be obtained by using a higher pre-charge voltage, the bit line differentiation speed is improved, and the storage unit read speed is further improved. Further, due to the action of the pull-up circuit, in the embodiment, the column selection circuit can adopt a single-stage low-voltage PMOS tube, the parasitic capacitance of the column selection circuit is smaller, so that the overall capacitance load on the pre-charge path is reduced, and because the decoding signal does not need to be subjected to level conversion, a faster bit line pre-charge speed can be achieved.

[0049] As shown in Figure 2 , the bit line pre-charge circuit further includes a pull-down circuit for pulling down the bit line to 0 level after the reading operation ends, and the pull-down circuit is controlled by the column address decoding signal YENB_B.

[0050] In specific applications, the full pull-up pre-charge circuit, the potential equalization circuit and the pull-up circuit can all adopt PMOS tubes, and the pull-down circuit can adopt an NMOS tube to be implemented.

[0051] Figure 2 The reference current module in the embodiment has the same function as the reference current source in the existing memory read circuit, and is used as a reference to compare with the current of the storage unit, so as to distinguish data 0 and 1.

[0052] It should be noted that, Figure 2 As shown in the circuit, it is a full-symmetrical sensitive current amplifier structure, and the left and right sides are respectively connected to the bit line BL and the REFBL of the upper and lower two storage arrays, and WL_TOP and WL_BOT are respectively the row selection lines of the selected storage units in the upper and lower two storage arrays.

[0053] As shown in Figure 3 , it is a specific structure diagram of the bit line pre-charge circuit for the super-high-speed NVM read path provided by the embodiment of the application.

[0054] Wherein, PMOS MP2 and MP5 are full pull-up pre-charge circuits of BL and REFBL respectively, and the pre-charge target voltage value is VDD. The source of MP2 and MP5 is connected to the pre-charge voltage source VDD12, and the gate of MP2 and MP5 inputs the pre-charge timing control signal ATD_B; the drain of MP2 and MP5 is connected to the voltage output end INA and INB of the bit line BL and REFBL respectively, as the voltage output end of the bit line.

[0055] It should be noted that in practical application, the pre-charge voltage source VDD12 can use a logic voltage source directly as the charging source. The logic voltage source refers to the voltage source of the digital circuit part in the system. Of course, an analog voltage with sufficient driving ability can also be generated according to the specific voltage value, but an additional analog voltage generation circuit needs to be designed. Using the logic voltage source can meet the needs and make the design simple.

[0056] Wherein, PMOS MP6 is a potential equalization circuit corresponding to the bit line BL and REFBL. The gate of MP6 inputs the pre-charge timing control signal ATD_B, the drain of MP6 is connected to the voltage output end INA of the bit line BL, and the source of MP6 is connected to the voltage output end INB of the bit line REFBL.

[0057] Wherein, PMOS MP1 and MP4 are pull-up circuits of INA end and INB end respectively, the source of MP1 and MP4 is connected to the pre-charge voltage source VDD12, the gate of MP1 and MP4 inputs the pull-up control signal SENB, and the drain of MP1 and MP4 is connected to the voltage output end of the bit line BL and REFBL, that is, INA end and INB end in Figure 3 .

[0058] Wherein, PMOS MP0 and MP3 are column selection circuits of the bit line BL and REFBL respectively, the gate of MP0 and MP3 inputs the column address decoding signal YENB_B, the source of MP0 and MP3 is connected to the voltage output end INA and INB of the bit line BL and REFBL respectively, and the drain of MP0 and MP3 is connected to the input end of the storage unit on the bit line BL and REFBL. The column address decoding signal YENB_B can be obtained by column address decoding.

[0059] Wherein, NMOS MN0 and MN1 are pull-down circuits of the bit line BL and REFBL respectively, the gate of MN0 and MN1 inputs the column address decoding signal YENB_B, the source of MN0 and MN1 is grounded, and the drain of MN0 and MN1 is connected to the input end of the storage unit on the bit line BL and REFBL.

[0060] The timing diagram shown in Figure 5 will be further described in detail below. Figure 3The working process of the circuit.

[0061] For the selected bit line, YENB_B is low; for the unselected bit line and the reference bit line, YENB_B is high, and the corresponding unselected bit line and the reference bit line are pulled to 0 level.

[0062] The pull-up control signal SENB is high during the entire read cycle, and the pull-up path is turned off; when the non-reading operation is performed, the pull-up control signal SENB is low, and the default state of the INA end and the INB end is pulled to VDD12.

[0063] In the precharge phase, the precharge timing control signal ATD_B is low, so that MP2 and MP5 are turned on, and the bit line BL and the reference bit line REFBL are charged by the precharge power supply VDD12; after the charging is completed, the precharge timing control signal ATD_B becomes high, so that MP2 and MP5 are turned off, and the charging is stopped.

[0064] After entering the bit line differentiation phase, since the bit line BL is selected, the voltage of the voltage output end INA of the bit line BL is VDD12, and the voltage of the voltage output end INB of the reference bit line REFBL is pulled to 0 level by MN1.

[0065] The voltage output end INA of the bit line BL and the voltage output end INB of the reference bit line REFBL serve as two input ends of the next stage dynamic comparator.

[0066] It should be noted that the bit line precharge circuit for the ultra-high-speed NVM read path in the embodiment of the application can be adapted to various dynamic comparators, and the embodiment of the application is not limited in this regard.

[0067] Since the gate-source voltage VSG of the PMOS needs to reach a threshold voltage Vth to be turned on, if the source end starts charging from 0 level, the PMOS is not turned on during the time period from VSG=0V to VSG=Vth, and no current flows through the column selection circuit to effectively charge the bit line BL, which is a great waste for the design of the ultra-high-speed Flash. Therefore, in the embodiment of the application, the default state of other nodes on the precharge path, in addition to the bit line and the reference bit line, is designed to be a high potential state, for example, VDD12, and these nodes mainly include the input ends INA, INB of the dynamic comparator and some nodes inside the comparator, thereby reducing the turn-on time and the equalization time of the potential on the column selection circuit and the like. The equalization refers to equalizing the potentials of the nodes, because it is necessary to charge the nodes INA, INB, BL and REFBL to the same potential in the precharge phase.

[0068] Referring to Figure 4 It is a dynamic comparator auxiliary precharge circuit structure provided by the embodiment of the application.

[0069] The PMOS transistors P2 and P3 are pull-up circuits of the pre-charge nodes LCHA and LCHB in the comparator, and can be used as Figure 3 The pre-charge auxiliary circuit of the bit line pre-charge circuit shown in FIG. 2 further accelerates the bit line pre-charge process.

[0070] The gate input control signal SAPCH is input to the gates of the PMOS transistors P2 and P3, the sources of the PMOS transistors P2 and P3 are connected to the pre-charge power supply VDD12, the drain of the PMOS transistor P2 is the pre-charge node LCHA, and the drain of the PMOS transistor P3 is the pre-charge node LCHB.

[0071] It should be noted that the control signal SAPCH is the same as the pre-charge timing control signal ATD_B shown in FIG. 3, and the two are generated by the same signal source but are driven by different outputs. Figure 3

[0072] The control signal SAPCH is low during the pre-charge phase, and the PMOS transistors P2 and P3 are turned on to charge the pre-charge nodes LCHA and LCHB to the potential of VDD12.

[0073] Suppose that the pre-charge nodes LCHA and LCHB are initially at low potential, then at the beginning of the pre-charge phase, the INA end and the INB end will be instantaneously pulled low, which will cause the INA end and the INB end to take a longer time to reach a reasonable equipotential target. However, by using the pull-up circuits P2 and P3, this influence can be avoided.

[0074] The potential changes of the main nodes on the pre-charge path during the read cycle are shown in FIG. 4. Figure 5 As shown in FIG. 4, only the bit line and the reference bit line are at low potential by default, and the input INA and INB of the dynamic comparator and the internal nodes LCHA and LCHB of the dynamic comparator are all at high potential by default.

[0075] The bit line pre-charge circuit for the super-high-speed NVM read path provided by the embodiment of the application can obtain a larger storage cell read current by using a higher pre-charge voltage, improve the bit line differentiation speed, and further improve the storage cell read speed. Through testing, the bit line pre-charge circuit can improve the bit line pre-charge process from 3 ns to about 2 ns, and the 1 ns improvement is considerable for super-high-speed Flash.

[0076] Correspondingly, the embodiment of the application also provides a chip including the bit line pre-charge circuit for the super-high-speed NVM read path of the above-mentioned embodiments.

[0077] ​It should be understood that the term "and / or" in this text only describes the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this text represents an "or" relationship between the associated objects before and after it.

[0078] The "multiple" appearing in the embodiments of the present application means two or more.

[0079] The first, second, and the like appearing in the embodiments of the present application are only for illustrative and distinguishing purposes, and there is no order difference, nor do they represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0080] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A bit line pre-charge circuit for a super-speed NVM read path, characterized by, The circuit includes: a full pull-up pre-charge circuit, a pull-up circuit, and a potential equalization circuit connected to the bit line; the bit line is selected by a column selection circuit during the pre-charge phase. The full pull-up pre-charge circuit is used to charge the bit line to the pre-charge voltage during the pre-charge phase. The pull-up circuit is used to pull the bit line to the pre-charge voltage during non-read operations. The potential equalization circuit is disposed between the first bit line and the second bit line, and is used to control the voltage of the first bit line and the voltage of the second bit line to remain equal during the charging process of the bit line by the full pull-up pre-charge circuit. The first bit line is the bit line of the selected memory cell, and the second bit line is the bit line of the corresponding reference memory cell. The full pull-up precharge circuit is controlled by the precharge timing control signal (ATD_B); during the precharge phase, the precharge timing control signal (ATD_B) enables the full pull-up precharge circuit to charge the selected bit line; after the precharge phase ends, the precharge timing control signal (ATD_B) turns off the full pull-up precharge circuit. The pull-up circuit is controlled by a pull-up control signal (SENB); during non-read operations, the pull-up control signal (SENB) pulls the first bit line voltage and the second bit line voltage up to the pre-charge voltage; throughout the entire read cycle, the pull-up control signal (SENB) controls the pull-up path to be turned off.

2. The bit line pre-charge circuit for ultra-high speed NVM read pass according to claim 1, wherein, The column selection circuit includes a single-stage low-voltage PMOS transistor.

3. The bit line pre-charge circuit for ultra-high speed NVM read pass according to claim 2, wherein, The column selection circuit is controlled by the column address decoding signal (YENB_B).

4. The bit line pre-charge circuit for ultra-high speed NVM read pass according to claim 3, wherein, The circuit also includes: A pull-down circuit is used to pull the bit line down to 0 level after a read operation is completed.

5. The bit line pre-charge circuit for ultra-high speed NVM read pass according to claim 4, wherein, The pull-down circuit is controlled by the column address decoding signal (YENB_B).

6. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 4, characterized in that, The full pull-up precharge circuit is a PMOS transistor; the source of the PMOS transistor is connected to the precharge voltage source, and the gate of the PMOS transistor is input to the precharge timing control signal (ATD_B); the drain of the PMOS transistor is connected to the bit line as the voltage output terminal of the bit line.

7. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 6, characterized in that, The pull-up circuit is a PMOS transistor; the source of the PMOS transistor is connected to a pre-charge voltage source, the gate of the PMOS transistor receives the pull-up control signal (SENB), and the drain of the PMOS transistor is connected to the voltage output terminal of the bit line.

8. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 6, characterized in that, The potential equalization circuit is a PMOS transistor; the gate of the PMOS transistor is input with the precharge timing control signal (ATD_B), the drain of the PMOS transistor is connected to the voltage output terminal (INA) of the first bit line, and the source of the PMOS transistor is connected to the voltage output terminal (INB) of the second bit line.

9. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 8, characterized in that, The pull-down circuit is an NMOS transistor, the gate of which receives the column address decoding signal (YENB_B), the source of which is grounded, and the drain of which is connected to the drain of a single-stage low-voltage PMOS transistor in the column select circuit of the same bit line.

10. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 7, characterized in that, The pull-up control signal (SENB) is high during the read operation cycle and low during non-read operations.

11. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 1, characterized in that, The pre-charge voltage is 1.2V.

12. The bit line precharge circuit for an ultra-high-speed NVM read path according to claim 6, characterized in that, The pre-charge voltage source is a logic voltage source.

13. A chip, characterized in that, Includes a bit line precharge circuit for an ultra-high-speed NVM read path as described in any one of claims 1 to 12.

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