Defect detection during erase operation

Abstract

The present disclosure relates to defect detection during erase operations. A system includes a memory device including: a memory array; and control logic, operatively coupled with the memory array, to perform operations including causing performance of an erase operation. The erase operation includes sub-operations. The operations further include causing performance of defect detection during at least one of the sub-operations. The defect detection is performed relative to at least one failure point using at least one defect detection method.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to defect detection during erase operations. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a memory device comprising: a memory array; and control logic operably coupled to the memory array to perform operations including: initiating an erase operation, the erase operation comprising a plurality of sub-operations performed relative to the memory array; during at least one of the plurality of sub-operations, causing at least one current differential to be identified between a pair of components of the memory array; determining whether the at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory array; and in response to determining that the at least one current differential indicates at least one defect relative to at least one fault point, causing an indication of at least one defect to be generated.

[0004] In another aspect, this disclosure relates to a method comprising: causing a processing device to initiate an erase operation, the erase operation comprising a plurality of sub-operations performed relative to a memory array; during at least one of the plurality of sub-operations, causing the processing device to identify at least one current differential between a pair of components of the memory array; determining whether the at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory array; and in response to determining that the at least one current differential indicates at least one defect relative to at least one fault point, causing the processing device to generate an indication of at least one defect.

[0005] In another aspect, this disclosure relates to a system comprising: a memory including instructions; and control logic operably coupled to the memory to perform operations including: sending a request to initiate an erase operation to the memory device, the erase operation including a plurality of sub-operations performed relative to a memory array of the memory device; receiving from the memory device an indication of at least one defect relative to at least one corresponding fault point of the memory array, wherein the at least one defect corresponds to at least one current differential identified between a pair of components of the memory array during at least one of the plurality of sub-operations; and, in response to receiving the indication of at least one defect, sending a request to perform at least one remedial action to the memory device. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart outlining a method for performing an erasure operation and an erasure operation screening according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an example method for performing an erasure operation to implement defect detection according to some embodiments of the present disclosure.

[0011] Figures 5A to 5B This is a flowchart of an example method for performing defect detection during at least one sub-operation of an erasure operation, according to some embodiments of the present disclosure.

[0012] Figure 6 The diagram is a three-dimensional (3D) alternative gate memory device illustrating the performance of an erase operation according to some embodiments of the present disclosure.

[0013] Figure 7 A block diagram of an example computer system in which embodiments of the present disclosure may be operated.

[0014] Figure 8 This is a diagram of a comparator circuit that can be used to perform ICS defect detection according to some embodiments of this disclosure. Detailed Implementation

[0015] This disclosure relates to defect detection during erase operations. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data is expected to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the type of memory cell, a memory cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented by binary values ​​(e.g., "0" and "1") or combinations of such values.

[0017] A memory device may comprise multiple memory cells arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more conductive lines of a memory device used in conjunction with one or more bit lines to generate the address of each memory cell. The intersection of a bit line and a word line constitutes the address of the memory cell. Hereinafter, a block refers to a cell of a memory device used for storing data and may comprise a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of the memory device to allow concurrent operation on each plane. A memory device may include circuitry for performing concurrent memory page accesses on two or more memory planes. For example, a memory device may include corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages on two or more memory planes containing different page types. For ease of description, these circuits may generally be referred to as independent plane driver circuitry. The control logic on a memory device comprises multiple separate processing threads to perform concurrent memory access operations (e.g., read, program, and erase operations). For example, each processing thread corresponds to a specific memory plane and performs a memory access operation on that specific memory plane using associated independent plane driver circuitry. As these processing threads operate independently, the power usage and requirements associated with each processing thread also change.

[0018] A three-dimensional (3D) replaced-gate memory device (e.g., a 3D replaced-gate NAND) is a memory device having a replaced-gate structure using word line stacking. For example, a 3D replaced-gate memory device may include word lines, select gates, etc., sandwiched between a set of layers including pillars (e.g., polysilicon pillars), a tunnel oxide layer, a charge trapping (CT) layer, and a dielectric (e.g., oxide) layer. A 3D replaced-gate memory device may have a "top stack" corresponding to a first side and a "bottom stack" corresponding to a second side. For example, the first side may be the drain side, and the second side may be the source side. Data in a 3D replaced-gate memory device may be stored as 1 bit / memory cell (SLC), 2 bit / memory cell (MLC), 3 bit / memory cell (TLC), etc. The read window budget (RWB) tolerance, corresponding to the distance between valleys of the threshold voltage distribution, may decrease as the number of bits / memory cells increases.

[0019] Erasure operations for memory devices, such as block erase operations for NAND memory devices, can be performed by executing multiple sub-operations. A sub-operation may include: an erase pulse sub-operation, during which an erase pulse voltage is applied to erase memory cells; and an erase verification sub-operation, during which an erase verification voltage is applied to verify the result of the erase pulse. Instead of using a single high-voltage erase pulse that can lead to increased wear and reduced durability of the memory device, the erase operation can be performed using multiple erase pulses (e.g., up to five erase pulses) applied at progressively higher voltages, with erase verification performed after each of the multiple erase pulses to identify which memory cells have been erased or not erased by the previous erase pulse. That is, if no memory cells have been verified to have been erased after an erase pulse, then a higher erase pulse voltage is applied to those memory cells during the next erase pulse. An erase pulse sub-operation may include: a ramp-up phase, where the erase pulse ramps up to a specified erase pulse voltage; an execution phase after the erase pulse ramps up to the specified voltage; and a reset phase, where the voltage is reset to allow subsequent erase verification sub-operations to be performed. Each of these erase pulse / erase verification cycles may be referred to as an erase cycle. If the number of erase cycles executed does not meet a threshold condition, the memory device may return an indication of an erase operation failure. For example, if the number of erase cycles exceeds a threshold number of erase cycles, the memory device may return an indication of an erase operation failure.

[0020] In certain memory devices, such as 3D replaced gate memory devices (e.g., 3D replaced gate NAND devices), the die can provide its status via at least one register (e.g., an 8-bit register). More specifically, the at least one status register may include a status register and an extended status register. Regarding the erase operation status, the status register may contain bits indicating whether the erase operation has succeeded or failed. That is, when set to a particular state, the bit may indicate that an error occurred during the erase operation. However, for multi-plane devices containing multiple planes, the bit may not indicate which plane has failed. To address this, a command (e.g., a 78h command) can be sent to each plane to determine which plane has failed.

[0021] The situation may be that the memory device contains one or more defects. Examples of defects may include short circuits (e.g., word line short circuits, bit line short circuits). Defects can cause failures during memory device operation, such as erase operations, programming operations, or read operations. However, some defects may be undetectable at the time of manufacture, or defects may become apparent over time during the operational life of the memory device. Furthermore, some early-stage defects may not be detectable during certain erase operations (e.g., during erase verification), but can cause failures during subsequent programming or read operations. Therefore, an erase operation performed on a defective memory device may not result in an erase failure.

[0022] This disclosure addresses the above and other defects by implementing defect detection during erase operations (e.g., block erase operations). Defect detection can leverage the voltage used to perform the erase operation to identify the presence of defects. For example, one or more current leakage detection mechanisms can be used to determine whether current leakage and / or voltage drops caused by current leakage exist between one or more pairs of components in the memory device during one or more sub-operations, and the presence of current leakage and / or voltage drops provides an indication of a defect within the memory device. Depending on the magnitude of the leakage current and the strength of the drive voltage, current leakage may or may not cause a voltage drop. Since erase operations are typically slow compared to other memory device operations, erase operations are not speed-sensitive.

[0023] For example, an erase operation may include multiple sub-operations. Sub-operations may include an erase pulse sub-operation and an erase verification sub-operation. In some embodiments, a sub-operation may further include a pre-programming sub-operation performed prior to the erase pulse sub-operation. In some embodiments, a sub-operation may further include an annealing pulse sub-operation performed between the erase pulse sub-operation and the erase verification sub-operation. In some embodiments, a sub-operation may further include a select gate (SG) scan sub-operation. Defect detection may be performed during one or more of the sub-operations. For example, defect detection may be performed during the erase pulse sub-operation and / or the erase verification sub-operation. Alternatively or additionally, defect detection may be performed during the pre-programming sub-operation, the annealing pulse sub-operation, and / or the SG scan sub-operation.

[0024] The defect detection described herein can be performed within the context of a 3D replaced gate memory device (e.g., a 3D replaced gate NAND). For example, defect detection can be performed by identifying WL-to-pillar current leakage, which may correspond to a device defect (e.g., an open circuit between WL and a pillar). As another example, defect detection can be performed by identifying a voltage difference or increment between even and odd WLs, which may correspond to a device defect (e.g., a short circuit between even and odd WLs).

[0025] The advantages of this disclosure include, but are not limited to, improved memory device defect detection and improved memory device reliability.

[0026] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0030] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory buses, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on variations in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level memory cell (SLC), may store one bit per memory cell. Other types of memory cells, such as multi-level memory cells (MLC), three-level memory cells (TLC), four-level memory cells (QLC), and five-level memory cells (PLC), may store multiple bits per memory cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although a 3D cross-point array of non-volatile memory cells and a non-volatile memory component of NAND flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller for media management within the same memory device package (e.g., memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The local media controller 135 may implement a defect detection (DD) component 137 that can perform defect detection during an erase operation. For example, the DD component 137 may perform defect detection during one or more of the pre-programming sub-operation, erase pulse sub-operation, annealing pulse sub-operation, erase verification sub-operation, and select gate (SG) scan sub-operation. In some embodiments, the DD component 137 performs defect detection during the erase pulse and erase verification sub-operations. Defect detection can be performed relative to any suitable point of failure using any suitable detection method. Reference will be made below. Figure 3 Section 5 describes further details regarding the operation of DD component 137.

[0043] Figure 2 A first device in the form of a presenting memory device 130 according to an embodiment and a presenting memory subsystem (e.g., Figure 1 A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0044] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2 (Not shown in the text) can be programmed as one of at least two target data states.

[0045] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 204. The memory device 130 also includes an input / output (I / O) control circuitry 260 to manage inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. Address register 214 communicates with I / O control circuitry 260, row decoding circuitry 208, and column decoding circuitry 210 to latch the address signal before decoding. Command register 224 communicates with I / O control circuitry 260 and local media controller 135 to latch incoming commands.

[0046] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 204 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses. In one embodiment, the local media controller 135 includes a DD component 137 that can perform defect detection as described herein during erase operations on memory device 130.

[0047] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 270 for transfer to memory cell array 204; then, new data can be latched from I / O control circuitry 260 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 260 for output to memory subsystem controller 115; then, new data can be transferred from data register 270 to cache register 218. Cache register 218 and / or data register 270 may form a page buffer of memory device 130 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 2 (Not shown) to sense the data status of the memory cells in the memory cell array 204, for example, by sensing the status of the data lines connected to the memory cells. The status register 222 can communicate with the I / O control circuitry system 260 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0048] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 236, and outputs data to memory subsystem controller 115 via I / O bus 236.

[0049] For example, commands can be received at I / O control circuitry system 260 via input / output (I / O) pins [7:0] of I / O bus 236, and then written to command register 224. Addresses can be received at I / O control circuitry system 260 via input / output (I / O) pins [7:0] of I / O bus 236, and then written to address register 214. Data can be received at I / O control circuitry system 260 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and then written to cache register 218. Data can then be written to data register 270 for programming memory cell array 204.

[0050] In this embodiment, cache register 218 may be omitted, and data may be written directly to data register 270. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0051] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functions of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The function of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0052] Figure 3 This is a flowchart of an example method 300 for performing an erase operation and an erase operation screening according to some embodiments of the present disclosure. Method 300 may be performed by control logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 and 2 The DD component 137 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] At operation 310, an erase operation is performed. For example, control logic (e.g., DD component 137 implemented by local media controller 135) causes an erase operation to be performed relative to a block of the memory device. In some embodiments, the memory device is a 3D replaced gate memory device (e.g., 3D replaced gate NAND). The erase operation may comprise multiple sub-operations.

[0054] The following text will refer to Figure 4 In further detail, the erase operation may comprise multiple sub-operations. Depending on the embodiment, the sub-operations may include a pre-programmed sub-operation, an erase pulse sub-operation, an optional annealing pulse sub-operation, an erase verification sub-operation, and an SG scan sub-operation. Each of these sub-operations requires a relatively short execution time, such as 40 to 60 microseconds (ms), except for the erase pulse sub-operation, which may occupy, for example, 1 millisecond (ms) or longer.

[0055] The following text will refer to Figure 4In further detail, the control logic can cause a defect detection process to be performed during one or more periods within a sub-operation. In some embodiments, the defect detection process is performed during only one period within a sub-operation. In some embodiments, the defect detection process is performed during all sub-operations. In some embodiments, the defect detection process is performed during an appropriate subset of the sub-operations. For example, the defect detection process can be performed during an erase pulse sub-operation and an erase verification sub-operation.

[0056] At operation 320, an erase operation filter is performed. For example, control logic causes an erase operation filter to be performed after an erase operation. The erase operation filter determines whether a block is valid or a "good" block after the erase operation to preserve data. If a block is determined to be valid, it can continue to be used during the operation. If a block is determined to be invalid or a "bad" block to preserve data, the data will not continue to be stored at that block, and a new block will be designated for data storage. Any suitable procedure can be used to perform the erase operation filter according to the embodiments described herein.

[0057] Figure 4 This is a flowchart of an example method 400 for performing an erasure operation to implement defect detection according to some embodiments of the present disclosure. Method 400 may be performed by control logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 and 2 The DD component 137 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0058] At operation 410, a pre-programming sub-operation is performed. For example, control logic (e.g., DD component 137 implemented by local media controller 135) may cause a pre-programming process to be performed relative to a word line (WL) associated with a memory cell (“memory cell”) of a memory array (e.g., a block) of the memory device. For example, the memory device may be for… Figure 1 The memory device 130.

[0059] The pre-programming process can be viewed as "soft" programming of the memory array. During the pre-programming process, all memory cells of the memory array can be programmed together to tighten the threshold voltage (V) after an erase operation is performed. tDistribution. For example, the select gate (SG) and active WL can be biased to the corresponding voltages. See below for reference. Figure 6 Illustrative examples of preprogrammed suboperations performed relative to a memory array of a 3D replaced gate memory device are provided.

[0060] In some embodiments, defect detection may be further performed during pre-programmed sub-operations. For example, the control logic may further cause the detection method to be performed relative to at least one fault point. The fault point may be the result of a defect during the processing of the memory array. For example, the fault point may be the result of an etching problem (e.g., over-etching) during the manufacturing of the memory array.

[0061] At least one fault point may include at least one fault point associated with a WL short circuit within the memory array. For example, for a memory array of a 3D replaced gate memory device, examples of fault points include, but are not limited to, a WL-to-pillar short circuit, a WL-to-through-array via (TAV) short circuit, and a WL (or SG)-to-source / to- ...

[0062] A WL-to-pillar short circuit refers to a short circuit between the WL and a pillar containing a pillar located between the bit line and the source line. A WL-to-TAV short circuit refers to a short circuit between the WL and a TAV used to connect the WL to an external contact. For example, such a short circuit can be caused by an etching defect between adjacent TAVs. A WL (or SG)-to-bit / source line short circuit refers to a short circuit between the WL or SG and a bit line or source line.

[0063] A charge pump circuit is a component of a WL driver circuit that generates a voltage for operating a memory device. For example, the charge pump circuit can charge an array of capacitors operating on different phase-controlled blocks to raise the input voltage to a target voltage to be applied to the WL. The WL driver circuit may further include a voltage regulator sensor circuit that monitors the voltage generated by the charge pump circuit. For example, when the charge pump circuit reaches the target voltage to be applied to the WL, the voltage regulator sensor circuit can stop the operation of the charge pump. More specifically, the voltage regulator sensor circuit can use a feedback signal as a control signal to pass a clock signal to the charge pump circuit or suppress the clock signal. Due to leakage, the output voltage level will slowly decrease when the charge pump circuit is not operating. When the output voltage level drops below a threshold voltage, the voltage regulator sensor circuit can restart the charge pump to raise the output voltage level back to the target voltage. For example, a short circuit in the WL can increase background leakage, which can cause the charge pump circuit to take longer to charge and can increase the use of feedback / control signals.

[0064] One example of a defect detection method involves pump clock counter defect detection. For instance, control logic may activate a pump clock counter (e.g., included in a voltage regulator sensor circuit) to count the number of clock pulses delivered to the charge pump circuit over a given amount of time after the charge pump achieves the target voltage, and compare the count to a threshold count to detect the presence of a defect. For example, if the count exceeds the threshold count, this indicates a defect.

[0065] Another example of defect detection is internal current sensing (ICS) defect detection. ICS defect detection can employ a comparator circuit, which includes circuitry connected to the detected voltage (V). det The positive terminal of ) and connected to the reference voltage (V ref A comparator at the negative terminal of the input. The target WL can be driven to a value higher than V. ref Specific voltage (V) det Furthermore, the floating target WL performs defect detection while ICS defect detection is performed relative to the target WL. If no defect exists relative to the target WL, then V det It will remain relatively stable and the detected output signal (Det_out) will continue to indicate V. det Greater than V ref However, if there is a defect relative to the target WL (e.g., WL-to-WL short circuit, WL-to-pillar short circuit), then V det It will decline. Ultimately, once V... det Drop below V ref Det_out will be flipped to indicate V ref Larger. (Reference) Figure 8 This demonstrates an example comparator circuit that can be used to perform ICS defect detection.

[0066] At operation 420, an erase pulse sub-operation is performed. For example, control logic causes an erase pulse to be applied. More specifically, an erase pulse sub-operation involves applying an erase pulse to the memory cells of the WL group being erased. The erase pulse sub-operation can take significantly longer for a period of time (or duration) compared to other memory operations and other sub-operations of the erase operation. The duration of the erase pulse sub-operation can be excessive due to the significant bias voltage (Vera) applied to the string of memory cells being erased using the erase pulse, for example, approximately 20 volts (V). After the erase pulse sub-operation completes, it can take a considerable amount of time to ramp up to this bias voltage, and the string of memory cells takes a significant amount of time to recover, such as to discharge. An erase suppression bias can be applied to suppress erasure relative to memory cells that have not undergone erasure. If it is determined during erase verification that no memory cells will be erased (as will be described in further detail below), another erase pulse sub-operation can be performed using an erase pulse with a higher voltage than the previous erase pulse. This process can continue until the erasure of all memory cells in the WL group has been verified. See below for reference. Figure 6 Illustrative examples of erase pulse sub-operations performed relative to a memory array of a 3D replaced gate memory device are provided.

[0067] In some embodiments, defect detection may be further performed during the erase pulse sub-operation. For example, the control logic may further cause a detection method to be performed relative to at least one fault point. The at least one fault point may include at least one fault point related to current leakage and / or voltage drop caused by current leakage within the memory array. For example, with respect to a memory array of a 3D replacement gate memory device, examples of fault points include, but are not limited to, source line (SRC) leakage, bit line leakage, pillar-to-WL leakage, and WL-to-WL leakage. SRC leakage refers to current leakage between the SRC and a component connected to the SRC (e.g., a circuit), bit line leakage refers to current leakage between a bit line and a component connected to the bit line (e.g., a circuit), pillar-to-WL leakage refers to current leakage between a pillar and a WL, and WL-to-WL leakage refers to current leakage between several pairs of WLs. These leakages can be identified considering the low voltage bias (e.g., about 0V) applied relative to the active WLs during the erase pulse. Regarding WL-to-WL leakage, this fault point can be detected when the erase pulse is applied relative to alternating active WLs (e.g., an even number or an odd number of WLs). For example, if an even-numbered erase pulse is applied, the memory cells corresponding to even-numbered active WLs are biased at a low voltage (e.g., 0V), while the memory cells corresponding to odd-numbered active WLs are biased at a higher voltage. This enables leakage detection between adjacent memory cells with even and odd-numbered WLs. Examples of defect detection methods include, but are not limited to, pump clock defect detection (e.g., CPCM), WL voltage regulator sensor defect detection, and ICS defect detection.

[0068] At operation 430, an annealing pulse sub-operation can be performed. For example, the control logic causes an annealing pulse to be applied to the WL. The purpose of the annealing pulse is to "wash out" shallow charge carriers (e.g., shallow holes and / or shallow electrons) from the pillar (e.g., oxide region) to increase the accuracy of erase verification. Annealing pulses can be applied relative to alternating WLs. More specifically, an even number of annealing pulses can be used to perform annealing pulses relative to an even number of WLs, followed by an odd number of annealing pulses relative to an odd number of WLs. For example, during an even number of annealing pulses, memory cells corresponding to even number of WLs can be ramped up to a positive bias voltage, while memory cells corresponding to odd number of WLs can be ramped up to a negative bias voltage (and vice versa for odd number of annealing pulses). In some embodiments, defect detection can be further performed during the annealing pulse sub-operation. For example, the control logic can further cause a detection method to be implemented to detect faults. Examples of faults include, but are not limited to, WL-to-WL leakage, WL-to-pillar leakage, and WL-to-via leakage. Examples of detection methods include, but are not limited to, pump clock defect detection (e.g., CPCM), WL regulator short-circuit sensor defect detection, and ICS defect detection. See below for reference. Figure 6 Describe other details regarding the annealing pulse operation.

[0069] At operation 440, an erase verification sub-operation is performed. For example, control logic causes an erase verification to be performed to determine whether the memory cell has been properly erased due to the erase pulse. The erase verification can be performed by applying a voltage to the control gate of the memory cell to determine whether the memory cell is conducting current. In some embodiments, the erase verification is applied relative to alternating WLs. For example, the erase verification can be performed first relative to the even WLs of the WL group, followed by the erase verification relative to the odd WLs of the WL group.

[0070] In some embodiments, defect detection may be further performed during the erase verification sub-operation. For example, control logic may further cause a detection method to be implemented to detect a fault. Examples of faults include, but are not limited to, WL-to-WL leakage, WL-to-column leakage, and WL-to-through-hole leakage. Examples of defect detection methods include, but are not limited to, pump clock defect detection (e.g., CPCM), WL regulator short-circuit sensor defect detection, and ICS defect detection.

[0071] At operation 450, it is determined whether the erase verification sub-operation was successful. For example, if all memory cells pass the erase verification, then the erase verification sub-operation is determined to be successful. If not, the process returns to operation 420 to perform another erase pulse sub-operation at a higher erase pulse voltage than that used during the previous execution of the erase pulse sub-operation.

[0072] If the erase verification sub-operation is determined to be successful at operation 450, it means that all memory cells have been successfully erased. At operation 460, the select gate (SG) scan sub-operation can then be performed. For example, the control logic causes an SG scan to be performed relative to SG. The SG scan is performed after the erase operation has been completed to determine the V of SG. t Whether it falls outside the acceptable range (e.g., too high or too low). If the SG falls outside the acceptable range, then the memory array (e.g., a block) may be marked as an invalid or bad memory array, and the memory array will not be used for further programming. Otherwise, the memory array will be considered a valid or good memory array for future programming.

[0073] In some embodiments, defect detection may be further performed during the SG scan sub-operation. For example, the control logic may further cause a detection method to be implemented to detect a fault. Examples of faults include, but are not limited to, SG to WL leakage, SG to position line and / or SRC leakage, and SG to column leakage. Examples of defect detection methods include, but are not limited to, pump clock defect detection (e.g., CPCM), WL regulator short-circuit sensor defect detection, and ICS defect detection.

[0074] Figure 5A This is a flowchart of an example method 500A for performing defect detection during at least one sub-operation of an erasure operation according to some embodiments of the present disclosure. Method 500A may be performed by control logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500A is performed by… Figure 1 and 2 The DD component 137 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] At operation 510A, an erase operation is initiated. For example, control logic (e.g., DD component 137 implemented by local media controller 135) may cause the erase operation to be initiated in response to a request to initiate an erase operation received from the memory subsystem controller. The erase operation may be performed relative to a word line (WL) associated with a memory cell (“cell”) of a memory array (e.g., a block) of the memory device.

[0076] At operation 520A, at least one current differential is identified. For example, the control logic may cause at least one current differential to be identified between a pair of components of the memory device during at least one sub-operation of the erase operation. The at least one current differential may correspond to current leakage between the pair of components. The at least one sub-operation may include at least one of a pre-programming sub-operation, an erase pulse sub-operation, an annealing pulse sub-operation, an erase verification sub-operation, or a select gate scan sub-operation. The at least one current differential may be identified as the difference between a first voltage applied to a first component of the pair of components during at least one sub-operation and a second voltage applied to a second component of the pair of components during at least one sub-operation. The pair of components may include at least one of the following: WL, pillar, TAV, bit line, source line, or SG.

[0077] At operation 530A, it is determined whether at least one defect exists. For example, control logic may determine whether at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory device. In some embodiments, determining whether at least one defect exists includes determining whether at least one current differential exceeds a corresponding threshold current differential. The threshold current differential may define a value or range of values ​​indicating an appropriate connection between a pair of components. At least one fault point may include at least one of the following: WL-WL leakage, WL-pillar leakage or short circuit, WL-TAV leakage or short circuit, source line leakage, bit line leakage, pillar-to-WL and SG leakage, or WL-to-line or source line short circuit. Any suitable method may be used to identify at least one current differential and determine whether at least one defect exists. Examples of defect detection methods include WL pump clock defect detection, WL regulator short-circuit sensor defect detection, and ICS defect detection.

[0078] If no defect is identified at operation 530A, an erase operation screening can be performed at operation 540A. For example, control logic can cause the erase operation screening to be performed.

[0079] However, if at least one defect is determined at operation 530A, an indication of at least one defect can be generated at operation 550A. For example, the control logic can cause the generation of an indication of at least one defect and send it to the memory subsystem controller. At operation 560A, the control logic can perform at least one remedial action. For example, the control logic can receive a request from the memory subsystem controller to perform at least one remedial action. For example, at least one remedial action can include at least one of the following: marking the memory device as a defective memory device (e.g., a memory device containing one or more current leaks between one or more pairs of components), or discarding (e.g., retrieving) the defective memory device. (Refer to above) Figures 1 to 4 Describe further details regarding the operation of 510A to 560A.

[0080] Figure 5B This is a flowchart of an example method 500B for performing defect detection during at least one sub-operation of an erasure operation, according to some embodiments of the present disclosure. Method 500B may be performed by control logic that may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, by Figure 1 and 2 The memory subsystem controller 115 executes method 500B. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0081] At operation 510B, an erase operation is initiated. For example, control logic (e.g., control logic of memory subsystem controller 115) can initiate the erase operation by sending a request to initiate the erase operation to the memory device. More specifically, the memory device may include a memory array (e.g., blocks) and a local media controller (e.g., memory cell array 204 and local media controller 135). The erase operation may include multiple sub-operations performed relative to the memory array.

[0082] At operation 520B, an indication of at least one defect is received. For example, the control logic may receive an indication of at least one defect relative to at least one corresponding fault point in the memory array (e.g., via a local media controller). The at least one defect may correspond to at least one current differential identified between a pair of components of the memory device during at least one sub-operation of the erase operation. The at least one current differential may correspond to current leakage between the pair of components. The at least one sub-operation may include at least one of a pre-programming sub-operation, an erase pulse sub-operation, an annealing pulse sub-operation, an erase verification sub-operation, or a select gate scan sub-operation. The at least one current differential may be identified as the difference between a first voltage applied to a first component of the pair of components during at least one sub-operation and a second voltage applied to a second component of the pair of components during at least one sub-operation. The pair of components may include at least one of the following: WL, pillar, TAV, bit line, source line, or SG.

[0083] In some embodiments, at least one current differential exceeds a corresponding threshold current differential. The threshold current differential defines a value or range of values ​​indicating the proper connection between a pair of components. At least one fault point may include at least one of the following: WL-WL leakage, WL-pillar leakage or short circuit, WL-TAV leakage or short circuit, source line leakage, bit line leakage, pillar-to-WL and SG leakage, or WL-to-line or source line short circuit. Any suitable method can be used to identify at least one current differential and determine the presence of at least one defect. Examples of defect detection methods include WL pump clock defect detection, WL regulator short-circuit sensor defect detection, and ICS defect detection.

[0084] At operation 530B, the control logic may perform at least one remedial action. For example, the control logic may send a request to perform at least one remedial action to the memory device (e.g., via a local media controller). For example, the at least one remedial action may include at least one of the following: marking the memory device as a defective memory device (e.g., a memory device containing one or more current leaks between one or more pairs of components), or discarding (e.g., retrieving) the defective memory device. Therefore, methods 500A to 500B can be used to identify defective memory devices during an erase operation and perform at least one remedial action to resolve the defective memory device. (Refer to above) Figures 1 to 5A Describe further details regarding operation of 510B to 530B.

[0085] Figure 6 The diagrams provided herein are three-dimensional (3D) replacements of the gate memory device (“device”) 600, illustrating the performance of an erase operation according to some embodiments of the present disclosure. However, the embodiments described herein can be applied to any suitable memory device.

[0086] As shown, device 600 includes bit lines 610, pillars 620-1 and 620-2, select gates (SG) 630-1 and 630-2, source lines (SRC) 640, and WL groups 650-1, 650-2, 660-1, and 660-2. More specifically, WL groups 650-1 and 650-2 are dummy WL groups, and WL groups 660-1 and 660-2 are active WL groups. WL group 650-1 includes dummy WLs 652-1 to 656-1, WL group 650-2 includes dummy WLs 652-2 to 656-2, WL group 660-1 includes active WLs 662-1 and 664-1, and WL group 660-2 includes active WLs 662-2, 664-2, and 666-2. However, this example should not be considered limiting. A virtual WL corresponds to a memory cell that does not store data and is contained to meet processing tolerances, while an active WL corresponds to a memory cell that stores data.

[0087] As further illustrated, WL 670 is provided. In some embodiments, device 600 is a plurality of stacked devices, wherein WL groups 650-1 and 660-1 are associated with a first stack of device 600 (e.g., an upper stack), and WL groups 650-2 and 660-2 are associated with a second stack of device 600 (e.g., a lower stack), such that WL 670 corresponds to a virtual WL separating WL groups 660-1 and 660-2. In other embodiments, device 600 is a “single stack” device, wherein WL groups 660-1 and 660-2 are not arranged in a stack. Here, WL 670 may be an active WL within one of WL groups 660-1 or 660-2.

[0088] Illustratively, in pre-programmed suboperations (e.g., in...) Figure 4 During the pre-programmed sub-operation executed at operation 410, bit lines 610, pillars 620-1 and 620-2, and SRC 640 may each be at a low bias voltage (e.g., 0V). SG 630-1 and 630-2, and memory cells corresponding to WL groups 650-1, 650-2, 660-1, and 660-2, may ramp up to higher bias voltages. For example, SG 630-1 and 630-2 may ramp up to approximately 6V, memory cells corresponding to virtual WLs 652-1 and 652-2 may ramp up to approximately 9V, memory cells corresponding to virtual WLs 654-1 and 654-2 may ramp up to approximately 6V, and memory cells corresponding to WL groups 660-1 and 660-2 may ramp up to approximately 12V. However, these example bias voltages should not be considered limiting. Defect detection can be performed during pre-programmed sub-operations, as referenced above. Figure 4 As described.

[0089] Illustratively, in the erase pulse sub-operation (e.g., in...) Figure 4 During the erase pulse sub-operation performed at operation 420, bit lines 610, pillars 620-1 and 620-2, and SRC 640 can each ramp up to a bias voltage of approximately 24V, SG630-1 and 630-2 can each ramp up to a bias voltage of approximately 20V, memory cells corresponding to virtual WL 652-1 and 652-2 can ramp up to a bias voltage of approximately 8V, memory cells corresponding to virtual WL 654-1 and 654-2 can ramp up to a bias voltage of approximately 12V, and memory cells corresponding to virtual WL 656-1 and 656-2 can ramp up to a voltage of approximately 16V.

[0090] If the erase pulse is applied relative to each of the WLs in WL groups 660-1 and 660-2, then the memory cells corresponding to WL groups 660-1 and 660-2 can be at a low bias voltage (e.g., 0V). However, in some cases, the erase pulse can be applied relative to alternating WLs. For example, the erase pulse can be applied relative to even-numbered WLs or odd-numbered WLs. If the erase pulse is applied relative to an even-numbered WL, then the memory cells corresponding to even-numbered WLs within WL groups 660-1 and 660-2 can be at a low bias voltage (e.g., 0V), while the memory cells corresponding to odd-numbered WLs within WL groups 660-1 and 660-2 can ramp up to a higher bias voltage (e.g., approximately 6V). Alternatively, if an erase pulse is applied relative to the odd number of WLs, then memory cells corresponding to odd-numbered WLs within WL groups 660-1 and 660-2 can be at a low bias voltage (e.g., 0V), while memory cells corresponding to even-numbered WLs within WL groups 660-1 and 660-2 can be ramped up to a higher bias voltage (e.g., approximately 6V). This reduces erase suppression (e.g., in...). Figure 4 During the erase pulse sub-operation at operation 420 (with erase suppression applied), pillars 620-1 and 620-2, bit lines 610 and SRC 640, SG 630-1 and 630-2, and memory cells corresponding to each of WL groups 650-1, 650-2, 660-1, and 660-2 may all be at approximately 24V. However, this example bias voltage should not be considered limiting. Defect detection can be performed during the erase pulse sub-operation, as referenced above. Figure 4 As described.

[0091] Illustratively, in annealing pulse sub-operations (e.g., in...) Figure 4During the annealing pulse sub-operation performed at operation 430, bit lines, pillars 620-1 and 620-2, and SRC 640 can each be at a low bias voltage (e.g., 0V), SG 630-1 and 630-2 can be ramped up to a bias voltage of approximately 6V, memory cells corresponding to virtual word lines 652-1 and 652-2 can be ramped up to a bias voltage of approximately 9V, and memory cells corresponding to virtual word lines 654-1 and 654-2 can be ramped up to a bias voltage of approximately 6V. Annealing pulses can be applied relative to alternating WLs. For example, annealing pulses can be applied relative to either even or odd WLs. If an annealing pulse is applied relative to an even number of WLs, memory cells corresponding to even-numbered WLs in WL groups 660-1 and 660-2 can be ramped up to a bias voltage of approximately 8V, while memory cells corresponding to odd-numbered WLs in WL groups 660-1 and 660-2 can be ramped up to a negative bias voltage (e.g., approximately -2V). Alternatively, if an annealing pulse is applied relative to an odd number of WLs, memory cells corresponding to odd-numbered WLs in WL groups 660-1 and 660-2 can be ramped up to a bias voltage of approximately 8V, while memory cells corresponding to even-numbered WLs in WL groups 660-1 and 660-2 can be ramped up to a negative bias voltage (e.g., approximately -2V). However, this example bias voltage should not be considered limiting. Defect detection can be performed during annealing pulse sub-operations, as referenced above. Figure 4 As described.

[0092] Illustratively, in the erase verification sub-operation (e.g., in Figure 4During the erase verification sub-operation performed at operation 440, pillars 620-1 and 620-2 may be at a low bias voltage (e.g., 0V), bit line 610 may ramp up to a bias voltage of approximately 1V, SRC 640 may ramp up to a bias voltage between 0V and approximately 0.5V, SG 630-1 and 630-2 may ramp up to a bias voltage of approximately 6V, memory cells corresponding to virtual word lines 652-1 and 652-2 may ramp up to a bias voltage of approximately 9V, and memory cells corresponding to virtual word lines 654-1 and 654-2 may ramp up to a bias voltage of approximately 6V. Erase verification may be applied relative to alternating WLs. For example, erase verification may be performed relative to either even or odd WLs. If erase verification is applied relative to even-numbered WLs, memory cells corresponding to even-numbered WLs in WL groups 660-1 and 660-2 can be boosted to approximately 8V, while memory cells corresponding to odd-numbered WLs in WL groups 660-1 and 660-2 can be boosted to approximately -2V. Alternatively, if erase verification is applied relative to odd-numbered WLs, memory cells corresponding to even-numbered WLs in WL groups 660-1 and 660-2 can be boosted to approximately -2V, while memory cells corresponding to odd-numbered WLs in WL groups 660-1 and 660-2 can be boosted to approximately 8V. However, this example bias voltage should not be considered limiting. Defect detection can be performed during the erase verification sub-operation, as referenced above. Figure 4 As described.

[0093] Illustratively, in the SG scan sub-operation (e.g., in...) Figure 4 During the erase verification sub-operation performed at operation 440, column 620-1 may ramp up to a low bias voltage (e.g., 0V), column 620-2 may ramp up to a bias voltage of approximately 2.3V, bit line 610 may ramp up to a bias voltage between approximately 0V and approximately 2.3V, SRC 640 may ramp up to a bias voltage of approximately 2.3V, SG 630-1 may ramp up to a bias voltage of approximately 6V, SG 630-2 may ramp up to a low bias voltage (e.g., 0V), memory cells corresponding to virtual word lines 652-1 and 652-2 may ramp up to a bias voltage of approximately 9V, memory cells corresponding to virtual word lines 654-1 and 654-2 may ramp up to a bias voltage of approximately 6V, and memory cells corresponding to WL groups 660-1 and 660-2 may ramp up to a bias voltage of approximately 8V. However, the bias voltages in this example should not be considered limiting. Defect detection can be performed during the SG scan sub-operation, as referenced above. Figure 4 As described.

[0094] Figure 7An example machine illustrating computer system 700 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of DD component 137). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0095] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), memory cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methods discussed herein.

[0096] The example computer system 700 includes a processing device 702 that communicates with each other via a bus 730, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718.

[0097] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0098] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0099] In one embodiment, instruction 726 includes instructions for implementing a component corresponding to the DD component (e.g., Figure 1 The machine-readable storage medium 724 (DD component 137) contains instructions for its function. While the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0100] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. An algorithm here is generally considered to be a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0101] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0102] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0103] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0104] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0105] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: Memory array; and Control logic, which is operatively coupled to the memory array, performs operations including: Initiate an erase operation, which includes a plurality of sub-operations performed relative to the memory array; Determine whether the erase verification sub-operation of the plurality of sub-operations was successful; In response to determining that the erase verification sub-operation is successful, a selection gate scan sub-operation is performed to execute the plurality of sub-operations. During at least one of the plurality of sub-operations, at least one current differential is identified between a pair of components of the memory array. Determine whether the at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory array; and In response to determining the at least one defect of the at least one current differential indication relative to the at least one fault point, an indication of the at least one defect is generated.

2. The memory device of claim 1, wherein the plurality of sub-operations further includes an erase pulse sub-operation.

3. The memory device of claim 2, wherein the plurality of sub-operations further includes a pre-programmed sub-operation performed prior to the erase pulse sub-operation.

4. The memory device of claim 2, wherein the plurality of sub-operations further includes an annealing pulse sub-operation performed between the erase pulse sub-operation and the erase verification sub-operation.

5. The memory device according to claim 1, wherein: The at least one current differential is identified as the difference between a first voltage applied to a first component of the pair of components during the at least one sub-operation and a second voltage applied to a second component of the pair of components during the at least one sub-operation; and Determining whether the at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory array includes determining whether the at least one current differential exceeds a corresponding threshold current differential.

6. The memory device according to claim 5, wherein: The pair of components includes at least one of the following: a word line WL, a pillar, a through-array via, a bit line, a source line, or a select gate; and The at least one fault point includes at least one of the following: WL to WL leakage, WL to pillar leakage or short circuit, WL to TAV leakage or short circuit, source line leakage, bit line leakage, pillar to WL and select gate SG leakage, or WL to bit line or source line short circuit.

7. The memory device of claim 1, wherein the operation further comprises causing at least one remedial action to be performed, the at least one remedial action comprising at least one of: marking the memory device as a defective memory device, or discarding the defective memory device.

8. A method comprising: An erase operation is initiated by a processing device, the erase operation comprising a plurality of sub-operations performed relative to a memory array of a memory device; The processing device determines whether the erase verification sub-operation of the plurality of sub-operations was successful; and In response to determining that the erase verification sub-operation was successful, the processing device causes a selection gate scan sub-operation to be executed for the plurality of sub-operations. During at least one of the plurality of sub-operations, the processing device causes at least one current differential to be identified between a pair of components of the memory array; The processing device determines whether the at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory array; and In response to determining at least one defect of the at least one current differential indication relative to the at least one fault point, the processing device causes an indication of the at least one defect to be generated.

9. The method of claim 8, wherein the plurality of sub-operations further comprises an erase pulse sub-operation.

10. The method of claim 9, wherein the plurality of sub-operations further includes pre-programmed sub-operations performed prior to the erase pulse sub-operation.

11. The method of claim 9, wherein the plurality of sub-operations further includes an annealing pulse sub-operation performed between the erase pulse sub-operation and the erase verification sub-operation.

12. The method according to claim 8, wherein: The at least one current differential is identified as the difference between a first voltage applied to a first component of the pair of components during the at least one sub-operation and a second voltage applied to a second component of the pair of components during the at least one sub-operation; and Determining whether the at least one current differential indicates at least one defect relative to at least one corresponding fault point of the memory array includes determining whether the at least one current differential exceeds a corresponding threshold current differential.

13. The method according to claim 8, wherein: The pair of components includes at least one of the following: a word line WL, a pillar, a through-array via, a bit line, a source line, or a select gate; and The at least one fault point includes at least one of the following: WL to WL leakage, WL to pillar leakage or short circuit, WL to TAV leakage or short circuit, source line leakage, bit line leakage, pillar to WL and select gate SG leakage, or WL to bit line or source line short circuit.

14. The method of claim 8, further comprising causing the processing device to perform at least one remedial action, the at least one remedial action comprising at least one of: marking the memory device as a defective memory device, or discarding the defective memory device.

15. A system comprising: Memory, which includes instructions; and Control logic, which is operatively coupled to the memory, performs operations including: A request to initiate an erase operation is sent to the memory device, the erase operation including a plurality of sub-operations performed relative to the memory array of the memory device, wherein the plurality of sub-operations include an erase verification sub-operation and a select gate scan sub-operation performed in response to determining that the erase verification sub-operation is successful; Receive from the memory device an indication of at least one defect relative to at least one corresponding fault point of the memory array, wherein the at least one defect corresponds to at least one current differential identified between a pair of components of the memory array during at least one of the plurality of sub-operations; and In response to receiving the instruction regarding the at least one defect, a request to perform at least one remedial action is sent to the memory device.

16. The system according to claim 15, wherein: The at least one current differential is identified as the difference between a first voltage applied to a first component of the pair of components during the at least one sub-operation and a second voltage applied to a second component of the pair of components during the at least one sub-operation; and The at least one current differential exceeds the corresponding threshold current differential.

17. The system according to claim 15, wherein: The pair of components includes at least one of the following: a word line WL, a pillar, a through-array via, a bit line, a source line, or a select gate; and The at least one fault point includes at least one of the following: WL to WL leakage, WL to pillar leakage or short circuit, WL to TAV leakage or short circuit, source line leakage, bit line leakage, pillar to WL and select gate SG leakage, or WL to bit line or source line short circuit.

18. The system of claim 15, wherein the at least one remedial action comprises at least one of: marking the memory device as a defective memory device, or discarding the defective memory device.

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