An oscillation period detection circuit, method and semiconductor memory

Abstract

An embodiment of the present application provides an oscillation period detection circuit, method, and semiconductor memory. The oscillation period detection circuit includes: an oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module, configured to receive the enable signal and the oscillation clock signal, perform effective time reorganization processing according to the oscillation clock signal and the enable signal, and determine a target time; a counting module, configured to receive the enable signal and the oscillation clock signal, perform period counting processing according to the enable signal and the oscillation clock signal, and determine a target period number; the oscillation period of the target oscillator is calculated based on the target time and the target period number. In this way, for the enable signal and the oscillation clock signal, the oscillation period is calculated through effective time reorganization processing and period counting respectively, thereby improving the detection accuracy and detection efficiency of the oscillation period.

Description

Technical Field

[0001] This application relates to the field of electronic measurement technologies, and particularly to an oscillation period detection circuit, method, and semiconductor memory. Background Art

[0002] A dynamic random access memory (DRAM) is a commonly used semiconductor memory device in a computer and consists of many repeated memory cells. In a DRAM, it is necessary to use an oscillator to generate regular timing signals and control multiple memory cells according to the timing signals. Therefore, the period detection of the oscillator is an important part of chip quality detection.

[0003] However, in the related art, the method for detecting the oscillation period duration still has deficiencies, resulting in low detection accuracy and detection efficiency. Summary of the Invention

[0004] This application provides an oscillation period detection circuit, method, and semiconductor memory, which can improve the detection accuracy and detection efficiency of the oscillation period.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of this application provides an oscillation period detection circuit, including:

[0007] An oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal;

[0008] A control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time;

[0009] A counting module, configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number;

[0010] Wherein, the oscillation period of the target oscillator is calculated based on the target time and the target period number.

[0011] In a second aspect, an embodiment of this application provides an oscillation period detection method, applied to an oscillation period detection circuit including a target oscillator. The method includes:

[0012] Controlling the target oscillator to output an oscillation clock signal according to the enable signal;

[0013] Performing effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time;

[0014] Perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the number of target cycles;

[0015] Calculate the target time and the number of target cycles to determine the oscillation period of the target oscillator.

[0016] In a third aspect, an embodiment of the present application provides a semiconductor memory, which at least includes the oscillation period detection circuit as described in the first aspect.

[0017] An embodiment of the present application provides an oscillation period detection circuit, method, and semiconductor memory. The oscillation period detection circuit includes: an oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine the target time; a counting module, configured to receive the enable signal and the oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the number of target cycles; wherein, the oscillation period of the target oscillator is calculated based on the target time and the number of target cycles. In this way, the enable signal and the oscillation clock signal are subjected to effective time reorganization processing to determine the target time, the enable signal and the oscillation clock signal are subjected to cycle counting to determine the number of target cycles, and subsequently, the oscillation period can be calculated through the target time and the number of target cycles, thereby improving the detection accuracy and detection efficiency of the oscillation period. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of an oscillation period circuit provided by an embodiment of the present application;

[0019] Figure 2 It is a schematic structural diagram of another oscillation period circuit provided by an embodiment of the present application;

[0020] Figure 3 It is a schematic diagram of the signal waveform of an oscillation period circuit provided by an embodiment of the present application;

[0021] Figure 4 It is a schematic diagram of the simulation test of an oscillation period circuit provided by an embodiment of the present application;

[0022] Figure 5 It is a schematic flow diagram of an oscillation period detection method provided by an embodiment of the present application;

[0023] Figure 6 It is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. In addition, it should be noted that for the convenience of description, only the parts related to the related application are shown in the drawings.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0026] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0027] It should be noted that the terms "first / second / third" involved in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of this application described here can be implemented in an order other than that illustrated or described here.

[0028] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in a computer and consists of many repeated storage units. In DRAM, an oscillator is needed to generate regular timing signals, and multiple storage units are controlled according to these timing signals. Therefore, the period detection of the oscillator is an important part of the quality detection of the storage chip.

[0029] There are various detection methods for the oscillator inside the storage chip, which can generally be divided into two categories. One is direct testing, where the output clock of the oscillator is led to the test bench. This testing method is applicable to low-speed clocks. The second is to output the number of internal clock cycles through control logic and calculate the period of the oscillator based on the working time of the oscillator.

[0030] However, in the related art, the detection method for the oscillation period duration still has deficiencies, resulting in low detection accuracy and detection efficiency.

[0031] Based on this, an embodiment of the present application provides an oscillation period detection circuit. Its basic idea is as follows: The oscillation period detection circuit includes: an oscillator module, including a target oscillator, which is used to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module, which is used to receive the enable signal and the oscillation clock signal, and perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time; a counting module, which is used to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number; wherein, the oscillation period of the target oscillator is calculated based on the target time and the target period number. In this way, the enable signal and the oscillation clock signal are subjected to effective time reorganization processing to determine the target time, and the enable signal and the oscillation clock signal are subjected to period counting to determine the target period number. Subsequently, the oscillation period can be calculated through the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0032] The following will describe each embodiment of the present application in detail with reference to the accompanying drawings.

[0033] In an embodiment of the present application, refer to Figure 1 , which shows a schematic structural diagram of an oscillation period detection circuit 10 provided by an embodiment of the present application. As Figure 1 shown, the oscillation period detection circuit 10 includes:

[0034] An oscillator module 101, including a target oscillator 1011, which is used to receive an enable signal and control the target oscillator 1011 to output an oscillation clock signal according to the enable signal;

[0035] A control module 102, which is used to receive the enable signal and the oscillation clock signal, and perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time;

[0036] A counting module 103, which is used to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number;

[0037] Wherein, the oscillation period of the target oscillator 1011 is calculated based on the target time and the target period number.

[0038] It should be noted that the oscillation period detection circuit provided by the embodiment of the present application can be applied to any electronic device involving an oscillator, such as a dynamic random access memory, a static random access memory, etc.

[0039] In the embodiments of the present application, the basic principle of the oscillation period detection circuit 10 is as follows: the number of internal clock cycles is output through the control logic, and the period of the oscillator is calculated based on the working time of the oscillator.

[0040] Specifically, the oscillation period detection circuit includes an oscillator module 101, a control module 102, and a counting module 103. The target oscillator 1011 in the oscillator module 101 outputs an oscillation clock signal according to the enable signal; the control module 102 performs effective time reorganization on the enable signal according to the oscillation clock signal and outputs the target time; the counting module 103 performs period counting on the oscillation clock signal according to the enable signal to determine the target period number. In this way, the oscillation period of the target oscillator 1011 can be calculated based on the target time and the target period number.

[0041] Further, in some embodiments, refer to Figure 2 , which shows a schematic structural diagram of another oscillation period detection circuit 10 provided by the embodiments of the present application. As Figure 2 shown, the control module 102 includes a first flip-flop 1021, a second flip-flop 1022, and a third flip-flop 1023. The input terminal (D) of the first flip-flop 1021 is used to receive the enable signal, the input terminal (D) of the second flip-flop 1022 is connected to the output terminal (Q) of the first flip-flop 1021, and the input terminal (D) of the third flip-flop 1023 is connected to the output terminal (Q) of the second flip-flop 1022. Moreover, the clock terminals (CK) of the first flip-flop 1021, the second flip-flop 1022, and the third flip-flop 1023 are all used to receive the oscillation clock signal; among them,

[0042] The first flip-flop 1021 is specifically configured to sample the enable signal according to the oscillation clock signal and output a first control signal;

[0043] The second flip-flop 1022 is configured to sample the first control signal according to the oscillation clock signal and output a second control signal;

[0044] The third flip-flop 1023 is configured to sample the second control signal according to the oscillation clock signal and output a third control signal.

[0045] Here, the duration for which the first control signal is in the first level state is used to determine the target time, and the target time is an integer multiple of the oscillation period of the target oscillator; the second control signal is used to latch the target period number when flipping from the first level state to the second level state, and the third control signal is used to clear the counting module 103 when flipping from the first level state to the second level state.

[0046] It should be noted that the control module 102 is composed of a first trigger 1021, a second trigger 1022 and a third trigger 1023, and their specific connection relationship is as follows: Figure 2 As shown. A trigger is an electronic device that often appears in a logic circuit. The trigger includes a clock terminal and an input terminal. The trigger receives an oscillating clock signal through the clock terminal and samples the signal at the input terminal according to the oscillating clock signal.

[0047] The first trigger 1021, the second trigger 1022 and the third trigger 1023 can adopt triggers of various principles, and those skilled in the art can select them according to the actual application scenario. For example, the first trigger 1021, the second trigger 1022 and the third trigger 1023 can all adopt D-type triggers, which can sample the signal at the input end at the rising edge of the oscillation clock signal.

[0048] For the first flip-flop 1021, the enable signal is sampled at the rising edge of the oscillation clock signal, thereby outputting the first control signal. Figure 3 , which shows a signal waveform diagram of an oscillation period circuit provided by an embodiment of the present application. Figure 3 As shown, since the first trigger 1021 samples only at the rising edge of the oscillation clock signal, the first control signal can only change its level state at the rising edge of the oscillation clock signal, so the duration of the first control signal being in the first level state must be an integral multiple of the oscillation period of the target oscillator 1011. In other words, the first trigger 1021 is mainly used to reorganize the effective time of the enable signal to an integral multiple of the oscillation period (of the target oscillator), thereby determining the target time.

[0049] For the second trigger 1022, the first control signal is sampled at the rising edge of the oscillation clock signal, and then output as the second control signal. Figure 3 As shown, the effective time of the second control signal (the duration of being in the first level state) is delayed by one oscillation cycle (of the target oscillator) relative to the first control signal, and the second control signal is mainly used to latch the target cycle number.

[0050] For the third trigger 1023, the second control signal is sampled at the rising edge of the oscillation clock signal, and the output terminal is the third control signal. Figure 3 As shown, the effective time (duration of being in the first level state) of the third control signal is delayed by one oscillation cycle (of the target oscillator) relative to the second control signal, and is mainly used to clear the counting module 103 .

[0051] Further, in some embodiments, the oscillator module 101 is specifically configured to receive an enable signal and a third control signal, and control the target oscillator 1011 to output an oscillation clock signal when the enable signal is in the first level state or the third control signal is in the first level state; and control the target oscillator 1011 to stop outputting the oscillation clock signal when both the enable signal and the third control signal are in the second level state. In this way, the target oscillator is controlled by both the enable signal and the third control signal, avoiding premature stoppage of oscillation of the target oscillator and causing errors during the measurement process.

[0052] Therefore, in some embodiments, as Figure 2 shown, the oscillator module 101 further includes a NOR gate 1012 and a NOT gate 1013; wherein,

[0053] The NOR gate 1012 is configured to perform a NOR operation on the third control signal and the enable signal to obtain an operation result signal;

[0054] The NOT gate 1013 is configured to perform a NOT operation on the operation result signal to obtain an enable control signal;

[0055] The target oscillator 1011 is configured to receive the enable control signal and output an oscillation clock signal according to the enable control signal.

[0056] It should be noted that the third control signal and the enable signal are sequentially subjected to a NOR operation and a NOT operation to obtain an enable control signal, and the enable control signal is used to control the target oscillator 1011 to output a target oscillation signal.

[0057] Further, in some embodiments, as Figure 2 shown, the counting module 103 includes a counter 1031, and the input terminal, clock terminal, and reset terminal of the counter 1031 are respectively connected to the enable signal, the oscillation clock signal, and the third control signal; wherein,

[0058] The counter 1031 is configured to perform a periodic counting process on the oscillation clock signal when the enable signal is in the first level state, output a periodic counting signal, and the periodic counting signal is used to indicate the target period number; and perform a clearing process when the third control signal flips from the first level state to the second level state.

[0059] It should be noted that the counting module 103 mainly includes a counter 1031. For the counter 1031, the enable signal plays a gating role. When the enable signal is valid (in the first level state), the counter 1031 performs a periodic counting on the oscillation clock signal, thereby outputting a periodic counting signal; in addition, for the counter 1031, the third control signal is a reset signal, and when the third control signal flips from the first level state to the second level state, the count value of the counter 1031 is cleared.

[0060] Further, in some embodiments, the oscillation period detection circuit 10 further includes a latch 104, and two input terminals of the latch are respectively connected to the period counting signal and the second control signal; wherein,

[0061] The latch 104 is configured to latch the period counting signal when the second control signal flips from the first level state to the second level state, so as to implement the latching process of the target period quantity.

[0062] It should be noted that the input terminal of the latch 104 receives the period counting signal output by the counter 1031, and also receives the second control signal, and latches the period counting signal at the falling edge of the second control signal.

[0063] From the above, when the enable signal is in the first level state, the counter 1031 counts the periods of the oscillation clock signal; at the falling edge of the second control signal, the latch 104 latches the period counting signal output by the counter 1031, so as to obtain the target period quantity; at the falling edge of the third control signal, the count value of the counter 1031 is cleared.

[0064] It should also be noted that the first level state is a high level state, and the second level state is a low level state, but this does not constitute a limitation of the embodiments of the present application.

[0065] Please refer to Figure 4 , which shows a schematic diagram of a simulation test of an oscillation period circuit provided by an embodiment of the present application. As Figure 4 shown, the embodiments of the present application have adopted two simulation experiments in total. In the first simulation experiment, the target time is 1000 nanoseconds, and the period quantity is the simulation result: 592 (binary: 0000 0010 0101 0000), so that the oscillation period can be calculated as 1.69 nanoseconds; in the second simulation experiment, the oscillation period is the simulation result: 1.687 nanoseconds, and the calculated period quantity is 593 (binary: 0000 0010 0101 0001). From the above, it can be seen that the result of the oscillation period circuit provided by the embodiments of the present application is relatively accurate.

[0066] Table 1

[0067]

[0068] An embodiment of the present application provides an oscillation period detection circuit. The oscillation period detection circuit includes an oscillator module, which includes a target oscillator for receiving an enable signal and controlling the target oscillator to output an oscillation clock signal according to the enable signal; a control module for receiving the enable signal and the oscillation clock signal and performing effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time; a counting module for receiving the enable signal and the oscillation clock signal and performing period counting processing according to the enable signal and the oscillation clock signal to determine a target period number; wherein, the oscillation period of the target oscillator is calculated according to the target time and the target period number. In this way, the embodiment of the present application provides a novel circuit control structure, which is mainly applied to detecting the period of the internal oscillator of a chip and can also be used as an auxiliary circuit in the Propagation Delay Time (Tpd) test in Wafer Level Test (WAT); specifically, the enable signal and the oscillation clock signal are subjected to effective time reorganization processing to determine the target time, the enable signal and the oscillation clock signal are subjected to period counting to determine the target period number, and subsequently, the oscillation period can be calculated through the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period; in addition, the oscillation period detection circuit provided by the embodiment of the present application is applicable to both high-speed clocks and low-speed clocks and has a wide range of application scenarios.

[0069] In another embodiment of the present application, refer to Figure 5 , which shows a schematic flowchart of an oscillation period detection method provided by an embodiment of the present application. As Figure 5 shown, the method may include:

[0070] S201: Control a target oscillator to output an oscillation clock signal according to an enable signal.

[0071] It should be noted that the oscillation period detection method in the embodiment of the present application is applied to the aforementioned oscillation period detection circuit, and the oscillation period detection circuit includes a target oscillator. Here, the target oscillator can output an oscillation clock signal according to the enable signal. That is to say, the purpose of the oscillation period detection method provided by the embodiment of the present application is to detect the period of the oscillation clock signal.

[0072] S202: Perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time.

[0073] S203: Perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number.

[0074] It should be noted that an effective clock reshaping process is performed on the enable signal using an oscillating clock signal, reshaping the effective time of the enable signal into an integer multiple of the oscillation period, thereby obtaining a target time; and, a period counting process is performed on the oscillating clock signal using the enable signal to obtain a target period number.

[0075] Specifically, in some embodiments, the oscillation period detection circuit may include a first flip-flop, a second flip-flop, and a third flip-flop. Correspondingly, the method may further include:

[0076] Receiving the enable signal and the oscillating clock signal through the first flip-flop, and performing a sampling process according to the oscillating clock signal and the enable signal, and outputting a first control signal;

[0077] Receiving the first control signal and the oscillating clock signal through the second flip-flop, and performing a sampling process on the first control signal according to the oscillating clock signal, and outputting a second control signal;

[0078] Receiving the second control signal and the oscillating clock signal through the third flip-flop, and performing a sampling process on the second control signal according to the oscillating clock signal, and outputting a third control signal.

[0079] It should be noted that the first flip-flop mainly samples the enable signal at the rising edge of the oscillating clock signal to obtain the first control signal, thereby reshaping the effective time of the enable signal into an integer multiple of the oscillation period of the target oscillator, which is convenient for subsequent calculations. That is to say, the duration for which the first control signal is in the first level state is used to determine the target time, and the target time is an integer multiple of the oscillation period of the target oscillator.

[0080] The second flip-flop mainly samples the first control signal at the rising edge of the oscillating clock signal to obtain the second control signal. The effective time of the second control signal is delayed by one oscillation period (of the target oscillator) compared to the first control signal, thereby being used for latching the target period number. That is to say, the second control signal is used to latch the target period number when it flips from the first level state to the second level state.

[0081] The third flip-flop mainly samples the second control signal at the rising edge of the oscillating clock signal to obtain the third control signal. The effective time of the third control signal is delayed by one oscillation period (of the target oscillator) compared to the second control signal, and the third control signal is used to clear the counting module. That is to say, the third control signal is used to perform a clearing process when it flips from the first level state to the second level state.

[0082] In the above description, the effective time of a signal refers to the time when the signal is in the first level state.

[0083] Further, in some embodiments, the controlling the target oscillator to output an oscillation clock signal according to the enable signal may include:

[0084] When the enable signal is in the first level state or the third control signal is in the first level state, controlling the target oscillator to output an oscillation clock signal;

[0085] When both the enable signal and the third control signal are in the second level state, controlling the target oscillator to stop outputting the oscillation clock signal.

[0086] It should be noted that using the enable signal and the third control signal to control the target oscillator simultaneously can prevent the target oscillator from stopping oscillating prematurely, thus avoiding errors during the measurement process.

[0087] In a specific embodiment, the oscillation period detection circuit further includes a counter and a latch. Correspondingly, the performing period counting processing on the oscillation clock signal according to the enable signal to determine the target period number may include:

[0088] When the enable signal is in the first level state, performing period counting processing on the oscillation clock signal through the counter to output a period counting signal, and the period counting signal is used to indicate the target period number;

[0089] When the second control signal flips from the first level state to the second level state, performing latch processing on the period counting signal through the latch to achieve latch processing of the target period number.

[0090] It should be noted that when the enable signal is valid, the counter performs period counting on the oscillation clock signal and outputs a period counting signal. Meanwhile, at the falling edge of the second control signal, the latch latches the period counting signal to obtain the target period number.

[0091] It should be noted that the reset terminal of the counter is connected to the third control signal. Therefore, in some embodiments, the method may further include:

[0092] When the third control signal flips from the first level state to the second level state, controlling the counter to perform a clearing process.

[0093] In this way, after each test is completed, the count value of the counter will return to zero, waiting for the next test.

[0094] Further, in some embodiments, the controlling the target oscillator to output an oscillation clock signal according to the enable signal may include:

[0095] Performing a NOR operation on the third control signal and the enable signal to obtain an operation result signal;

[0096] Perform a NOT operation on the operation result signal to obtain an enable control signal;

[0097] According to the enable control signal, control the target oscillator to output an oscillation clock signal.

[0098] It should be noted that the third control signal and the enable signal are used to control the oscillation clock signal after NOR operation and NOT operation. In this way, when both the third control signal and the enable signal are in the second level state, the enable control signal is in the second level state, and the target oscillator stops outputting the target oscillation signal; when the third control signal is in the first level state or the enable signal is in the first level state, the enable control signal is in the first level state, and the target oscillator outputs the target oscillation signal.

[0099] In this way, through the above processing, the target number of periods of the oscillation clock signal within the target time can be obtained.

[0100] S204: Calculate the target time and the target number of periods to determine the oscillation period of the target oscillator.

[0101] It should be noted that after obtaining the target time and the target number of periods, the oscillation period of the target oscillator can be determined through a simple operation.

[0102] Specifically, the calculation of the target time and the target number of periods to determine the oscillation period of the target oscillator may include:

[0103] Divide the target time by the target number of periods to obtain the oscillation period of the target oscillator.

[0104] It should be noted that the oscillation period of the target oscillator = target time / target number of periods.

[0105] In another embodiment, since the first count value of the counter is 0, the exact number of periods of the oscillation period signal is actually (target number of periods + 1), that is, the exact oscillation period = target time / (target number of periods + 1). However, in a test, the number of general oscillation periods is relatively large, and the target number of periods can be used to replace (target number of periods + 1) for calculation, and the error is within an acceptable range.

[0106] It should also be noted that the first level state is a high level state, and the second level state is a low level state.

[0107] An embodiment of the present application provides an oscillation period detection method, which controls the target oscillator to output an oscillation clock signal according to an enable signal; performs effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time; performs period counting processing according to the enable signal and the oscillation clock signal to determine a target period number; calculates the target time and the target period number to determine the oscillation period of the target oscillator. In this way, the enable signal and the oscillation clock signal are subjected to effective time reorganization processing to determine the target time, and the enable signal and the oscillation clock signal are subjected to period counting to determine the target period number. Subsequently, the oscillation period can be calculated through the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0108] In another embodiment of the present application, refer to Figure 6 , which shows a semiconductor memory 30 provided by an embodiment of the present application. The semiconductor memory 30 at least includes the foregoing oscillation period detection circuit 10.

[0109] For the semiconductor memory 30, since it includes the oscillation period detection circuit 10, during the oscillation period detection process, the enable signal and the oscillation clock signal are used for effective time reorganization processing to determine the target time, and the enable signal and the oscillation clock signal are subjected to period counting to determine the target period number. Subsequently, the oscillation period can be calculated through the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0110] In yet another embodiment of the present application, an electronic device is provided, which at least includes the foregoing semiconductor memory 30.

[0111] For the electronic device, since it includes the semiconductor memory 30, during the oscillation period detection process, the enable signal and the oscillation clock signal are used for effective time reorganization processing to determine the target time, and the enable signal and the oscillation clock signal are subjected to period counting to determine the target period number. Subsequently, the oscillation period can be calculated through the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0112] The above is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

[0113] It should be noted that in this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element.

[0114] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0115] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0116] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0117] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0118] As mentioned above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An oscillation period detection circuit, characterized in that, Comprising: An oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; A control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time; A counting module, configured to receive the enable signal and the oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine a target cycle number; Wherein, the oscillation period of the target oscillator is calculated according to the target time and the target cycle number; The control module includes a first flip-flop, a second flip-flop, and a third flip-flop. The input terminal (D) of the first flip-flop is configured to receive the enable signal. The input terminal (D) of the second flip-flop is connected to the output terminal (Q) of the first flip-flop. The input terminal (D) of the third flip-flop is connected to the output terminal (Q) of the second flip-flop. And the clock terminals (CK) of the first flip-flop, the second flip-flop, and the third flip-flop are all configured to receive the oscillation clock signal; wherein, The first flip-flop is specifically configured to sample the enable signal according to the oscillation clock signal and output a first control signal; The second flip-flop is configured to sample the first control signal according to the oscillation clock signal and output a second control signal; The third flip-flop is configured to sample the second control signal according to the oscillation clock signal and output a third control signal; Wherein, the duration of the first control signal in the first level state is used to determine the target time, and the target time is an integer multiple of the oscillation period of the target oscillator; the second control signal is used to latch the target cycle number when flipping from the first level state to the second level state, and the third control signal is used to clear the counting module when flipping from the first level state to the second level state; The oscillator module is specifically configured to receive the enable signal and the third control signal, control the target oscillator to output the oscillation clock signal when the enable signal is in the first level state or the third control signal is in the first level state; and control the target oscillator to stop outputting the oscillation clock signal when both the enable signal and the third control signal are in the second level state.

2. The oscillation period detection circuit according to claim 1, wherein The counting module includes a counter. The input terminal, clock terminal, and reset terminal of the counter are respectively connected to the enable signal, the oscillation clock signal, and the third control signal; wherein, The counter is configured to perform cycle counting processing on the oscillation clock signal when the enable signal is in the first level state and output a cycle counting signal, and the cycle counting signal is used to indicate the target cycle number; and perform a clearing process when the third control signal flips from the first level state to the second level state.

3. The oscillation period detection circuit according to claim 2, wherein The oscillation period detection circuit further includes a latch, and two input terminals of the latch are respectively connected to the period counting signal and the second control signal; wherein, The latch is configured to latch the period counting signal when the second control signal flips from the first level state to the second level state, so as to implement the latching process of the target period quantity.

4. The oscillation period detection circuit according to claim 1, wherein The oscillator module further includes a NOR gate and a NOT gate; The NOR gate is configured to perform a NOR operation on the third control signal and the enable signal to obtain an operation result signal; The NOT gate is configured to perform a NOT operation on the operation result signal to obtain an enable control signal; The target oscillator is configured to receive the enable control signal and output the oscillation clock signal according to the enable control signal.

5. The oscillation period detection circuit according to claim 1, wherein The first flip-flop, the second flip-flop, and the third flip-flop are all D-type flip-flops.

6. The oscillation period detection circuit according to any one of claims 1-5, characterized in that, The first level state is a high level state, and the second level state is a low level state.

7. An oscillation period detection method, characterized in that, Applied to an oscillation period detection circuit including a target oscillator, the method includes: Controlling the target oscillator to output an oscillation clock signal according to the enable signal; Performing effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time; Performing period counting processing according to the enable signal and the oscillation clock signal to determine a target period quantity; Calculating the target time and the target period quantity to determine the oscillation period of the target oscillator; The oscillation period detection circuit includes a first flip-flop, a second flip-flop, and a third flip-flop; the method further includes: Receiving the enable signal and the oscillation clock signal through the first flip-flop, and performing sampling processing according to the oscillation clock signal and the enable signal to output a first control signal; Receiving the first control signal and the oscillation clock signal through the second flip-flop, and performing sampling processing on the first control signal according to the oscillation clock signal to output a second control signal; Receiving the second control signal and the oscillation clock signal through the third flip-flop, and performing sampling processing on the second control signal according to the oscillation clock signal to output a third control signal; Wherein, the duration of the first control signal in the first level state is used to determine the target time, and the target time is an integer multiple of the oscillation period of the target oscillator; the second control signal is used to latch the target period quantity when flipping from the first level state to the second level state, and the third control signal is used to perform a clearing process when flipping from the first level state to the second level state; The controlling the target oscillator to output an oscillation clock signal according to the enable signal includes: When the enable signal is in the first level state or the third control signal is in the first level state, controlling the target oscillator to output the oscillation clock signal; When both the enable signal and the third control signal are in the second level state, controlling the target oscillator to stop outputting the oscillation clock signal.

8. The oscillation period detection method according to claim 7, characterized in that The oscillation period detection circuit includes a counter and a latch. The period counting process of the oscillation clock signal according to the enable signal to determine the target period quantity includes: When the enable signal is in the first level state, the counter performs a period counting process on the oscillation clock signal to output a period counting signal, and the period counting signal is used to indicate the target period quantity; When the second control signal flips from the first level state to the second level state, the latch performs a latching process on the period counting signal to implement the latching process of the target period quantity.

9. The oscillation period detection method according to claim 8, wherein The method further includes: When the third control signal flips from the first level state to the second level state, controlling the counter to perform a clearing process.

10. The oscillation period detection method according to claim 8, characterized in that, The controlling the target oscillator to output an oscillation clock signal according to the enable signal includes: Performing a NOR operation on the third control signal and the enable signal to obtain an operation result signal; Performing a NOT operation on the operation result signal to obtain an enable control signal; Controlling the target oscillator to output the oscillation clock signal according to the enable control signal.

11. The oscillation period detection method according to any one of claims 7-10, characterized in that, The calculating the target time and the target period quantity to determine the oscillation period of the target oscillator includes: Dividing the target time by the target period quantity to obtain the oscillation period of the target oscillator.

12. The oscillation period detection method according to any one of claims 7-11, characterized in that, The first level state is a high level state, and the second level state is a low level state.

13. A semiconductor memory, characterized in that, The semiconductor memory at least includes the oscillation period detection circuit according to any one of claims 1-6.

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