Non-extractive image processing method and apparatus

Abstract

The present disclosure provides a non-downsampling image processing method and device, the non-downsampling image processing method comprising: obtaining a to-be-processed image; inputting the to-be-processed image into an image processing network to obtain an output image for output, the resolution of the output image being the same as that of the to-be-processed image; wherein the image processing network comprises an analysis module, a synthesis module and at least one processing module; inputting the to-be-processed image into the image processing network to obtain the output image for output comprises: inputting the to-be-processed image into the analysis module for feature analysis and outputting a feature tensor image; inputting the feature tensor image into the processing module for processing and outputting a processed feature tensor image, the resolution of the feature tensor image output by the processing module being the same as that of the to-be-processed image; and obtaining the output image by synthesizing the feature tensor images output by the at least one processing module through the synthesis module.

Description

Technical Field

[0001] This disclosure relates to the field of image processing technology, and in particular to a non-extraction image processing method and apparatus. Background Technology

[0002] Convolutional Neural Networks (CNNs) are a type of neural network that uses images as input and output, and replaces scalar weights with filters (convolutional layers).

[0003] Current convolutional neural networks need to perform upsampling and downsampling operations, such as pooling, during image processing. These upsampling and downsampling operations will lose information in the feature map, resulting in distorted image processing results. Summary of the Invention

[0004] This disclosure provides a non-extraction image processing method and apparatus to address the problem that upsampling and downsampling operations in existing convolutional neural networks lose information in feature maps during image processing.

[0005] To solve the above-mentioned technical problems, this disclosure is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a non-extractive image processing method, including:

[0007] Obtain the image to be processed;

[0008] The image to be processed is input into an image processing network to obtain an output image, the resolution of which is the same as that of the image to be processed.

[0009] The image processing network includes an analysis module, a synthesis module, and at least one processing module; the image to be processed is input into the image processing network to obtain an output image, which includes:

[0010] The image to be processed is input into the analysis module for feature analysis, and then a feature tensor image is output.

[0011] The feature tensor image is input into the processing module for processing and then the processed feature tensor image is output. The resolution of the feature tensor image output by the processing module is the same as the resolution of the image to be processed.

[0012] The output image is obtained by synthesizing the feature tensor images output by at least one of the processing modules through the synthesis module.

[0013] Furthermore, the image processing network includes multiple analysis modules; the image to be processed is input into the analysis modules for feature analysis, and a feature tensor image is output, specifically including:

[0014] The image to be processed is input into the multiple analysis modules for feature analysis, and each module outputs a feature tensor image with a preset number of channels. The number of channels in the feature tensor image output by each analysis module is different.

[0015] Furthermore, the processing module includes: multiple micro-scale enlargement modules and multiple micro-scale reduction modules, which are interconnected to form the processing module; the feature tensor image is input into the processing module for processing and then outputs the processed feature tensor image, specifically including:

[0016] The feature tensor image is input to the micro-scale upscaling module for micro-scale upscaling processing, and the micro-scale upscaling processed feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale upscaling module is less than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is greater than the resolution of the input feature tensor image.

[0017] The feature tensor image is input to the micro-scale reduction module for micro-scale reduction processing, and the micro-scale reduced feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale reduction module is greater than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is less than the resolution of the input feature tensor image.

[0018] The multiple analysis modules are arranged in descending order of the number of output channels. In the processing module, the feature tensor image output by each analysis module is spliced ​​together with the feature tensor images output by all the preceding analysis modules and the last analysis module after being processed by the microscale enlargement module and / or microscale reduction module, and then output.

[0019] The process of synthesizing at least one feature tensor image input from the processing module to obtain the output image via the synthesis module specifically includes:

[0020] Furthermore, the input feature tensor image is synthesized by the synthesis module to obtain an output image with the same format as the image to be processed, and the number of channels of the output image is the same as the number of channels of the image to be processed.

[0021] Furthermore, the image processing network includes multiple processing modules connected in sequence, with the output of one processing module serving as the input of the next processing module.

[0022] Furthermore, the number of output channels of two adjacent analysis modules is a multiple of M, where M is an integer greater than 1.

[0023] Furthermore, the analysis module is implemented using a single convolutional layer.

[0024] Furthermore, the synthesis module is implemented using a single convolutional layer.

[0025] Furthermore, the microscale enlargement module is implemented using a transposed convolutional layer with a stride of 1.

[0026] Furthermore, the microscale reduction module is implemented using a convolutional layer with a stride of 1.

[0027] Furthermore, the ratio of the resolution of the feature tensor image output by the microscale enlargement module to the resolution of the input feature tensor image is 1+ε, where ε is a value greater than 0 and less than 1.

[0028] Furthermore, the ratio of the resolution of the input feature tensor image to the resolution of the output feature tensor image of the microscale reduction module is 1+ε, where ε is a value greater than 0 and less than 1.

[0029] In a second aspect, embodiments of this disclosure provide a non-extraction image processing apparatus, comprising:

[0030] The acquisition unit is used to acquire the image to be processed;

[0031] An execution unit is configured to input the image to be processed into an image processing network, obtain an output image, and output the output image with the same resolution as the image to be processed.

[0032] The image processing network includes an analysis module, a synthesis module, and at least one processing module; the image to be processed is input into the image processing network to obtain an output image, which includes:

[0033] The image to be processed is input into the analysis module for feature analysis, and then a feature tensor image is output.

[0034] The feature tensor image is input into the processing module for processing and then the processed feature tensor image is output. The resolution of the feature tensor image output by the processing module is the same as the resolution of the image to be processed.

[0035] The output image is obtained by synthesizing the feature tensor images output by at least one of the processing modules through the synthesis module.

[0036] Thirdly, embodiments of this disclosure provide an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the non-extraction image processing method described in the first aspect.

[0037] Fourthly, embodiments of this disclosure provide a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the non-extraction image processing method described in the first aspect.

[0038] In this embodiment of the disclosure, the processing module in the image processing network performs non-extraction operations on the input feature tensor image, which can avoid the information loss of the feature tensor image caused by the extraction operation in the image processing process and improve the image processing effect. Attached Figure Description

[0039] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0040] Figure 1 This is a schematic flowchart of an image processing method according to an embodiment of the present disclosure;

[0041] Figure 2 This is a schematic diagram of the structure of the image processing network according to an embodiment of the present disclosure;

[0042] Figure 3 This is a schematic diagram of the structure of a dense network;

[0043] Figure 4 This is a schematic diagram of the structure of an image processing apparatus according to an embodiment of the present disclosure;

[0044] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0045] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] Please refer to Figure 1 , Figure 1This is a flowchart illustrating a non-extraction image processing method according to an embodiment of the present disclosure. The non-extraction image processing method includes:

[0047] Step 11: Obtain the image to be processed;

[0048] Step 12: Input the image to be processed into the image processing network to obtain an output image, the resolution of which is the same as that of the image to be processed;

[0049] The image processing network includes an analysis module, a synthesis module, and at least one processing module; the image to be processed is input into the image processing network to obtain an output image, which includes:

[0050] The image to be processed is input into the analysis module for feature analysis, and then a feature tensor image is output.

[0051] The feature tensor image is input into the processing module for processing and then the processed feature tensor image is output. The resolution of the feature tensor image output by the processing module is the same as the resolution of the image to be processed.

[0052] The output image is obtained by synthesizing the feature tensor images output by at least one of the processing modules through the synthesis module.

[0053] In this embodiment of the disclosure, "non-decompression" means that no upsampling or downsampling operations (such as pooling) are performed during image processing.

[0054] In this embodiment of the disclosure, the processing module in the image processing network performs a non-decomposition operation on the input feature tensor image (the resolution of the output feature tensor image is the same as the resolution of the image to be processed), which can avoid the information loss of the feature tensor image caused by the decomposition operation in the image processing process and improve the image processing effect.

[0055] In some embodiments of this disclosure, optionally, the image processing network includes multiple analysis modules. The image to be processed is input into the analysis modules for feature analysis and then outputs a feature tensor image. Specifically, the image to be processed is input into the multiple analysis modules for feature analysis and each outputs a feature tensor image with a preset number of channels. The number of channels in the feature tensor image output by each analysis module is different. Figure 2 In the embodiment shown, the image processing network includes five analysis modules. Of course, in other embodiments of this disclosure, the number of analysis modules is not limited to this.

[0056] In this embodiment of the disclosure, optionally, the plurality of analysis modules are arranged in descending order of the number of output channels, and the multiple of the number of output channels between two adjacent analysis modules is M, where M is an integer greater than 1. For example, Figure 2 In the illustrated embodiment, the five analysis modules are arranged in descending order of the number of output channels, from bottom to top: 256, 128, 64, 32, and 16. The number of output channels of two adjacent analysis modules is twice that of each other.

[0057] In this embodiment of the disclosure, the analysis module can receive various types of images, such as grayscale images, RGB images, or YUV images, and output feature tensor images. For example, assuming the input to the analysis module is an RGB image with three channels (R, G, and B), the output can be a preset number of channels (16, 32, 64, 128, 256, etc.).

[0058] In this embodiment of the disclosure, optionally, the analysis module is implemented using a single convolutional layer.

[0059] In this embodiment of the disclosure, optionally, the processing module includes: multiple micro-scale enlargement modules and multiple micro-scale reduction modules, wherein the multiple micro-scale enlargement modules and the multiple micro-scale reduction modules are interconnected to form the processing module; inputting the feature tensor image into the processing module for processing and outputting the processed feature tensor image specifically includes:

[0060] The feature tensor image is input to the micro-scale upscaling module for micro-scale upscaling processing, and the micro-scale upscaling processed feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale upscaling module is less than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is greater than the resolution of the input feature tensor image.

[0061] The feature tensor image is input to the microscale reduction module for microscale reduction processing, and the microscale-reduced feature tensor image is output. The number of channels of the feature tensor image output by the microscale reduction module is greater than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is less than the resolution of the input feature tensor image.

[0062] In this embodiment, the padding of the micro-scale augmentation module is set to 0. Padding refers to increasing the size of the feature tensor image after passing through the convolution kernel to offset the effect of size shrinkage during computation. That is, in this embodiment, the feature tensor image is not padded after convolution; instead, some pixels are added directly to the border of the feature tensor image during convolution, making the resolution of the output feature tensor image slightly larger than the resolution of the input feature tensor image. For example, if the convolution kernel size is 3×3, then a row of pixels can be added to the left, right, top, and bottom of the feature tensor image. Further optionally, the ratio of the resolution of the feature tensor image output by the micro-scale augmentation module to the resolution of the input feature tensor image is 1+ε, where ε is a value greater than 0 and less than 1. For example, if the resolution of the input feature tensor image is 640×640 and the convolution kernel size is 3×3 (adding one row of pixels vertically and horizontally respectively), then ε = (1+1) / 640 = 0.31%. The micro-scale augmentation module processes the input feature tensor image and outputs a feature tensor image with fewer channels and slightly higher resolution (compared to the input feature tensor). Optionally, in this embodiment, the micro-scale augmentation module is implemented using a transposed convolutional layer with a stride of 1.

[0063] In this embodiment of the disclosure, optionally, the padding of the micro-scale reduction module is set to 0. That is, in this embodiment, the feature tensor image is not padded after convolution; instead, during convolution, some pixels are directly reduced from the borders of the feature tensor image, making the resolution of the output feature tensor image slightly lower than the resolution of the input feature tensor image. For example, if the convolution kernel size is 3×3, then one row of pixels can be reduced from the left, right, top, and bottom of the feature tensor image. Further optionally, the ratio of the resolution of the input feature tensor image to the resolution of the output feature tensor image of the micro-scale reduction module is 1+ε, where ε is a value greater than 0 and less than 1. That is, the micro-scale reduction module processes the input feature tensor image, increasing the number of channels and outputting a feature tensor image with a slightly lower resolution (compared to the input feature tensor). In this embodiment of the disclosure, optionally, the micro-scale reduction module is implemented using a convolutional layer with a stride of 1.

[0064] In this embodiment of the present disclosure, optionally, the step of synthesizing the feature tensor images input by at least one of the processing modules to obtain the output image through the synthesis module specifically includes: synthesizing the input feature tensor images through the synthesis module to obtain an output image with the same format as the image to be processed, wherein the number of channels of the output image is the same as the number of channels of the image to be processed. That is, the resolution of the output image of the synthesis module is equal to the resolution of the input image to be processed. In other words, the synthesis module can input feature tensor images with any number of channels and output an output image with the same number of channels as the image to be processed input by the image processing network. For example, the synthesis module can reduce the number of channels from multiple channels to three (R, G, B) or one (grayscale) channel. In this embodiment of the present disclosure, optionally, the synthesis module is implemented using a single convolutional layer.

[0065] In this embodiment of the disclosure, optionally, the plurality of analysis modules are arranged in descending order of the number of output channels. In the processing module, the feature tensor image output by each analysis module is concatted with the feature tensor images output by all the preceding analysis modules and the last analysis module after being processed by the microscale enlargement module and / or microscale reduction module.

[0066] Figure 2 The plus sign in the diagram indicates an addition operation on an array (also called a matrix, vector, tensor, or feature map).

[0067] In this embodiment of the disclosure, optionally, the image processing network includes multiple processing modules connected in sequence, with the output of the previous processing module serving as the input of the next processing module.

[0068] In this embodiment of the disclosure, please refer to Figure 2 The image processing network in this embodiment of the present disclosure uses an input image, and during the image processing, the resolution of the input image can be reduced to the following resolution levels: (1+4ε)×, (1+3ε)×, (1+2ε)×, (1+ε)×, 1×.

[0069] from Figure 2 It can be seen from this that Figure 2The image processing network in this embodiment has a W-loop structure, where the number of W's is two. However, in other embodiments of this disclosure, the number of W's can be more than two, and this disclosure does not limit this. From the first step, the input image is available at all channel count levels, so the W-loop operates with multi-channel capacity, similar to a full microgrid algorithm. Back-projection provides short skip connections at high channel counts and long skip connections at low channel counts. Therefore, the image processing network in this embodiment can be called a micro-grid back-projection (mGBP) network.

[0070] In this embodiment, a multi-level micro-mesh back projection method is adopted. By scaling down at a microscale, the signal extraction process (such as various downsampling methods, various pooling operations, and dilated convolution) in existing methods is avoided. Therefore, this method can ensure that all parts of the entire processing system retain the high resolution of the original input image, thereby avoiding the loss of important information of the original image and the internal feature map of the system during the processing.

[0071] In addition, please refer to Figure 2 As can be seen, in this embodiment of the disclosure, the image processing network is similar to a densely connected network and can provide skip connections. For a densely connected network, please refer to [link to relevant documentation]. Figure 3 The convolutional layers are connected sequentially, and all layers are skip-connected to each other. The number of connections grows exponentially, and gradients during backpropagation can access any layer in the network in one step. By connecting all layers in the network to each other, each layer receives features from all the layers preceding it as input, introducing the concepts of shared features and arbitrary inter-layer interconnections. This greatly alleviates the problem of gradient vanishing during training in deep networks, which makes optimization difficult, and also reduces the size and computational cost of image processing networks.

[0072] The image processing method in this embodiment is a non-extractive, original-resolution-preserving, multi-level image transformation method.

[0073] The image processing network described in this embodiment can be used in convolutional neural networks, other deep neural networks, or non-deep learning networks.

[0074] The image processing method in this embodiment can be used to process a single image or a video composed of a sequence of video frames. Please refer to... Figure 2When the image processing method in this embodiment is used to process a single image, each module in the image processing network of this disclosure uses a 2D convolutional layer. When the image processing method in this embodiment is used to process a video composed of a sequence of frames, each module in the image processing network of this disclosure uses a 3D convolutional layer.

[0075] In this embodiment of the disclosure, during the training process of the above-mentioned image processing network, a fidelity (distortion) loss function can be used to determine the loss of the image processing network. The fidelity loss function is: L L1 (x, y) = E[|xy|], where E represents the approximate expected value of the average value over a set of samples, x is the expected value, and y is the true value. L1 refers to the L1 loss function for fidelity.

[0076] During the training process of the above image processing network, the following metrics can be used to validate the image processing network:

[0077] γ=L L2 (x, y)

[0078] Among them, L L2 (x, y) = E[(xy)] 2 This is equivalent to the mean square error (MSE) directly related to the peak signal-to-noise ratio (PSNR). L2 refers to the L2 loss.

[0079] In summary, the image processing method of this disclosure has the following advantages:

[0080] 1) The processing module in the image processing network performs non-extraction operations on the input feature tensor image, which can avoid the information loss of the feature tensor image caused by the extraction operation in the image processing process and improve the image processing effect.

[0081] 2) Image processing networks have a hierarchical structure, which allows skip connections to grow linearly rather than exponentially. Therefore, dense structures are possible.

[0082] The image processing method in this embodiment can be used for repairing (restoring or reconstructing), rebuilding or enhancing images while maintaining their original resolution.

[0083] Please refer to Figure 4 This disclosure also provides a non-extraction image processing apparatus 40, comprising:

[0084] Acquisition unit 41 is used to acquire the image to be processed;

[0085] The execution unit 42 is used to input the image to be processed into the image processing network to obtain an output image for output, wherein the resolution of the output image is the same as the resolution of the image to be processed;

[0086] The image processing network includes an analysis module, a synthesis module, and at least one processing module; the image to be processed is input into the image processing network to obtain an output image, which includes:

[0087] The image to be processed is input into the analysis module for feature analysis, and then a feature tensor image is output.

[0088] The feature tensor image is input into the processing module for processing and then the processed feature tensor image is output. The resolution of the feature tensor image output by the processing module is the same as the resolution of the image to be processed.

[0089] The output image is obtained by synthesizing the feature tensor images output by at least one of the processing modules through the synthesis module.

[0090] Furthermore, the image processing network includes multiple analysis modules; the execution unit is used to input the image to be processed into the multiple analysis modules for feature analysis, and output feature tensor images with a preset number of channels respectively, wherein the number of channels of the feature tensor images output by each analysis module is different.

[0091] Furthermore, the processing module includes: multiple microscale enlargement modules and multiple microscale reduction modules, wherein the multiple microscale enlargement modules and the multiple microscale reduction modules are interconnected to form the processing module;

[0092] The microscale upscaling module is used to perform microscale upscaling processing on the input feature tensor image and output the microscale upscaling processed feature tensor image. The number of channels of the feature tensor image output by the microscale upscaling module is less than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is greater than the resolution of the input feature tensor image.

[0093] The microscale reduction module is used to perform microscale reduction processing on the input feature tensor image and output the microscale reduced feature tensor image. The number of channels of the feature tensor image output by the microscale reduction module is greater than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is less than the resolution of the input feature tensor image.

[0094] The multiple analysis modules are arranged in descending order of the number of output channels. In the processing module, the feature tensor image output by each analysis module is spliced ​​together with the feature tensor images output by all the preceding analysis modules and the last analysis module after being processed by the microscale enlargement module and / or microscale reduction module, and then output.

[0095] Furthermore, the synthesis module is used to process the input feature tensor image to obtain an output image with the same format as the image to be processed, wherein the number of channels of the output image is the same as the number of channels of the image to be processed.

[0096] Furthermore, the image processing network includes multiple processing modules connected in sequence, with the output of one processing module serving as the input of the next processing module.

[0097] Furthermore, the number of output channels of two adjacent analysis modules is a multiple of M, where M is an integer greater than 1.

[0098] Furthermore, the ratio of the resolution of the feature tensor image output by the microscale enlargement module to the resolution of the input feature tensor image is 1+ε, where ε is a value greater than 0 and less than 1.

[0099] Furthermore, the ratio of the resolution of the input feature tensor image to the resolution of the output feature tensor image of the microscale reduction module is 1+ε, where ε is a value greater than 0 and less than 1.

[0100] Furthermore, the analysis module is implemented using a single convolutional layer.

[0101] Furthermore, the synthesis module is implemented using a single convolutional layer.

[0102] Furthermore, the microscale enlargement module is implemented using a transposed convolutional layer with a stride of 1.

[0103] Furthermore, the microscale reduction module is implemented using a convolutional layer with a stride of 1.

[0104] Please refer to Figure 5 This disclosure also provides an electronic device 50, including a processor 51, a memory 52, and a program or instructions stored in the memory 52 and executable on the processor 51. When the program or instructions are executed by the processor 51, they implement the various processes of the above-described image processing method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0105] This disclosure also provides a readable storage medium storing a program or instructions. When executed by a processor, the program or instructions implement the various processes of the above-described image processing method embodiments and achieve the same technical effects. To avoid repetition, further details are omitted here. The computer-readable storage medium may include read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0106] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0107] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0108] The embodiments of this disclosure have been described above with reference to the accompanying drawings. However, this disclosure is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this disclosure without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this disclosure.

Claims

1. A non-extraction image processing method, characterized in that, include: Obtain the image to be processed; The image to be processed is input into an image processing network to obtain an output image, the resolution of which is the same as that of the image to be processed. The image processing network includes an analysis module, a synthesis module, and at least one processing module; the image to be processed is input into the image processing network to obtain an output image, which includes: The image to be processed is input into the analysis module for feature analysis, and then a feature tensor image is output. The feature tensor image is input into the processing module for processing and then the processed feature tensor image is output. The resolution of the feature tensor image output by the processing module is the same as the resolution of the image to be processed. The output image is obtained by synthesizing the feature tensor images output by at least one of the processing modules through the synthesis module; The processing module includes: multiple micro-scale enlargement modules and multiple micro-scale reduction modules, which are interconnected to form the processing module; the processing module inputs the feature tensor image into the processing module for processing and outputs the processed feature tensor image, specifically including: The feature tensor image is input to the micro-scale upscaling module for micro-scale upscaling processing, and the micro-scale upscaling processed feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale upscaling module is less than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is greater than the resolution of the input feature tensor image. The feature tensor image is input to the micro-scale reduction module for micro-scale reduction processing, and the micro-scale reduced feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale reduction module is greater than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is less than the resolution of the input feature tensor image. Among them, multiple analysis modules are arranged in descending order of the number of output channels. In the processing module, the feature tensor image output by each analysis module is spliced ​​with the feature tensor images output by all the preceding analysis modules and the last analysis module after being processed by the microscale enlargement module and / or microscale reduction module, and then output. The microscale augmentation module is implemented using a transposed convolutional layer with a stride of 1; The ratio of the resolution of the feature tensor image output by the microscale augmentation module to the resolution of the input feature tensor image is 1+ε, where ε is a value greater than 0 and less than 1.

2. The method according to claim 1, characterized in that, The image processing network includes multiple analysis modules; the image to be processed is input into the analysis modules for feature analysis, and then a feature tensor image is output. Specifically, this includes: The image to be processed is input into the multiple analysis modules for feature analysis, and each module outputs a feature tensor image with a preset number of channels. The number of channels in the feature tensor image output by each analysis module is different.

3. The method according to claim 1, characterized in that: The process of synthesizing at least one feature tensor image input from the processing module to obtain the output image via the synthesis module specifically includes: The synthesis module synthesizes the input feature tensor image to obtain an output image with the same format as the image to be processed, and the number of channels in the output image is the same as the number of channels in the image to be processed.

4. The method according to claim 1, characterized in that, The image processing network includes multiple processing modules connected in sequence, with the output of one processing module serving as the input of the next.

5. The method according to claim 1, characterized in that, The number of output channels of two adjacent analysis modules is a multiple of M, where M is an integer greater than 1.

6. The method according to any one of claims 1-5, characterized in that, The analysis module is implemented using a single convolutional layer.

7. The method according to any one of claims 1-5, characterized in that, The synthesis module is implemented using a single convolutional layer.

8. The method according to claim 1, characterized in that, The microscale reduction module is implemented using a convolutional layer with a stride of 1.

9. The method according to claim 1 or 8, characterized in that, The ratio of the resolution of the input feature tensor image to the resolution of the output feature tensor image of the microscale reduction module is 1+ε, where ε is a value greater than 0 and less than 1.

10. A non-extraction image processing apparatus, characterized in that, include: The acquisition unit is used to acquire the image to be processed; An execution unit is configured to input the image to be processed into an image processing network, obtain an output image, and output the output image with the same resolution as the image to be processed. The image processing network includes an analysis module, a synthesis module, and at least one processing module; the image to be processed is input into the image processing network to obtain an output image, which includes: The image to be processed is input into the analysis module for feature analysis, and then a feature tensor image is output. The feature tensor image is input into the processing module for processing and then the processed feature tensor image is output. The resolution of the feature tensor image output by the processing module is the same as the resolution of the image to be processed. The output image is obtained by synthesizing the feature tensor images output by at least one of the processing modules through the synthesis module; The processing module includes multiple micro-scale enlargement modules and multiple micro-scale reduction modules, which are interconnected to form the processing module. The module processes the feature tensor image by inputting it into the processing module and then outputting the processed feature tensor image, specifically including: The feature tensor image is input to the micro-scale upscaling module for micro-scale upscaling processing, and the micro-scale upscaling processed feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale upscaling module is less than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is greater than the resolution of the input feature tensor image. The feature tensor image is input to the micro-scale reduction module for micro-scale reduction processing, and the micro-scale reduced feature tensor image is output. The number of channels of the feature tensor image output by the micro-scale reduction module is greater than the number of channels of the input feature tensor image, and the resolution of the output feature tensor image is less than the resolution of the input feature tensor image. Among them, multiple analysis modules are arranged in descending order of the number of output channels. In the processing module, the feature tensor image output by each analysis module is spliced ​​with the feature tensor images output by all the preceding analysis modules and the last analysis module after being processed by the microscale enlargement module and / or microscale reduction module, and then output. The microscale augmentation module is implemented using a transposed convolutional layer with a stride of 1; The ratio of the resolution of the feature tensor image output by the microscale augmentation module to the resolution of the input feature tensor image is 1+ε, where ε is a value greater than 0 and less than 1.

11. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the non-extractive image processing method as described in any one of claims 1-9.

12. A non-transient computer-readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the non-extractive image processing method as described in any one of claims 1-9.

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