Voltage regulator circuit for forced continuous current mode in multi-phase circuits

Abstract

The embodiments of the present disclosure provide a voltage stabilization circuit for a forced continuous current mode in a multi-phase circuit. The circuit comprises a main-phase PWM signal regulation circuit and a plurality of sub-phase PWM signal regulation circuits. The main-phase PWM signal regulation circuit outputs a main-phase PWM signal that flips from a low level to a high level according to the rising edge of a time-controlled pulse signal when the main-phase inductor current drops to 0A and the duration does not reach a preset off-time, or according to the falling edge of a main-phase inductor current judgment signal when the main-phase inductor current drops to 0A and the duration reaches a preset off-time; each sub-phase PWM signal regulation circuit outputs a sub-phase PWM signal that flips from a low level to a high level according to the rising edge of a time-delay pulse signal when the sub-phase inductor current drops to 0A and the duration does not reach a preset off-time, or according to the falling edge of a sub-phase inductor current judgment signal when the sub-phase inductor current drops to 0A and the duration reaches a preset off-time.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a voltage stabilizing circuit for a forced continuous current mode (FCCM) in a multi-phase circuit. Background Art

[0002] In a traditional multi-phase control circuit operating in FCCM mode, when all phases are on and the output voltage is high, to lower the output voltage, the peak currents of all inductors in the multi-phase control circuit must be clamped to 0A. This, combined with an adaptive off-time voltage regulation method, ensures that the average inductor current in the enabled phases is negative, effectively dissipating energy. However, in applications with low switching frequencies, such as 500K or 250K with high duty cycles, the long off-time calculated by the circuit leads to a high negative absolute value of the DC inductor current at the 0A peak limit. This rapid discharge of the high absolute value of the negative inductor current causes the output voltage to drop significantly, rapidly releasing the circuit from clamping, causing the EAO (Error Amplification Output) signal to rebound sharply. Under these conditions, the sudden increase in the instantaneous peak inductor current leads to a significant accumulation of energy, causing the output voltage to rebound sharply, which in turn causes the EAO signal to drop again. This cycle repeats, resulting in large-signal oscillation in the system. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide a voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit, which enables the low-frequency multi-phase circuit to slowly discharge when entering the 0A peak current clamp under FCCM, and the EAO signal to slowly recover after exiting the clamp. The output voltage is regulated by the loop to be stable, avoiding the large signal oscillation problem caused by the high absolute value negative current during clamping in traditional multi-phase circuits.

[0004] To achieve the above objectives, an embodiment of the present disclosure provides a voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit, comprising: a main phase pulse width modulation (PWM) signal regulating circuit and a plurality of auxiliary phase PWM signal regulating circuits. The main phase PWM signal regulation circuit is configured to output a main phase PWM signal that flips from a low level to a high level according to the rising edge of a time control pulse signal when the main phase inductor current in the main phase circuit drops to 0 A and the duration does not reach a preset off time; or output a main phase PWM signal that flips from a low level to a high level according to the falling edge of a main phase inductor current judgment signal when the main phase inductor current in the main phase circuit drops to 0 A and the duration reaches the preset off time; and each of the multiple secondary phase PWM signal regulation circuits is configured to output a secondary phase PWM signal that flips from a low level to a high level according to the rising edge of a delay pulse signal when the secondary phase inductor current in the current secondary phase circuit drops to 0 A and the duration does not reach the preset off time; or output a secondary phase PWM signal that flips from a low level to a high level according to the falling edge of a secondary phase inductor current judgment signal when the secondary phase inductor current in the current secondary phase circuit drops to 0 A and the duration reaches the preset off time.

[0005] In some embodiments of the present disclosure, the main phase PWM signal regulation circuit includes: an adaptive off-time control circuit, a main phase inductor current judgment circuit and a main phase PWM signal flipping circuit. Wherein, the first end of the adaptive off-time control circuit is coupled to the main phase PWM signal end, the second end of the adaptive off-time control circuit is coupled to the set frequency input end, and the adaptive off-time control circuit is configured to obtain the rising edge of the time control pulse signal when the upper power tube in the main phase circuit is turned off and the turn-on time of the lower power tube reaches the time value corresponding to the set frequency input by the set frequency input end, and provide the rising edge of the time control pulse signal to the main phase PWM signal flipping circuit via the first node; the first end of the main phase inductor current judgment circuit is coupled to the main phase inductor current judgment signal end, the second end of the main phase inductor current judgment circuit is coupled to the main phase PWM signal end, the third end of the main phase inductor current judgment circuit is coupled to the clamp enable signal end, and the main The phase inductor current judgment circuit is configured to obtain a main phase PWM signal reversal trigger signal when receiving a falling edge of the main phase inductor current judgment signal input by the main phase inductor current judgment signal terminal, and provide the main phase PWM signal reversal trigger signal to the main phase PWM signal reversal circuit via the second node; a first end of the main phase PWM signal reversal circuit is coupled to the signal comparison input terminal, a second end of the main phase PWM signal reversal circuit is coupled to the first node, and a third end of the main phase PWM signal reversal circuit is coupled to the second node; the main phase PWM signal reversal circuit is configured to output the main phase PWM signal that is reversed from a low level to a high level at a main phase PWM signal output terminal according to a rising edge of the time control pulse signal or the main phase PWM signal reversal trigger signal.

[0006] In some embodiments of the present disclosure, the main phase inductor current determination circuit includes a first inverter, a second inverter, a first OR gate, and a first D flip-flop. The first inverter has an input coupled to the first terminal of the main phase inductor current determination circuit, and an output coupled to the clock terminal of the first D flip-flop. The second inverter has an input coupled to the third terminal of the main phase inductor current determination circuit, and an output coupled to the second input of the first OR gate. The first input of the first OR gate is coupled to the second terminal of the main phase inductor current determination circuit, and the output of the first OR gate is coupled to the R input of the first D flip-flop. The D input of the first D flip-flop is coupled to the Q non-output terminal of the first D flip-flop, and the Q output of the first D flip-flop is coupled to the second node.

[0007] In some embodiments of the present disclosure, the main phase PWM signal inversion circuit includes: a first RS flip-flop and a second OR gate. The R input of the first RS flip-flop is coupled to the first terminal of the main phase PWM signal inversion circuit, the S input of the first RS flip-flop is coupled to the output of the second OR gate, and the Q output of the first RS flip-flop is coupled to the main phase PWM signal output terminal. The first input of the second OR gate is coupled to the first node, and the second input of the second OR gate is coupled to the second node.

[0008] In some embodiments of the present disclosure, when the main phase inductor current judgment signal inputted at the main phase inductor current judgment signal terminal has a falling edge, the Q output terminal of the first D trigger outputs a high-level main phase PWM signal flip trigger signal.

[0009] In some embodiments of the present disclosure, when the clamp enable signal input to the clamp enable signal terminal is at a high level and the main phase PWM signal input to the main phase PWM signal terminal is at a high level, the first D flip-flop is cleared.

[0010] In some embodiments of the present disclosure, when the peak sampling signal of the main phase inductor current of the main phase circuit rises and reaches the error amplification output signal, the comparison pulse signal input to the signal comparison input terminal is flipped from a low level to a high level, the R input terminal of the first RS trigger is input to a high level, and the main phase PWM signal output terminal outputs a main phase PWM signal that is flipped from a high level to a low level.

[0011] In some embodiments of the present disclosure, the auxiliary phase PWM signal adjustment circuit includes: an interphase delay control circuit, an auxiliary phase inductor current judgment circuit and an auxiliary phase PWM signal flipping circuit. Wherein, the first end of the interphase delay control circuit is coupled to the auxiliary phase PWM signal end of the current auxiliary phase circuit, the second end of the interphase delay control circuit is coupled to the set frequency input end, and the interphase delay control circuit is configured to obtain the rising edge of the delayed pulse signal when the duration of the rising edge of the auxiliary phase PWM signal of the current auxiliary phase circuit reaches the set time, and provide the rising edge of the delayed pulse signal to the auxiliary phase PWM signal flipping circuit via a third node; the first end of the auxiliary phase inductor current judgment circuit is coupled to the auxiliary phase inductor current judgment signal end, the second end of the auxiliary phase inductor current judgment circuit is coupled to the auxiliary phase PWM signal end of the next auxiliary phase circuit, the third end of the auxiliary phase inductor current judgment circuit is coupled to the clamping enable signal end, and the auxiliary phase inductor current judgment circuit is The auxiliary phase PWM signal flipping circuit is configured to obtain an auxiliary phase PWM signal flipping trigger signal when receiving a falling edge of the auxiliary phase inductor current judgment signal input by the auxiliary phase inductor current judgment signal terminal, and provide the auxiliary phase PWM signal flipping trigger signal to the auxiliary phase PWM signal flipping circuit via a fourth node; the first end of the auxiliary phase PWM signal flipping circuit is coupled to the signal comparison input terminal, the second end of the auxiliary phase PWM signal flipping circuit is coupled to the third node, and the third end of the auxiliary phase PWM signal flipping circuit is coupled to the fourth node. The auxiliary phase PWM signal flipping circuit is configured to output, at the auxiliary phase PWM signal output terminal, an auxiliary phase PWM signal of the next auxiliary phase circuit flipped from a low level to a high level according to the rising edge of the delay pulse signal or the auxiliary phase PWM signal flipping trigger signal.

[0012] In some embodiments of the present disclosure, the auxiliary phase inductor current determination circuit includes: a third inverter, a fourth inverter, a third OR gate, and a second D flip-flop. The third inverter has an input coupled to the first terminal of the auxiliary phase inductor current determination circuit, and an output coupled to the clock terminal of the second D flip-flop; the fourth inverter has an input coupled to the third terminal of the auxiliary phase inductor current determination circuit, and an output coupled to the second input of the third OR gate; the third OR gate has a first input coupled to the second terminal of the auxiliary phase inductor current determination circuit, and an output coupled to the R input of the second D flip-flop; the D input of the second D flip-flop is coupled to the Q non-output terminal of the second D flip-flop, and the Q output of the second D flip-flop is coupled to the fourth node.

[0013] In some embodiments of the present disclosure, the secondary phase PWM signal inversion circuit includes: a second RS flip-flop and a fourth OR gate. The R input of the second RS flip-flop is coupled to the first terminal of the secondary phase PWM signal inversion circuit, the S input of the second RS flip-flop is coupled to the output of the fourth OR gate, and the Q output of the second RS flip-flop is coupled to the secondary phase PWM signal output terminal. The first input of the fourth OR gate is coupled to the third node, and the second input of the fourth OR gate is coupled to the fourth node.

[0014] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation of the embodiments of the present disclosure. In the accompanying drawings:

[0016] Figure 1 is an exemplary circuit diagram of a voltage stabilization circuit 100 for a multi-phase circuit FCCM down-clamping;

[0017] Figure 2 is a timing diagram of an IPEAK signal in the voltage stabilization circuit 100 in the multi-phase circuit FCCM lower clamping state;

[0018] Figure 3 1 is an example diagram of the key signal timing of the voltage stabilizing circuit 100 in the multi-phase circuit FCCM clamping state;

[0019] Figure 4 is a schematic block diagram of a voltage stabilization circuit 400 for a forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure;

[0020] Figure 5 is an exemplary circuit diagram of a voltage stabilizing circuit 400 for a forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure;

[0021] Figure 6 1 is an example diagram of key signal timings of a voltage stabilizing circuit 400 for a forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure.

[0022] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as the control electrode, and the other two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively. The transistors used in the embodiments of the present disclosure are mainly switching transistors. In addition, for the convenience of unified expression, in the context, the base of the bipolar transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Figure 1 FIG. 1 shows an exemplary circuit diagram of a voltage stabilizing circuit 100 clamped in FCCM in a multi-phase circuit. Figure 1 In the example, the PWM (Pulse Width Modulation) signal is the pulse width modulation signal of the current main phase or auxiliary phase circuit, the VSUM signal is the peak sampling signal of the inductor current of the current main phase or auxiliary phase circuit, and i represents the phase order corresponding to the current auxiliary phase PWM signal. If i>1, it corresponds to the phase order of the auxiliary phase circuit. The EAO signal is the error amplifier output signal, and the IPEAK signal is the comparison pulse signal. Figure 2 As shown in FIG, when the VSUM signal rises and reaches the EAO signal, the IPEAK signal flips from a low level to a high level.

[0027] exist Figure 1 In the example, the PWM signals of all phase circuits flip from high to low, determined by the rising edge of the IPEAK signal. When the IPEAK signal, flipping from low to high, is input to the RESET terminal of the RS flip-flop, the output of the RS flip-flop is reset, causing the Q output of the RS flip-flop to output a low level. That is, the main phase PWM signal PWM_1 and the sub-phase PWM signal PWM_i+1 flip from high to low.

[0028] exist Figure 1 In the example, the transition of the main phase PWM signal PWM_1 from a low level to a high level is determined by the arrival of the rising edge of the time control pulse signal OFF. The time control pulse signal OFF is a pulse signal output by the adaptive off-time control circuit OFF-TIMER. When the upper power transistor in the main phase circuit is turned off and the on time of the lower power transistor reaches the time value corresponding to the set frequency input at the set frequency input terminal Freq_Select, the time control pulse signal OFF, which transitions from a low level to a high level, is input to the SET terminal of the RS flip-flop, setting the output of the RS flip-flop to 1, thereby causing the Q output terminal of the RS flip-flop to output a high level. In other words, the main phase PWM signal PWM_1 transitions from a low level to a high level, thus completing the transition process of a complete switching cycle of the main phase PWM signal.

[0029] exist Figure 1 In the example, the transition of the secondary phase PWM signal PWM_i+1 from a low level to a high level is determined by the arrival of the rising edge of the delayed pulse signal DLY_OUT_i. The delayed pulse signal DLY_OUT_i is a pulse signal output by the interphase delay control circuit PHASE_DLY after delaying the rising edge of the secondary phase PWM signal PWM_i. When the secondary phase PWM signal PWM_i transitions from a low level to a high level in each cycle and the duration reaches the set time P_DLY, the delayed pulse signal DLY_OUT_i transitions from a low level to a high level and is input to the SET terminal of the RS flip-flop, setting the output of the RS flip-flop to 1. This causes the output level of the secondary phase PWM signal PWM_i+1 to transition from a low level to a high level, thus completing the transition process for a complete switching cycle of the secondary phase PWM signal.

[0030] exist Figure 1In the PHASE_DLY delay control circuit, the delay selection is related to the switching frequency of the current multi-phase circuit. When the switching frequency is high, the delay is designed to be shortened, and when the switching frequency is low, the delay is designed to be longer. Taking a 6-phase circuit with a switching frequency of 1MHz as an example, its single-phase switching period is designed to be 1us. In order to maintain a uniform energy distribution in the steady state when all phases of the 6-phase circuit are turned on, the delay τ in the PHASE_DLY delay control circuit should satisfy the following formula (1):

[0031]

[0032] exist Figure 1 In the case of a multi-phase circuit, if the current application frequency is relatively low, such as 500KHz or 250KHz, when the circuit enters the 0A peak inductor current clamping state due to the high output voltage VOUT, the DC value of the multi-phase inductor current will be at an extremely high negative value. During the clamping process, the output voltage VOUT will drop severely due to the rapid discharge of the high absolute negative inductor current, and the circuit will quickly exit the clamping state, causing the EAO signal to rebound significantly. In this case, the sharp increase in the instantaneous peak value of the inductor current will lead to a sharp accumulation of energy, causing the output voltage VOUT to rebound significantly and then causing the EAO signal to drop again. This cycle will cause the circuit to experience large signal oscillations, such as Figure 3 shown.

[0033] The disclosed embodiments provide a voltage-stabilizing circuit for forced continuous current mode in a multiphase circuit. Because the multiphase circuits all operate in a control mode with a fixed, preset off-time, the absolute value of the DC current in the multiphase inductor is lower than in the original control mode. This allows the low-frequency multiphase circuit to discharge slowly when entering 0A peak current clamping in FCCM. After exiting the clamping, the EAO signal slowly recovers, and the output voltage is regulated to a stable state by the loop. This avoids the large-signal oscillation problem caused by the high absolute value of negative current during clamping in traditional multiphase circuits. Figure 4 FIG. 4 is a schematic block diagram of a voltage stabilizing circuit 400 for a forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure. Figure 4 As shown, the voltage regulation circuit 400 for forced continuous current mode in a multi-phase circuit may include: a main phase PWM signal regulation circuit 410 and a plurality of auxiliary phase PWM signal regulation circuits 420_i.

[0034] The main phase PWM signal conditioning circuit 410 can be coupled to a main phase PWM signal terminal PWM_1, a set frequency input terminal Freq_Select, a main phase inductor current determination signal terminal ZCD_INT_1, a clamp enable signal terminal EAO_CLAMP, a signal comparison input terminal IPEAK, and a main phase PWM signal output terminal OUT_PWM_1. The main phase PWM signal conditioning circuit 410 can be configured to output the main phase PWM signal PWM_1, which switches from a low level to a high level, based on the rising edge of the time control pulse signal OFF, when the main phase inductor current in the main phase circuit drops to 0 A and the duration does not reach the preset off-time T1. Alternatively, the main phase PWM signal PWM_1 can be output, which switches from a low level to a high level, based on the falling edge of the main phase inductor current determination signal ZCD_INT_1, when the main phase inductor current in the main phase circuit drops to 0 A and the duration reaches the preset off-time T1.

[0035] Each of the plurality of auxiliary phase PWM signal conditioning circuits 420_i can be coupled to the auxiliary phase PWM signal terminal PWM_i of the current auxiliary phase circuit, the next auxiliary phase PWM signal terminal PWM_i+1, the set frequency input terminal Freq_Select, the auxiliary phase inductor current determination signal terminal ZCD_INT_i, the clamp enable signal terminal EAO_CLAMP, the signal comparison input terminal IPEAK, and the auxiliary phase PWM signal output terminal OUT_PWM_i+1. Each of the multiple auxiliary phase PWM signal regulation circuits is configured to output an auxiliary phase PWM signal PWM_i+1 that flips from a low level to a high level according to a rising edge of a delay pulse signal DLY_OUT_i when the auxiliary phase inductor current in the current auxiliary phase circuit drops to 0 A and the duration does not reach the preset off-time T1; or to output an auxiliary phase PWM signal PWM_i+1 that flips from a low level to a high level according to a falling edge of an auxiliary phase inductor current judgment signal ZCD_INT_i when the auxiliary phase inductor current in the current auxiliary phase circuit drops to 0 A and the duration reaches the preset off-time T1.

[0036] According to the embodiment of the present disclosure, the voltage stabilizing circuit for the forced continuous current mode in the multi-phase circuit makes the absolute value of the DC quantity of the multi-phase inductor current lower than that in the original control mode through a fixed preset off time, so that the low-frequency multi-phase circuit slowly discharges when entering the 0A peak current clamp under FCCM, and the EAO signal slowly recovers after exiting the clamp, and the output voltage is regulated by the loop to be stable, avoiding the large signal oscillation problem caused by the high absolute value negative current during clamping in the traditional multi-phase circuit.

[0037] Figure 5FIG. 4 shows an exemplary circuit diagram of a voltage stabilizing circuit 400 for a forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure. Figure 5 As shown, the main phase PWM signal adjustment circuit 410 may include: an adaptive off-time control circuit 411, a main phase inductor current determination circuit 412, and a main phase PWM signal inversion circuit 413. A first terminal of the adaptive off-time control circuit 411 is coupled to the main phase PWM signal terminal PWM_1, and a second terminal of the adaptive off-time control circuit 411 is coupled to the set frequency input terminal Freq_Select. The adaptive off-time control circuit 411 is configured to obtain a rising edge of the time control pulse signal OFF when the upper power transistor in the main phase circuit is turned off and the on time of the lower power transistor reaches the time value corresponding to the set frequency input at the set frequency input terminal Freq_Select, and provide the rising edge of the time control pulse signal OFF to the main phase PWM signal inversion circuit 413 via the first node N1. A first end of the main phase inductor current judgment circuit 412 is coupled to the main phase inductor current judgment signal terminal ZCD_INT_1, a second end of the main phase inductor current judgment circuit 412 is coupled to the main phase PWM signal terminal PWM_1, and a third end of the main phase inductor current judgment circuit 412 is coupled to the clamping enable signal terminal EAO_CLAMP. The main phase inductor current judgment circuit 412 is configured to obtain a main phase PWM signal flip trigger signal MPTTS when receiving a falling edge of the main phase inductor current judgment signal input by the main phase inductor current judgment signal terminal ZCD_INT_1, and provide the main phase PWM signal flip trigger signal MPTTS to the main phase PWM signal flip trigger circuit 413 via the second node N2. A first end of the main phase PWM signal flipping circuit 413 is coupled to the signal comparison input end IPEAK, a second end of the main phase PWM signal flipping circuit 413 is coupled to the first node N1, and a third end of the main phase PWM signal flipping circuit 413 is coupled to the second node N2. The main phase PWM signal flipping circuit 413 is configured to output the main phase PWM signal flipped from a low level to a high level at the main phase PWM signal output end OUT_PWM_1 according to the rising edge of the time control pulse signal OFF or the main phase PWM signal flipping trigger signal MPTTS.

[0038] The main phase inductor current determination circuit 412 may include a first inverter D1, a second inverter D2, a first OR gate G1, and a first D flip-flop D_1. The input of the first inverter D1 is coupled to the first terminal of the main phase inductor current determination circuit 412, and the output of the first inverter D1 is coupled to the clock terminal Clk of the first D flip-flop D_1. The input of the second inverter D2 is coupled to the third terminal of the main phase inductor current determination circuit 412, and the output of the second inverter D2 is coupled to the second input of the first OR gate G1. The first input of the first OR gate G1 is coupled to the second terminal of the main phase inductor current determination circuit 412, and the output of the first OR gate G1 is coupled to the R input terminal Reset of the first D flip-flop D_1. The D input of the first D flip-flop D_1 is coupled to the Q non-output terminal of the first D flip-flop D_1, and the Q output terminal of the first D flip-flop D_1 is coupled to the second node N2.

[0039] The main phase PWM signal inversion circuit 413 may include a first RS flip-flop RS_1 and a second OR gate G2. The R input of the first RS flip-flop RS_1 is coupled to the first terminal of the main phase PWM signal inversion circuit 413, the S input of the first RS flip-flop RS_1 is coupled to the output of the second OR gate G2, and the Q output of the first RS flip-flop RS_1 is coupled to the main phase PWM signal output terminal OUT_PWM_1. The first input of the second OR gate G2 is coupled to the first node N1, and the second input of the second OR gate G2 is coupled to the second node N2.

[0040] The falling edge of the main phase inductor current judgment signal ZCD_INT_1 input to the main phase inductor current judgment signal terminal indicates that the main phase inductor current has dropped below 0 A and has lasted for a predetermined shutdown time T1. When the main phase inductor current drops to 0 A, the main phase inductor current judgment signal ZCD_INT_1 flips to a high level. When the main phase inductor current drops to 0 A and lasts for a predetermined shutdown time T1, the main phase inductor current judgment signal ZCD_INT_1 flips to a low level. Alternatively, when the main phase inductor current drops to 0 A and lasts for less than the predetermined shutdown time T1, the main phase inductor current judgment signal ZCD_INT_1 also flips from a high level to a low level.

[0041] In the embodiments of the present disclosure, Figure 1 The multi-phase circuit FCCM clamped voltage stabilizing circuit 100 is similar in that the PWM signals of all phase circuits are flipped from high level to low level, which is determined by the arrival of the rising edge of the IPEAK signal. Therefore, in the embodiment of the present disclosure, this part is not repeated.

[0042] The following combination Figure 5 The working process of the main phase PWM signal adjustment circuit 410 of the voltage stabilization circuit 400 for the forced continuous current mode in the multi-phase circuit according to the embodiment of the present disclosure is explained by way of example.

[0043] exist Figure 5 In this example, if the main phase inductor current drops to 0A and its duration does not exceed the preset off-time T1, the time control pulse signal OFF flips from a low level to a high level and is input to the second OR gate G2 via the first node N1. This causes the S input of the first RS flip-flop RS_1 to be high, causing the Q output of the first RS flip-flop RS_1 to be high. This means that the main phase PWM signal PWM_1 outputted from the main phase PWM signal output terminal OUT_PWM_1 flips from a low level to a high level. This high-level main phase PWM signal PWM_1 is provided to the first input of the first OR gate G1. Because the main phase inductor current drops to 0A, the clamp enable signal EAO_CLAMP input is high. Therefore, the R input Reset of the first D flip-flop D_1 is 0, clearing the first D flip-flop D_1. If the main phase inductor current determination signal ZCD_INT_1 also flips from a high level to a low level at this time, it will not affect the output of the main phase PWM signal PWM_1.

[0044] exist Figure 5 In this example, if the main phase inductor current drops to 0A and lasts for the preset off-time T1, the main phase inductor current determination signal terminal ZCD_INT_1 flips from a high level to a low level. The clock terminal Clk input of the first D-type flip-flop D_1 also flips high, and the Q output of the first D-type flip-flop D_1 also flips high. This means that the main phase PWM signal flip trigger signal MPTTS is high, causing the main phase PWM signal PWM_1 to flip from a low level to a high level. Similarly, the first D-type flip-flop D_1 is cleared. At this point, the time control pulse signal OFF, which has not yet flipped from a low level to a high level, has no effect on the output main phase PWM signal PWM_1.

[0045] In addition, if Figure 5As shown, the secondary phase PWM signal conditioning circuit 420_i may include: an interphase delay control circuit 421_i, a secondary phase inductor current determination circuit 422_i, and a secondary phase PWM signal inversion circuit 423_i. A first terminal of the interphase delay control circuit 421_i is coupled to the secondary phase PWM signal terminal PWM_i of the current secondary phase circuit, and a second terminal of the interphase delay control circuit is coupled to the set frequency input terminal Freq_Select. The interphase delay control circuit 421_i is configured to, when the duration of the rising edge of the secondary phase PWM signal PWM_i of the current secondary phase circuit reaches a set time T1, generate a rising edge of the delayed pulse signal DLY_OUT_i and provide the rising edge of the delayed pulse signal DLY_OUT_i to the secondary phase PWM signal inversion circuit 423_i via a third node N3. A first terminal of the auxiliary inductor current determination circuit 422_i is coupled to the auxiliary inductor current determination signal terminal ZCD_INT_i. A second terminal of the auxiliary inductor current determination circuit 422_i is coupled to the auxiliary PWM signal terminal PWM_i of the current auxiliary phase circuit. A third terminal of the auxiliary inductor current determination circuit 422_i is coupled to the clamp enable signal terminal EAO_CLAMP. Upon receiving a falling edge of the auxiliary inductor current determination signal inputted via the auxiliary inductor current determination signal terminal ZCD_INT_i, the auxiliary inductor current determination circuit 422_i is configured to generate a auxiliary PWM signal inversion trigger signal SPTTS and provide the auxiliary PWM signal inversion trigger signal SPTTS to the auxiliary PWM signal inversion circuit 423_i via a fourth node N4. A first terminal of the secondary phase PWM signal inversion circuit 423_i is coupled to the signal comparison input terminal IPEAK, a second terminal of the secondary phase PWM signal inversion circuit 423_i is coupled to the third node N3, and a third terminal of the secondary phase PWM signal inversion circuit 423_i is coupled to the fourth node N4. The secondary phase PWM signal inversion circuit 423_i is configured to output, at a secondary phase PWM signal output terminal OUT_PWM_i+1, a secondary phase PWM signal PWM_i+1 of the next secondary phase circuit, which is flipped from a low level to a high level in response to a rising edge of the delay pulse signal DLY_OUT_i or the secondary phase PWM signal inversion trigger signal SPTTS.

[0046] The auxiliary inductor current determination circuit 422_i may include a third inverter D3, a fourth inverter D4, a third OR gate G3, and a second D flip-flop D_i. The input of the third inverter D3 is coupled to the first terminal of the auxiliary inductor current determination circuit 422_i, and the output of the third inverter D3 is coupled to the clock terminal Clk of the second D flip-flop D_i. The input of the fourth inverter D4 is coupled to the third terminal of the auxiliary inductor current determination circuit 422_i, and the output of the fourth inverter D4 is coupled to the second input of the third OR gate G3. The first input of the third OR gate G3 is coupled to the second terminal of the auxiliary inductor current determination circuit 422_i, and the output of the third OR gate G3 is coupled to the R input of the second D flip-flop D_i. The D input of the second D flip-flop D_i is coupled to the Q non-output terminal of the second D flip-flop D_i, and the Q output of the second D flip-flop D_i is coupled to the fourth node N4.

[0047] The secondary phase PWM signal inversion circuit 423_i may include a second RS flip-flop RS_i and a fourth OR gate G4. The R input of the second RS flip-flop RS_i is coupled to the first terminal of the secondary phase PWM signal inversion circuit 423_i, the S input of the second RS flip-flop RS_i is coupled to the output of the fourth OR gate G4, and the Q output of the second RS flip-flop RS_i is coupled to the secondary phase PWM signal output terminal OUT_PWM_i+1. The first input of the fourth OR gate G4 is coupled to the third node N3, and the second input of the fourth OR gate G4 is coupled to the fourth node N4.

[0048] The following combination Figure 5 The working process of the auxiliary phase PWM signal adjustment circuit 420_i of the voltage stabilization circuit 400 for forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure is explained with an example.

[0049] exist Figure 5In the example, if the secondary phase inductor current of the current secondary phase circuit drops to 0A and its duration does not reach the preset off-time T1, the delayed pulse signal DLY_OUT_i, which flips from a low level to a high level, is input to the fourth OR gate G4 via the third node N3. As a result, the S input terminal of the second RS flip-flop RS_i is input at a high level, causing the Q output terminal of the second RS flip-flop RS_i to output a high level. In other words, the secondary phase PWM signal output terminal OUT_PWM_i+1 outputs the secondary phase PWM signal PWM_i+1 of the next secondary phase circuit, which flips from a low level to a high level. Simultaneously, the high-level secondary phase PWM signal PWM_i+1 of the next secondary phase circuit is provided to the first input terminal of the third OR gate G3 via the next secondary phase PWM signal terminal PWM_i+1. Since the main phase inductor current drops to 0A, the clamp enable signal EAO_CLAMP input is input at a high level. Therefore, the R input terminal Reset of the second D flip-flop D_i is input to 0, clearing the second D flip-flop D_i. If the input of the secondary phase inductor current determination signal terminal ZCD_INT_i is also flipped from a high level to a low level at this time, it will not affect the output secondary phase PWM signal PWM_i+1.

[0050] exist Figure 5 In this example, if the secondary phase inductor current of the current secondary phase circuit drops to 0A and lasts for a predetermined off-time period (T1), the secondary phase inductor current determination signal terminal ZCD_INT_i flips from a high level to a low level. The clock terminal Clk input of the second D-type flip-flop D_i also flips high, and the Q output of the second D-type flip-flop D_i also flips high. This means that the secondary phase PWM signal flipping trigger signal SPTTS is high, causing the secondary phase PWM signal output terminal OUT_PWM_i+1 to output the secondary phase PWM signal PWM_i+1 of the next secondary phase circuit, flipping from a low level to a high level. Similarly, the second D-type flip-flop D_i is cleared. At this point, the delayed pulse signal DLY_OUT_i, which has not yet flipped from a low level to a high level, has no effect on the output secondary phase PWM signal PWM_i+1.

[0051] Figure 6 The figure shows the key signal timing when clamping occurs in FCCM in a voltage stabilizing circuit 400 for a forced continuous current mode in a multi-phase circuit according to an embodiment of the present disclosure in a low frequency and high duty cycle application. Figure 6 , the multi-phase circuit working at low frequency, slowly discharges when entering the 0A peak current clamp under FCCM, and the EAO signal slowly recovers after exiting the clamp. The output voltage VOUT is regulated to be stable by the loop, avoiding the large signal oscillation caused by the high absolute value negative current during clamping as mentioned above.

[0052] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus and method according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0053] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0054] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0055] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit, characterized in that: include: Main phase PWM signal regulation circuit and multiple sub-phase PWM signal regulation circuits, The main phase PWM signal adjustment circuit is configured to output a main phase PWM signal that flips from a low level to a high level according to the rising edge of the time control pulse signal when the main phase inductor current in the main phase circuit drops to 0A and the duration does not reach the preset off time; or output a main phase PWM signal that flips from a low level to a high level according to the falling edge of the main phase inductor current judgment signal when the main phase inductor current in the main phase circuit drops to 0A and the duration reaches the preset off time; and Each of the plurality of auxiliary phase PWM signal regulation circuits is configured to output an auxiliary phase PWM signal that flips from a low level to a high level according to a rising edge of a delay pulse signal when the auxiliary phase inductor current in the current auxiliary phase circuit drops to 0 A and the duration does not reach the preset off time; or output an auxiliary phase PWM signal that flips from a low level to a high level according to a falling edge of an auxiliary phase inductor current judgment signal when the auxiliary phase inductor current in the current auxiliary phase circuit drops to 0 A and the duration reaches the preset off time, The main phase PWM signal adjustment circuit includes: an adaptive off-time control circuit, a main phase inductor current determination circuit, and a main phase PWM signal inversion circuit. The first terminal of the adaptive off-time control circuit is coupled to the main phase PWM signal terminal, and the second terminal of the adaptive off-time control circuit is coupled to the set frequency input terminal. The adaptive off-time control circuit is configured to obtain a rising edge of the time control pulse signal when the upper power tube in the main phase circuit is turned off and the on time of the lower power tube reaches the time value corresponding to the set frequency input by the set frequency input terminal, and provide the rising edge of the time control pulse signal to the main phase PWM signal inversion circuit via the first node. The auxiliary phase PWM signal adjustment circuit includes: an interphase delay control circuit, an auxiliary phase inductor current judgment circuit and an auxiliary phase PWM signal inversion circuit, wherein a first end of the interphase delay control circuit is coupled to the auxiliary phase PWM signal end of the current auxiliary phase circuit, and a second end of the interphase delay control circuit is coupled to the set frequency input end. The interphase delay control circuit is configured to obtain the rising edge of the delayed pulse signal when the duration of the rising edge of the auxiliary phase PWM signal of the current auxiliary phase circuit reaches a set time, and provide the rising edge of the delayed pulse signal to the auxiliary phase PWM signal inversion circuit via a third node.

2. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 1, characterized in that: A first terminal of the main phase inductor current judgment circuit is coupled to a main phase inductor current judgment signal terminal, a second terminal of the main phase inductor current judgment circuit is coupled to the main phase PWM signal terminal, and a third terminal of the main phase inductor current judgment circuit is coupled to a clamp enable signal terminal. The main phase inductor current judgment circuit is configured to, upon receiving a falling edge of the main phase inductor current judgment signal inputted by the main phase inductor current judgment signal terminal, obtain a main phase PWM signal inversion trigger signal, and provide the main phase PWM signal inversion trigger signal to the main phase PWM signal inversion circuit via a second node. A first end of the main phase PWM signal inversion circuit is coupled to a signal comparison input end, a second end of the main phase PWM signal inversion circuit is coupled to the first node, and a third end of the main phase PWM signal inversion circuit is coupled to the second node. The main phase PWM signal inversion circuit is configured such that, according to a rising edge of the time control pulse signal or the main phase PWM signal inversion trigger signal, a main phase PWM signal output end outputs the main phase PWM signal that is inverted from a low level to a high level.

3. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 2, characterized in that: The main phase inductor current judgment circuit includes a first inverter, a second inverter, a first OR gate and a first D flip-flop. The input terminal of the first inverter is coupled to the first terminal of the main phase inductor current determination circuit, and the output terminal of the first inverter is coupled to the clock terminal of the first D flip-flop; The input terminal of the second inverter is coupled to the third terminal of the main phase inductor current determination circuit, and the output terminal of the second inverter is coupled to the second input terminal of the first OR gate; The first input terminal of the first OR gate is coupled to the second terminal of the main phase inductor current determination circuit, and the output terminal of the first OR gate is coupled to the R input terminal of the first D flip-flop; A D input terminal of the first D flip-flop is coupled to a Q non-output terminal of the first D flip-flop, and a Q output terminal of the first D flip-flop is coupled to the second node.

4. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 2, characterized in that: The main phase PWM signal inversion circuit includes: a first RS trigger and a second OR gate, The R input terminal of the first RS trigger is coupled to the first terminal of the main phase PWM signal inversion circuit, the S input terminal of the first RS trigger is coupled to the output terminal of the second OR gate, and the Q output terminal of the first RS trigger is coupled to the main phase PWM signal output terminal; A first input terminal of the second OR gate is coupled to the first node, and a second input terminal of the second OR gate is coupled to the second node.

5. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 3, characterized in that: When the main phase inductor current judgment signal inputted by the main phase inductor current judgment signal terminal reaches a falling edge, the Q output terminal of the first D flip-flop outputs the main phase PWM signal inversion trigger signal of a high level.

6. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 3, characterized in that: When the clamp enable signal inputted by the clamp enable signal terminal is at a high level and the main phase PWM signal inputted by the main phase PWM signal terminal is at a high level, the first D flip-flop is cleared.

7. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 4, characterized in that: When the peak sampling signal of the main phase inductor current of the main phase circuit rises and reaches the error amplification output signal, the comparison pulse signal input to the signal comparison input terminal flips from a low level to a high level, the R input terminal of the first RS trigger is input at a high level, and the main phase PWM signal output terminal outputs a main phase PWM signal flipped from a high level to a low level.

8. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 1, characterized in that: A first terminal of the auxiliary phase inductor current judgment circuit is coupled to a auxiliary phase inductor current judgment signal terminal, a second terminal of the auxiliary phase inductor current judgment circuit is coupled to a auxiliary phase PWM signal terminal of a next auxiliary phase circuit, and a third terminal of the auxiliary phase inductor current judgment circuit is coupled to a clamping enable signal terminal. The auxiliary phase inductor current judgment circuit is configured to, upon receiving a falling edge of the auxiliary phase inductor current judgment signal inputted by the auxiliary phase inductor current judgment signal terminal, obtain a auxiliary phase PWM signal inversion trigger signal, and provide the auxiliary phase PWM signal inversion trigger signal to the auxiliary phase PWM signal inversion circuit via a fourth node. A first terminal of the secondary phase PWM signal inversion circuit is coupled to a signal comparison input terminal, a second terminal of the secondary phase PWM signal inversion circuit is coupled to the third node, and a third terminal of the secondary phase PWM signal inversion circuit is coupled to the fourth node. The secondary phase PWM signal inversion circuit is configured to output a secondary phase PWM signal of the next secondary phase circuit inverted from a low level to a high level at a secondary phase signal output terminal according to a rising edge of the delayed pulse signal or the secondary phase PWM signal inversion trigger signal.

9. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 8, characterized in that: The auxiliary phase inductor current judgment circuit includes: a third inverter, a fourth inverter, a third OR gate and a second D flip-flop. The input terminal of the third inverter is coupled to the first terminal of the auxiliary phase inductor current determination circuit, and the output terminal of the third inverter is coupled to the clock terminal of the second D flip-flop; An input terminal of the fourth inverter is coupled to the third terminal of the auxiliary phase inductor current determination circuit, and an output terminal of the fourth inverter is coupled to the second input terminal of the third OR gate; The first input terminal of the third OR gate is coupled to the second terminal of the auxiliary phase inductor current determination circuit, and the output terminal of the third OR gate is coupled to the R input terminal of the second D flip-flop; A D input terminal of the second D flip-flop is coupled to a Q non-output terminal of the second D flip-flop, and a Q output terminal of the second D flip-flop is coupled to the fourth node.

10. The voltage stabilizing circuit for a forced continuous current mode in a multi-phase circuit according to claim 8, characterized in that: The auxiliary phase PWM signal inversion circuit includes: a second RS trigger and a fourth OR gate, The R input terminal of the second RS flip-flop is coupled to the first terminal of the secondary phase PWM signal inversion circuit, the S input terminal of the second RS flip-flop is coupled to the output terminal of the fourth OR gate, and the Q output terminal of the second RS flip-flop is coupled to the secondary phase PWM signal output terminal; A first input terminal of the fourth OR gate is coupled to the third node, and a second input terminal of the fourth OR gate is coupled to the fourth node.

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