A voltage adjustment circuit, an integrated circuit, and a voltage regulator

Abstract

The application discloses a voltage adjusting circuit, an integrated circuit and a voltage stabilizer, wherein the voltage adjusting circuit comprises an LDO-like structure, an SSF output structure and a first PMOS connected with the LDO-like structure and the SSF output structure; the LDO-like structure comprises an error amplifier and a feedback loop formed by a first NMOS and a first voltage dividing resistor string; the drain of the first PMOS is connected with the drain of the first NMOS; the gate of the first PMOS is connected with the SSF output structure, the SSF output structure is provided with a bias voltage, and the SSF output structure is connected with the output end of the error amplifier in the LDO-like structure; and the output end of the SSF output structure is connected with a load. A common bias voltage providing part is used to provide a bias voltage for each SSF output structure, and each load has a complete feedback loop to ensure the stability of the output voltage without adding an error amplifier.

Description

Technical Field

[0001] This invention relates to circuits, and more specifically to a voltage regulation circuit that maintains a stable load voltage. Background Technology

[0002] A voltage regulation circuit is as follows Figure 1 The LDO structure shown operates on the principle of Vout = Vref(1 + R2 / R1). When load changes cause Vout to fluctuate, a voltage divider signal is fed back to the input of the error amplifier through resistors R1 and R2. This causes the output of the error amplifier to adjust the gate of the PMOS transistor P1, thereby regulating Vout and completing the negative feedback regulation process to ensure that Vout remains constant when the load changes. However, this structure is not suitable for driving multiple loads because as the load increases, multiple error amplifiers are needed to complete the negative feedback, increasing the area and power consumption. Summary of the Invention

[0003] To address the voltage regulation problem caused by increased load, this application provides a voltage regulation circuit.

[0004] A voltage regulation circuit includes an LDO-like structure, an SSF output structure, and a first PMOS transistor connecting the LDO-like structure and the SSF output structure. The LDO-like structure includes an error amplifier and a feedback loop composed of a first NMOS transistor and a first voltage divider resistor string. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first PMOS transistor is connected to the SSF output structure to provide a bias voltage for the SSF output structure. The SSF output structure is connected to the output terminal of the error amplifier in the LDO-like structure. The output terminal of the SSF output structure is connected to a load.

[0005] Furthermore, the LDO-like structure includes an error amplifier, a first NMOS transistor, and a first voltage divider resistor string; the output terminal of the error amplifier is connected to the gate of the first NMOS transistor, the inverting input terminal of the error amplifier is connected to the first voltage divider resistor string, and the first voltage divider resistor string and the first NMOS transistor constitute the feedback loop of the error amplifier.

[0006] Furthermore, the SSF output structure includes a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, and a second voltage divider resistor string; the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second NMOS transistor is connected to the output terminal of the error amplifier in the LDO-like structure, and the gate of the third PMOS transistor is connected to the drain of the second NMOS transistor; one end of the second voltage divider resistor string is connected to the source of the second NMOS transistor, and the other end is grounded; the drain output of the third PMOS transistor and the source output of the second NMOS transistor form the output terminal of the SSF output structure.

[0007] Furthermore, there are several SSF output structures, each of which is connected to the first PMOS transistor and the LDO-like structure, and the output terminal of each SSF output structure is connected to a load.

[0008] Furthermore, the first voltage divider resistor series consists of two resistors.

[0009] Furthermore, the second voltage divider resistor string has the same resistance value as the first voltage divider resistor string.

[0010] An integrated circuit comprising any one of the voltage regulation circuits described above.

[0011] A voltage regulator comprising any of the voltage adjustment circuits described above.

[0012] The beneficial effects of this invention are as follows:

[0013] This invention provides a common bias voltage supply section on the circuit to provide a bias voltage for each SSF output structure. Without adding an error amplifier, each load has a complete feedback loop to ensure the stability of the output voltage. When the load increases, only the SSF input structure needs to be added to provide stable power supply for multiple loads. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 It is a voltage regulation circuit in the prior art;

[0016] Figure 2 It is the improved voltage regulation circuit in Example 1;

[0017] Figure 3 It is the improved voltage regulation circuit in Example 2. Detailed Implementation

[0018] To make the purpose, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0020] In the description of this application, it should be understood that the demonstrative pronouns such as "first", "second", and "third" are used only for the convenience of describing this application, and do not indicate or imply that the elements referred to must have a specific order, and therefore should not be construed as a limitation on this application.

[0021] Example 1

[0022] This embodiment provides a voltage adjustment circuit, such as Figure 2 As shown, it specifically includes an LDO-like structure, an SSF output structure, and a first PMOS transistor P1 connecting the LDO-like structure and the SSF output structure.

[0023] The LDO-like structure includes a differential amplifier, a first NMOS transistor N1, and a first voltage divider resistor string, which is composed of R1 and R2; R1 is grounded and R2 is connected to the source of N1.

[0024] The output terminal of the error amplifier is connected to the gate of the first NMOS transistor N1, and the inverting input terminal of the error amplifier is connected to the first voltage divider resistor string. The first voltage divider resistor string R1, R2 and the first NMOS transistor N1 constitute the feedback loop of the error amplifier; the non-inverting input terminal of the error amplifier is connected to the reference input voltage vref.

[0025] The SSF (super source follower) output structure includes a second PMOS transistor P2, a second NMOS transistor N2, a third PMOS transistor P3, and a second voltage divider resistor string composed of resistors R3 and R4. The gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1, and the gate of the second NMOS transistor N2 is connected to the output terminal of the error amplifier in the LDO-like structure. The gate of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2. One end of resistor R4 in the second voltage divider resistor string is connected to the source of the second NMOS transistor N2, and one end of resistor R3 is grounded. The drain output of the third PMOS transistor P3 and the source output of the second NMOS transistor N2 form the output terminal vout1 of the entire SSF output structure.

[0026] The resistance of the first voltage divider resistor string is equal to the resistance of the second voltage divider resistor string, R2 = R4, and R1 = R3. Figure 2 As can be seen, the branch consisting of P2, N2, R4, and R3 is a copy of the branch consisting of P1, N2, R2, and R1; the configuration of P2, N2, and P3 forms the SSF voltage power supply input by the NMOS transistor.

[0027] The working principle of this example solution is as follows:

[0028] The reference input voltage vref is amplified by an error amplifier and fed back through a feedback loop formed by N1 and resistors R1 and R2, resulting in an output voltage vout = vref(1 + R2 / R1) at the source of N1. The first PMOS transistor P1 mirrors the current of the second PMOS transistor P2, meaning P1 provides a bias voltage to P2. Simultaneously, the gate voltage of N2 is controlled by the output of the error amplifier. When the load changes, the feedback from the third PMOS transistor P3 stabilizes vout1, making it equal to vref(1 + R2 / R1).

[0029] When the load changes, a large current is required, and the voltage at the vout1 terminal suddenly drops. The drain voltage of N2 also drops accordingly. As a result, the gate voltage of P3 also drops, causing its VSG to increase. P3 will then increase the current flowing to the vout1 terminal, causing the voltage value at the vout1 terminal to rise. This forms a complete feedback loop for the load change, maintaining a stable voltage output at the vout1 terminal.

[0030] For individual loads, an SSF with an NMOS transistor input is used for power supply. This structure uses an LDO-like structure to form a common section, providing a bias voltage for each SSF output structure. When the load is increased, only the SSF input structure needs to be added to provide stable power supply for multiple loads.

[0031] Example 2

[0032] This embodiment provides a voltage regulation circuit, which includes multiple SSF output structures, enabling multiple loads to be connected simultaneously, such as... Figure 3 As shown, it specifically includes an LDO-like structure, two SSF output structures, and a first PMOS transistor P1 connecting the LDO-like structure and the SSF output structures.

[0033] Each SSF output structure is connected to the first PMOS transistor P1 and an LDO-like structure, and the output terminal of each SSF output structure is connected to a load.

[0034] The LDO-like structure includes a differential amplifier, a first NMOS transistor N1, and a first voltage divider resistor string, which is composed of R1 and R2; R1 is grounded and R2 is connected to the source of N1.

[0035] The output terminal of the error amplifier is connected to the gate of the first NMOS transistor N1, and the inverting input terminal of the error amplifier is connected to the first voltage divider resistor string. The first voltage divider resistor string R1, R2 and the first NMOS transistor N1 constitute the feedback loop of the error amplifier; the non-inverting input terminal of the error amplifier is connected to the reference input voltage vref.

[0036] The LDO-like structure and the first PMOS transistor form the common part of the voltage regulation circuit, providing a bias voltage for each additional SSF output structure.

[0037] The SSF (super source follower) output structure includes a second PMOS transistor P2, a second NMOS transistor N2, a third PMOS transistor P3, and a second voltage divider resistor string composed of resistors R3 and R4. The gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1, and the gate of the second NMOS transistor N2 is connected to the output terminal of the error amplifier in the LDO-like structure. The gate of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2. One end of resistor R4 in the second voltage divider resistor string is connected to the source of the second NMOS transistor N2, and one end of resistor R3 is grounded. The drain output of the third PMOS transistor P3 and the source output of the second NMOS transistor N2 form the output terminal vout1 of the entire SSF output structure.

[0038] P4, N3, P5, R6, and R5 constitute another SSF output structure. The gate voltage of transistor N3 is still provided by the output of the error amplifier. The gate of transistor P4 is connected to the gate of transistor P1, and the bias voltage is provided to transistor P4 by transistor P1. Load 2 is connected to the common output terminal of the source of N3 and the drain of P5, which is the output terminal vout2 of the other SSF output structure.

[0039] Each additional load adds an SSF output structure, which provides complete feedback to the load voltage, keeping the load voltage stable.

[0040] The resistance values ​​of the first, second, and third voltage divider resistor strings are all the same, R2 = R4 = R6, and R1 = R3 = R5. The branch composed of P4, N3, R6, and R5 is also a copy of the branch composed of P1, N2, R2, and R1; the configuration of P4, N3, and P5 also forms a power supply for the SSF voltage input by the NMOS transistor.

[0041] When load 2 changes abruptly, requiring an increase in current, the voltage at vout2 drops, and the drain voltage at N3d also drops. Consequently, the gate voltage at P5 decreases, leading to an increase in its VSG, which in turn increases the current flowing from P5 to the output terminal of vout2. This raises the voltage at the vout2 terminal, stabilizing the load voltage and ending the circuit feedback.

[0042] In this embodiment, an SSF output structure is added compared to Embodiment 1, which can increase the load of the connected circuit without adding an amplifier and can maintain a stable load voltage.

[0043] Example 3

[0044] This embodiment provides an integrated circuit, including the voltage regulation circuit in embodiment 1 or 2.

[0045] Example 4

[0046] This embodiment provides a voltage regulator, including the voltage adjustment circuit in embodiment 1 or 2.

[0047] In the several embodiments provided in this application, it should be understood that the disclosed structure can be implemented in other ways. The structural embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0048] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A voltage regulation circuit, characterized in that, The system includes an LDO-like structure, an SSF output structure, and a first PMOS transistor connecting the LDO-like structure and the SSF output structure. The LDO-like structure includes an error amplifier and a feedback loop composed of a first NMOS transistor and a first voltage divider resistor string. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first PMOS transistor is connected to the SSF output structure, providing a bias voltage for the SSF output structure. The SSF output structure is connected to the output terminal of the error amplifier in the LDO-like structure. The output terminal of the SSF output structure is connected to a load. The SSF output structure includes a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, and a second voltage divider resistor string. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second NMOS transistor is connected to the output terminal of the error amplifier in the LDO-like structure, and the gate of the third PMOS transistor is connected to the drain of the second NMOS transistor. One end of the second voltage divider resistor string is connected to the source of the second NMOS transistor, and the other end is grounded. The drain output of the third PMOS transistor and the source output of the second NMOS transistor form the output terminal of the SSF output structure.

2. The voltage regulation circuit according to claim 1, characterized in that, The LDO-like structure includes an error amplifier, a first NMOS transistor, and a first voltage divider resistor string; the output terminal of the error amplifier is connected to the gate of the first NMOS transistor, and the inverting input terminal of the error amplifier is connected to the first voltage divider resistor string. The first voltage divider resistor string and the first NMOS transistor constitute the feedback loop of the error amplifier.

3. The voltage adjustment circuit according to claim 1, characterized in that, There are several SSF output structures, each of which is connected to the first PMOS transistor and the LDO-like structure, and the output terminal of each SSF output structure is connected to a load.

4. The voltage regulation circuit according to claim 1, characterized in that, The first voltage divider resistor string consists of two resistors.

5. The voltage regulation circuit according to claim 1, characterized in that, The second voltage divider resistor string has the same resistance value as the first voltage divider resistor string.

6. An integrated circuit, characterized in that, Includes the voltage regulation circuit as described in any one of claims 1-5.

7. A voltage regulator, characterized in that, Includes the voltage regulation circuit as described in any one of claims 1-5.

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