Quantum computing task scheduling method, device, computer equipment and storage medium

Abstract

The embodiment of the present application belongs to the field of quantum computing, and relates to a method, device, computer equipment and storage medium for scheduling quantum computing tasks, the method comprising: obtaining multiple quantum computing tasks; generating logical quantum circuits corresponding to each quantum computing task respectively; generating logical topological graphs corresponding to each quantum computing task respectively according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generating a physical topological graph of the quantum chip based on the coupling relationship between the physical quantum bits on the quantum chip; calculating each logical topological graph and the physical topological graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph; executing the quantum computing tasks corresponding to each logical topological graph in parallel through the physical quantum bits corresponding to each physical topological subgraph, and obtaining quantum computing results. The present application improves the task throughput of the quantum processor.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and in particular to a quantum computing task scheduling method, device, computer equipment and storage medium. Background Art

[0002] Quantum computers encode information in quantum bits, and encode the problem to be solved in the operation of quantum gates or the measurement of quantum states, and obtain the answer to the problem based on the final state after measurement. Quantum computing has a significant acceleration in solving some problems compared to classical computing. For example, quantum computing can greatly improve the speed of solving problems such as prime factorization of large numbers and searching disordered databases.

[0003] Quantum computers also require an operating system to manage hardware resources. The task scheduler is the core of the operating system and is responsible for allocating quantum computing tasks to the quantum bits of the quantum processor for execution.

[0004] A quantum processor includes a quantum chip and measurement and control equipment. The quantum chip contains multiple physical quantum bits. Quantum computing tasks usually do not use all the quantum bits on the quantum chip. Most current quantum computers simply execute quantum computing tasks in serial. Although some quantum computers can realize parallel scheduling of quantum computing tasks, they usually execute tasks in the order of the arrival time of quantum computing tasks. If the remaining physical quantum bits meet the needs of the next quantum computing task when executing the current task, the next quantum computing task will be executed in parallel. However, it does not take into account the possible fragmentation problem, that is, some physical quantum bits are idle for a certain period of time, resulting in a waste of physical quantum bits. Therefore, the existing quantum computing task scheduling technology makes the data processing efficiency and task throughput of quantum processors low. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a quantum computing task scheduling method, apparatus, computer equipment and storage medium to improve the task throughput of a quantum processor.

[0006] In order to solve the above technical problems, the embodiment of the present application provides a quantum computing task scheduling method, which adopts the following technical solution:

[0007] Get multiple quantum computing tasks in the current batch;

[0008] Generate logical quantum circuits corresponding to each quantum computing task respectively, wherein the logical quantum circuits include logical quantum bits and quantum gates applied to the logical quantum bits;

[0009] Generate a logical topology diagram corresponding to each of the quantum computing tasks according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generate a physical topology diagram based on the coupling relationship between the physical quantum bits on the quantum chip;

[0010] Calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph;

[0011] The quantum computing tasks corresponding to the respective logical topology graphs are executed in parallel through the physical quantum bits corresponding to the respective physical topology subgraphs to obtain quantum computing results.

[0012] In order to solve the above technical problems, the embodiment of the present application also provides a quantum computing task scheduling device, which adopts the following technical solution:

[0013] The task acquisition module is used to obtain multiple quantum computing tasks in the current batch;

[0014] A circuit generation module is used to generate a logical quantum circuit corresponding to each quantum computing task, wherein the logical quantum circuit includes a logical quantum bit and a quantum gate applied to the logical quantum bit;

[0015] A topology map generation module is used to generate a logical topology map corresponding to each of the quantum computing tasks according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and to generate a physical topology map based on the coupling relationship between the physical quantum bits on the quantum chip;

[0016] A subgraph determination module, used to calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph;

[0017] The task execution module is used to execute the quantum computing tasks corresponding to each logical topology graph in parallel through the physical quantum bits corresponding to each physical topology subgraph to obtain the quantum computing results.

[0018] In order to solve the above technical problems, the embodiment of the present application further provides a computer device, which adopts the following technical solution:

[0019] Get multiple quantum computing tasks in the current batch;

[0020] Generate logical quantum circuits corresponding to each quantum computing task respectively, wherein the logical quantum circuits include logical quantum bits and quantum gates applied to the logical quantum bits;

[0021] Generate a logical topology diagram corresponding to each of the quantum computing tasks according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generate a physical topology diagram based on the coupling relationship between the physical quantum bits on the quantum chip;

[0022] Calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph;

[0023] The quantum computing tasks corresponding to the respective logical topology graphs are executed in parallel through the physical quantum bits corresponding to the respective physical topology subgraphs to obtain quantum computing results.

[0024] In order to solve the above technical problems, the embodiment of the present application further provides a computer-readable storage medium, which adopts the following technical solution:

[0025] Get multiple quantum computing tasks in the current batch;

[0026] Generate logical quantum circuits corresponding to each quantum computing task respectively, wherein the logical quantum circuits include logical quantum bits and quantum gates applied to the logical quantum bits;

[0027] Generate a logical topology diagram corresponding to each of the quantum computing tasks according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generate a physical topology diagram based on the coupling relationship between the physical quantum bits on the quantum chip;

[0028] Calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph;

[0029] The quantum computing tasks corresponding to the respective logical topology graphs are executed in parallel through the physical quantum bits corresponding to the respective physical topology subgraphs to obtain quantum computing results.

[0030] Compared with the prior art, the embodiments of the present application mainly have the following beneficial effects: obtaining multiple quantum computing tasks of the current batch, and generating logical quantum circuits corresponding to each quantum computing task respectively; generating logical topological graphs corresponding to each quantum computing task respectively according to the logical quantum bits contained in each logical quantum circuit and the quantum gates applied to the logical quantum bits, and generating a physical topological graph based on the coupling relationship between the physical quantum bits on the quantum chip; calculating each logical topological graph and the physical topological graph through a preset subgraph matching algorithm and a two-dimensional packing algorithm, and determining the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph, wherein the subgraph matching algorithm ensures that the physical topological subgraph has the same topological structure as the logical topological graph, so that the quantum computing task corresponding to the logical topological graph can be executed; the two-dimensional packing algorithm ensures that the physical quantum bits on the quantum chip can be maximized and the generation of resource fragments can be reduced, so that as many quantum computing tasks as possible can be executed in parallel, thereby improving the data processing efficiency and task throughput of the quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a flow chart of an embodiment of a quantum computing task scheduling method according to the present application;

[0033] Figure 2 is a schematic diagram of an embodiment of a logic quantum circuit according to the present application;

[0034] Figure 3 is a schematic diagram of an embodiment of parallel scheduling of quantum computing tasks according to the present application;

[0035] Figure 4 is a schematic diagram of an embodiment of determining a physical topology subgraph according to the present application;

[0036] Figure 5 is a schematic diagram of the structure of an embodiment of a quantum computing task scheduling device according to the present application;

[0037] Figure 6 It is a structural diagram of an embodiment of a computer device according to the present application. DETAILED DESCRIPTION

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0039] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0040] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0041] It should be noted that the quantum computing task scheduling method provided in the embodiment of the present application is generally executed by a computer device, which may be a quantum computer. Accordingly, the quantum computing task scheduling device is generally arranged in the computer device.

[0042] refer to Figure 1 , shows a flow chart of an embodiment of a quantum computing task scheduling method according to the present application. The quantum computing task scheduling method comprises the following steps:

[0043] Step S101, obtaining multiple quantum computing tasks of the current batch.

[0044] Specifically, the computer device can divide the received quantum computing tasks into batches (mini-batch), and process multiple quantum computing tasks in a batch each time. In one embodiment, the task scheduler adopts the form of a pipeline, and divides the tasks arriving within a preset time window w into a batch according to the arrival time of the quantum computing tasks, so as to realize batch scheduling of tasks. The pipeline means that when the current batch of quantum computing tasks is executed by the quantum processor, the task scheduler schedules the next batch of quantum computing tasks.

[0045] In one embodiment, the operating system loads an executable program file and converts the quantum program in the executable file into a quantum computing task. The quantum computing task is scheduled by a task scheduler and executed on the quantum processor.

[0046] Step S102, respectively generating logical quantum circuits corresponding to each quantum computing task, wherein the logical quantum circuits include logical quantum bits and quantum gates applied to the logical quantum bits.

[0047] Specifically, a logical quantum circuit corresponding to each quantum computing task can be generated. The logical quantum circuit is a form of expression and description of the quantum computing task, which includes logical quantum bits and quantum gates applied to the logical quantum bits. The number of logical quantum bits in the logical quantum circuit and the logical quantum bits on which quantum gates need to be applied can be obtained by calculation. The generation of the logical quantum circuit can be based on existing technical means in the field, which will not be repeated here.

[0048] Step S103, generating a logical topology diagram corresponding to each quantum computing task according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generating a physical topology diagram based on the coupling relationship between the physical quantum bits on the quantum chip.

[0049] Specifically, based on the logical quantum circuit, the number of physical quantum bits required to perform quantum computing tasks and the relationship between physical quantum bits can be determined. The task scheduler schedules quantum computing tasks to be executed on some or all of the physical quantum bits of the quantum chip based on the logical quantum circuit.

[0050] In quantum computing, we cannot simply compare the number of logical qubits required for logical quantum circuits with the number of physical qubits in a quantum chip to determine whether and how a quantum computing task can be placed in a quantum chip. In a quantum chip, some physical qubits are coupled to each other, while others are not. A two-bit gate (a type of quantum gate) can only be applied between two physical qubits that are coupled, so there are topological restrictions when placing quantum computing tasks on a quantum chip.

[0051] To this end, the present application places quantum computing tasks based on a topological map. The topological map includes a logical topological map and a physical topological map. Among them, the logical topological map is generated based on the logical qubits contained in each logical quantum circuit and the quantum gates between the logical qubits. The physical qubits are generated based on the physical qubits on the quantum chip and the coupling relationship between the physical qubits. Among them, the coupling relationship between the physical qubits is determined after the quantum chip is manufactured, and is the inherent information of the quantum chip.

[0052] Furthermore, the above step S103 may include: taking the logical quantum bits contained in each logical quantum circuit as nodes, and connecting the logical quantum bits applied with two-bit quantum gates or multi-bit quantum gates through connecting lines to obtain a logical topology diagram corresponding to each quantum computing task; taking the physical quantum bits on the quantum chip as nodes, and connecting the coupled physical quantum bits through connecting lines to obtain a physical topology diagram of the quantum chip.

[0053] Specifically, for each quantum computing task, the logical quantum circuit corresponding to the quantum computing task is obtained, and each logical quantum bit in the logical quantum circuit is regarded as a node; if two-bit quantum gates or multi-bit quantum gates are applied to some logical quantum bits, the nodes corresponding to these logical quantum bits are connected through connecting lines to obtain the logical topology diagram corresponding to the quantum computing task. Each quantum computing task corresponds to a logical topology diagram.

[0054] Figure 2 is a schematic diagram of a logic quantum circuit in an embodiment, specifically, referring to Figure 2 The logical quantum circuit in includes four logical quantum bits Q0, Q1, Q2 and Q3. The 1, 2, 3 and 4 above indicate the number of circuit layers, and the circuit depth is 4. H, X and CNOT represent quantum gates, where H and X are single-bit gates and CNOT is a two-bit gate. It is easy to see that each quantum computing task in the first-layer circuit is applied with a single-bit gate H; in the second-layer circuit, the logical quantum bits Q1 and Q2 are applied with a two-bit gate CNOT; in the third-layer circuit, the logical quantum bit Q1 is applied with a single-bit gate X; in the fourth-layer circuit, the logical quantum bits Q0 and Q1 are applied with a two-bit gate CNOT. The time required for each quantum gate can be determined when the quantum chip is made. When generating a logical topology diagram, the nodes corresponding to the logical quantum bits to which the same two-bit gate is applied are connected by connecting lines, for example Figure 3 Q0 and Q1, Q1 and Q2 in.

[0055] A physical topology map can be generated based on the entire quantum chip. The physical quantum bits on the quantum chip are taken as nodes. If there is a coupling relationship between two physical quantum bits, the nodes corresponding to the two physical quantum bits are connected by connecting lines to obtain a physical topology map.

[0056] In this embodiment, a logical topology diagram of each logical quantum circuit is generated respectively, and a physical topology diagram of the quantum chip is generated to prepare for the placement of quantum computing tasks on the quantum chip.

[0057] Step S104: Calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph.

[0058] Specifically, in this application, the task scheduler models the parallel scheduling of quantum computing tasks as a two-dimensional strip packing problem (2D strip packing). One dimension in this problem is time, and the other dimension is quantum bits. Each quantum computing task can be regarded as a small rectangle, one dimension represents the task execution time required for the quantum computing task, and the other dimension is the quantum bits required for the task. Among them, the task execution time can be calculated based on the type, number and circuit depth of the quantum gates in the logical quantum circuit. The quantum chip can be regarded as a rectangular strip of fixed width, the physical quantum bits available on the quantum chip can be compared to the width of the rectangular strip, and the time can be compared to the height of the rectangular strip. The task scheduler needs to place the small rectangles of these quantum computing tasks on the rectangular strip without overlapping, and minimize the height of the rectangular strip, that is, the time taken to execute a batch of quantum computing tasks. Figure 3 is a schematic diagram of parallel scheduling of quantum computing tasks in one embodiment. Figure 3 , the current batch of quantum computing tasks includes Task 0, Task 1, Task 2, Task 3 and Task 4, but their execution order may be different. When quantum chips execute quantum computing tasks in parallel, some physical quantum bits may be idle and unused, for example Figure 3 The physical quantum bits represented by the blank polygon a between Task 1 and Task 4 are called resource fragments. It can be understood that the more resource fragments there are, the lower the data processing efficiency and task throughput of the quantum chip will be. This application needs to reduce such resource fragments.

[0059] This application determines the physical quantum bits corresponding to the quantum computing task through a two-dimensional packing algorithm. In the traditional two-dimensional packing technology, the size of the placed object is compared with the size of the placement area. However, in quantum computing, the number of logical quantum bits in the logical quantum circuit and the number of physical quantum bits available on the quantum chip cannot be simply compared. As mentioned earlier, there is a coupling relationship between some physical quantum bits in the quantum chip, and there is no coupling relationship between some physical quantum bits. Only between two physical quantum bits with a coupling relationship can a two-bit gate be applied, so when the quantum computing task is placed on the quantum chip, there are still topological limitations.

[0060] To this end, it is also necessary to find a physical topology subgraph corresponding to the logical topology graph on the quantum chip. The physical topology subgraph has the same topological structure as the logical topology graph, and the search for the physical topology subgraph can be achieved through a subgraph matching algorithm. Among them, subgraph matching refers to finding the same graph structure as the target graph network in the graph network.

[0061] Therefore, the present application determines the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph on the quantum chip through a two-dimensional band packing algorithm and a subgraph matching algorithm to maximize the use of the physical quantum bits on the quantum chip. It can be understood that the physical topology subgraphs do not overlap.

[0062] Figure 4 is a schematic diagram of determining a physical topology subgraph in an embodiment. Specifically, refer to Figure 4 , through the subgraph matching algorithm, the physical topology subgraph corresponding to the logical topology graph is determined on the physical topology graph. The logical topology graph has the same topological structure as the physical topology subgraph, and the physical quantum bits corresponding to the physical topology subgraph will be used to execute the quantum computing tasks corresponding to the logical topology graph.

[0063] Step S105, through the physical quantum bits corresponding to each physical topology subgraph, the quantum computing tasks corresponding to each logical topology subgraph are executed in parallel to obtain the quantum computing results.

[0064] Specifically, after obtaining the physical topology subgraphs corresponding to each logical topology graph, the quantum computing tasks corresponding to each logical topology graph are processed in parallel through the physical quantum bits on the quantum chip corresponding to each physical topology subgraph, so that multiple quantum computing tasks can be processed at the same time, and the physical quantum bits on the quantum chip are used to the maximum extent, reducing the generation of resource fragments on the quantum chip and improving the data processing efficiency and task throughput of the quantum chip. It should be noted that quantum computing tasks in the same batch may not be able to be executed at the same time. Figure 3 In the algorithm, the quantum computing tasks are named Task 0, Task 1, Task 2, Task 3, and Task 4 in order according to the order of task arrival time. After scheduling by the subgraph matching algorithm and the two-dimensional packing algorithm, the execution order of quantum computing tasks in the same batch may be adjusted, and two or several quantum computing tasks can be executed at the same time. The goal is to minimize the time taken by the entire batch. After each group of physical quantum bits completes the calculation, the quantum computing results corresponding to each quantum computing task are obtained.

[0065] In this embodiment, multiple quantum computing tasks of the current batch are obtained, and logical quantum circuits corresponding to each quantum computing task are generated respectively; logical topological graphs corresponding to each quantum computing task are generated according to the logical quantum bits contained in each logical quantum circuit and the quantum gates applied to the logical quantum bits, and a physical topological graph is generated based on the coupling relationship between the physical quantum bits on the quantum chip; each logical topological graph and the physical topological graph are calculated by a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph, wherein the subgraph matching algorithm ensures that the physical topological subgraph has the same topological structure as the logical topological graph, so that the quantum computing task corresponding to the logical topological graph can be executed; the two-dimensional packing algorithm ensures that the physical quantum bits on the quantum chip can be maximized and the generation of resource fragments can be reduced, so that as many quantum computing tasks as possible can be executed in parallel, thereby improving the data processing efficiency and task throughput of the quantum chip.

[0066] Furthermore, the above-mentioned step S103 may include: for each logical topology map, calculating the logical topology map and the physical topology map according to a preset subgraph matching algorithm to obtain at least one candidate subgraph of the logical topology map in the physical topology map; and determining the physical topology subgraph corresponding to the logical topology map in at least one candidate subgraph through a preset two-dimensional packing algorithm.

[0067] Specifically, for each logical topology graph, the logical topology graph and the physical topology graph are calculated according to a preset subgraph matching algorithm to obtain a candidate subgraph of the logical topology graph in the physical topology graph. Since there may be multiple topological structures corresponding to the logical topology graph on the quantum chip, at least one candidate subgraph can be obtained. The present application can use any subgraph matching algorithm to search for candidate subgraphs, including but not limited to VF3, CFL-Match3, GSI and other algorithms.

[0068] After the candidate subgraphs are obtained, each candidate subgraph is calculated using a preset two-dimensional binning algorithm to select the candidate subgraph that best meets the two-dimensional binning idea as the physical topology subgraph corresponding to the logical topology graph.

[0069] In one embodiment, the two-dimensional bin packing algorithm may be any two-dimensional bin packing algorithm, including but not limited to any one of Shelf Algorithms, Guillotine Algorithms, Maximal Rectangles Algorithms, and Skyline Algorithm.

[0070] In one embodiment, a two-dimensional packing algorithm has a preset indicator. After the object to be placed (such as the logical topology map of the quantum computing task in the present application) is placed in a candidate sub-area (such as the candidate sub-map in the present application) in the target area (such as the physical topology map corresponding to the quantum chip), the indicator value of the preset indicator can be calculated. The indicator value is used to evaluate whether the placement operation is appropriate. The final sub-area (such as the physical topology sub-map in the present application) can be determined in each candidate sub-area according to the indicator value of the preset indicator.

[0071] In this embodiment, the logical topology graph and the physical topology graph are calculated by a subgraph matching algorithm to obtain a candidate subgraph, and then the physical topology subgraph is determined in the candidate subgraph by a two-dimensional band packing algorithm, thereby maximizing the use of the physical quantum bits on the quantum chip.

[0072] Furthermore, after the above-mentioned step of calculating the logical topology map and the physical topology map according to the preset subgraph matching algorithm, it can also include: when there is no candidate subgraph corresponding to the logical topology map in the physical topology map, counting the number of available quantum bits of the physical topology map; when the number of available quantum bits is greater than or equal to the number of logical quantum bits of the logical topology map, performing line conversion on the logical topology map; calculating the logical topology map and the physical topology map after line conversion by using the subgraph matching algorithm to obtain at least one candidate subgraph.

[0073] Specifically, when calculating the logical topology graph and the physical topology graph through the subgraph matching algorithm, it may be impossible to find the candidate subgraph. At this time, the quantum computing task corresponding to the logical topology graph cannot be directly executed through the physical quantum bits on the current quantum chip.

[0074] At this point, the number of currently available physical qubits in the physical topology can be counted to obtain the number of available qubits; then, the number of logical qubits in the logical topology can be counted to obtain the number of logical qubits. If the number of available qubits is greater than or equal to the number of logical qubits, it may be due to the limitation of the topological structure that the candidate subgraph cannot be found.

[0075] At this time, the logical topology graph can be converted. In one embodiment, a SWAP gate can be added to the logical topology graph to exchange the quantum states of two logical qubits to achieve circuit conversion. Then, the logical topology graph and the physical topology graph after circuit conversion are calculated by a subgraph matching algorithm to obtain at least one candidate subgraph.

[0076] In this embodiment, when there is no candidate subgraph corresponding to the logical topology graph in the physical topology graph, and the number of available quantum bits in the physical topology graph is greater than or equal to the number of logical quantum bits in the logical topology graph, the logical topology graph is converted, and the logical topology graph after the circuit conversion is recalculated through the subgraph matching algorithm to obtain a candidate subgraph, thereby ensuring that the quantum chip can perform as many quantum computing tasks as possible.

[0077] Furthermore, after the step of executing the quantum computing tasks corresponding to each logical topology graph in parallel through the physical quantum bits corresponding to each physical topology subgraph, the method may also include: obtaining multiple second quantum computing tasks of the next batch; judging whether there are insertable tasks among the multiple second quantum computing tasks according to preset task insertion conditions; and when there are insertable tasks, executing the insertable tasks and the quantum computing tasks of the current batch in parallel through the current quantum chip.

[0078] Specifically, after the quantum computing tasks corresponding to each logical topology graph are executed in parallel through the physical quantum bits corresponding to each physical topology subgraph, the task scheduler can also obtain multiple second quantum computing tasks of the next batch.

[0079] This application maximizes the utilization of physical quantum bits on a quantum chip through a subgraph matching algorithm and a two-dimensional band packing algorithm. However, when a quantum chip is performing a quantum computing task, there may still be sporadic resource fragments on the quantum chip.

[0080] To this end, when the next batch of multiple second quantum computing tasks arrives, it can be determined whether there are insertable tasks among the multiple second quantum computing tasks according to the preset insertion conditions. An insertable task means that a quantum computing task can be inserted into the quantum chip currently in the operating state without affecting the operation of the quantum computing tasks currently in the operating state.

[0081] If there are insertable tasks, the insertable tasks will be adjusted into the current batch of multiple quantum computing tasks, and the quantum chip will execute them in parallel to obtain the quantum computing results.

[0082] In this embodiment, when the current batch of quantum computing tasks is being executed, if there are insertable tasks in the second quantum computing tasks of the next batch, the current batch of quantum computing tasks and the insertable tasks are executed in parallel by the quantum chip, further improving the task throughput and data processing efficiency of the quantum chip.

[0083] Furthermore, the above-mentioned step of judging whether there is an insertable task in multiple second quantum computing tasks according to the preset task insertion condition may include: for each second quantum computing task, generating a second logical quantum circuit and a second logical topology graph corresponding to the second quantum computing task; judging whether there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph by a subgraph matching algorithm and a two-dimensional band packing algorithm, wherein the physical topology graph related information includes the physical topology subgraph corresponding to each quantum computing task of the current batch; determining the task execution time of the current batch according to the logical quantum circuits of each quantum computing task of the current batch, and obtaining the executed time of the current batch; determining the second task execution time of the second quantum computing task according to the second logical quantum circuit; when the task execution time, the executed time and the second task execution time meet the preset time condition, and the second physical topology subgraph corresponding to the second logical topology graph exists in the physical topology graph, determining the second quantum computing task as an insertable task.

[0084] Specifically, for each second quantum computing task in the next batch, a second logical quantum circuit and a second logical topology graph corresponding to the second quantum computing task are generated. Then, through the subgraph matching algorithm and the two-dimensional packing algorithm, it is determined whether there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph. Among them, when calculating the subgraph matching algorithm and the two-dimensional packing algorithm for the second logical topology graph, the physical topology subgraphs of each quantum computing task in the current batch need to be taken into account, that is, the physical topology subgraphs of each quantum computing task in the current batch have occupied certain areas in the physical topology graph, and the second physical topology subgraph corresponding to the second logical topology graph can only be found in the unoccupied areas of the physical topology graph.

[0085] Each quantum computing task of the current batch has a task execution time, that is, the length of time required for the quantum chip to complete all the quantum computing tasks of the current batch. The task execution time can be determined based on the logical quantum circuits of each quantum computing task. Figure 2 For example, the logic quantum circuit contains 4 layers. In each layer of the circuit, the application time of the quantum gate is known. The longest application time is selected as the time required for the circuit of this layer, and then the time required for each layer of the circuit is added to obtain the execution time of the quantum computing task corresponding to the logic quantum circuit. The quantum computing tasks in the current batch may not all be executed at the same time, for example Figure 3 In the process, the quantum computing tasks are named Task 0, Task 1, Task 2, Task 3, and Task 4 according to the order of task arrival time. Their execution times can be different. After scheduling, the task execution order will be adjusted. At least one quantum computing task is executed each time. The execution time of each quantum computing task is accumulated to obtain the task execution time of the current batch.

[0086] The quantum computing tasks of the current batch also have an execution time, which is the length of time that multiple quantum computing tasks of the current batch have been executed.

[0087] Then, the second task execution time of the second quantum computing task is calculated according to the second logical quantum circuit. If there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph, and the sum of the executed time and the second task execution time is less than or equal to the fragment idle time (the start time of the next time the physical quantum bits constituting the resource fragment are occupied by the quantum computing task minus the end time of the last time they were occupied by the quantum computing task), the second quantum computing task is inserted into the multiple quantum computing tasks of the current batch, and the second quantum computing task does not affect the final completion time of the multiple quantum computing tasks of the current batch, then the second quantum computing task meets the preset task insertion condition, and the second quantum computing task is determined as an insertable task.

[0088] In one embodiment, if the second physical topology subgraph corresponding to the second quantum computing task cannot be directly found through the subgraph matching algorithm and the two-dimensional band packing algorithm, the second logical quantum circuit of the second quantum computing task can also be converted to determine whether the second physical topology subgraph exists in the physical topology graph after the second logical quantum circuit is converted.

[0089] In this embodiment, it is determined whether there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph, and whether the second quantum computing task affects the final completion time of multiple quantum computing tasks in the current batch is determined through the task execution time, the executed time and the second task execution time of the second quantum computing task in the current batch. It can be accurately determined whether the second quantum task is an insertable task, and thus it can be determined whether to insert the second quantum computing task into the multiple quantum computing tasks in the current batch.

[0090] Furthermore, the quantum computing tasks contained in each batch are divided according to the order of arrival time of the quantum computing tasks. The above-mentioned quantum computing task scheduling method may also include: obtaining the quantum computing tasks to be scheduled; when there is no batch being executed and there is no waiting task, executing the quantum computing task; otherwise, marking the quantum computing task as a waiting task; when the expected waiting time of the waiting task is greater than the preset time, dividing the waiting task into a batch, and scheduling the quantum computing tasks in the batch according to the subgraph matching algorithm and the two-dimensional band packing algorithm.

[0091] Among them, the waiting task can be a quantum computing task that has not yet been executed by the quantum chip.

[0092] Specifically, the task scheduler divides the multiple quantum computing tasks into different batches according to the order of their arrival time, where the arrival time may be the time when the quantum computing task is submitted to the quantum computer. In one embodiment, the task scheduler may divide the quantum computing tasks received within the preset time w into a batch (mini-batch) every preset time w. The task scheduler obtains the quantum computing task to be scheduled. If there is no batch being executed at this time and there is no waiting task (for example, this state may occur after initialization), the task scheduler will directly execute the quantum computing task through the quantum chip.

[0093] Otherwise, the quantum computing task is marked as a waiting task. The waiting task has an estimated waiting time. Assume that the execution time of the current batch of tasks being executed is t t , the start execution time of the current batch is t0, the current time is t1, then the estimated waiting time of the quantum computing task to be scheduled is t t -(t1-t0). If the expected waiting time is longer than the preset time, the current waiting tasks are divided into a batch, and the quantum computing tasks in the batch are scheduled according to the subgraph matching algorithm and the two-dimensional packing algorithm to avoid the quantum computing tasks being in a waiting state for a long time.

[0094] In this embodiment, when a quantum computing task can be executed directly, the task is executed directly; when the task enters a waiting state and the expected waiting time is greater than a preset time, a pipeline-style small batch scheduling is performed to avoid the quantum computing task being in a waiting state for a long time and unable to be executed.

[0095] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through computer-readable instructions, and the computer-readable instructions can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the aforementioned storage medium can be a non-volatile storage medium such as a disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0096] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0097] Further references Figure 5 , as a response to the above Figure 1 The present application provides an embodiment of a quantum computing task scheduling device, and the device embodiment is similar to Figure 1 Corresponding to the method embodiment shown, the device can be specifically applied to various electronic devices.

[0098] like Figure 5 As shown, the quantum computing task scheduling device 200 described in this embodiment includes: a task acquisition module 201, a circuit generation module 202, a topology map generation module 203, a subgraph determination module 204 and a task execution module 205, wherein:

[0099] The task acquisition module 201 is used to acquire multiple quantum computing tasks of the current batch.

[0100] The circuit generation module 202 is used to generate the logical quantum circuits corresponding to each quantum computing task, wherein the logical quantum circuits include logical quantum bits and quantum gates applied to the logical quantum bits.

[0101] The topology map generation module 203 is used to generate a logical topology map corresponding to each quantum computing task according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and to generate a physical topology map based on the coupling relationship between the physical quantum bits on the quantum chip.

[0102] The subgraph determination module 204 is used to calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph.

[0103] The task execution module 205 is used to execute the quantum computing tasks corresponding to each logical topology graph in parallel through the physical quantum bits corresponding to each physical topology subgraph to obtain the quantum computing results.

[0104] In this embodiment, multiple quantum computing tasks of the current batch are obtained, and logical quantum circuits corresponding to each quantum computing task are generated respectively; logical topological graphs corresponding to each quantum computing task are generated according to the logical quantum bits contained in each logical quantum circuit and the quantum gates applied to the logical quantum bits, and a physical topological graph is generated based on the coupling relationship between the physical quantum bits on the quantum chip; each logical topological graph and the physical topological graph are calculated by a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph, wherein the subgraph matching algorithm ensures that the physical topological subgraph has the same topological structure as the logical topological graph, so that the quantum computing task corresponding to the logical topological graph can be executed; the two-dimensional packing algorithm ensures that the physical quantum bits on the quantum chip can be maximized and the generation of resource fragments can be reduced, so that as many quantum computing tasks as possible can be executed in parallel, thereby improving the data processing efficiency and task throughput of the quantum chip.

[0105] In some optional implementations of this embodiment, the topology map generation module 203 may include: a logic generation submodule and a physical generation submodule, wherein:

[0106] The logic generation submodule is used to use the logic quantum bits contained in each logic quantum circuit as nodes, and connect the logic quantum bits with two-bit quantum gates or multi-bit quantum gates through connecting lines to obtain the logic topology diagram corresponding to each quantum computing task.

[0107] The physical generation submodule is used to use the physical quantum bits on the quantum chip as nodes and connect the coupled physical quantum bits through connecting lines to obtain the physical topology diagram of the quantum chip.

[0108] In this embodiment, a logical topology diagram of each logical quantum circuit is generated respectively, and a physical topology diagram of the quantum chip is generated to prepare for the placement of quantum computing tasks on the quantum chip.

[0109] In some optional implementations of this embodiment, the subgraph determination module 204 may include: a candidate calculation submodule and a subgraph determination submodule, wherein:

[0110] The candidate calculation submodule is used to calculate the logical topology map and the physical topology map according to a preset sub-map matching algorithm for each logical topology map, and obtain at least one candidate sub-map of the logical topology map in the physical topology map.

[0111] The subgraph determination submodule is used to determine the physical topology subgraph corresponding to the logical topology graph from at least one candidate subgraph by using a preset two-dimensional binning algorithm.

[0112] In this embodiment, the logical topology graph and the physical topology graph are calculated by a subgraph matching algorithm to obtain a candidate subgraph, and then the physical topology subgraph is determined in the candidate subgraph by a two-dimensional band packing algorithm, thereby maximizing the use of the physical quantum bits on the quantum chip.

[0113] In some optional implementations of this embodiment, the candidate calculation submodule may further include: an available statistics unit, a line conversion unit, and a topology map calculation unit, wherein:

[0114] The available statistical unit is used to count the number of available quantum bits in the physical topology map when there is no candidate sub-map corresponding to the logical topology map in the physical topology map.

[0115] The circuit conversion unit is used to perform circuit conversion on the logical topology diagram when the number of available quantum bits is greater than or equal to the number of logical quantum bits in the logical topology diagram.

[0116] The topology map calculation unit is used to calculate the logical topology map and the physical topology map after the line conversion through a sub-map matching algorithm to obtain at least one candidate sub-map.

[0117] In this embodiment, when there is no candidate subgraph corresponding to the logical topology graph in the physical topology graph, and the number of available quantum bits in the physical topology graph is greater than or equal to the number of logical quantum bits in the logical topology graph, the logical topology graph is converted, and the logical topology graph after the circuit conversion is recalculated through the subgraph matching algorithm to obtain a candidate subgraph, thereby ensuring that the quantum chip can perform as many quantum computing tasks as possible.

[0118] In some optional implementations of this embodiment, the task execution module 305 may include: a task acquisition submodule, a task judgment submodule and a parallel execution submodule, wherein:

[0119] The task acquisition submodule is used to obtain multiple second quantum computing tasks for the next batch.

[0120] The task judgment submodule is used to judge whether there is an insertable task in the multiple second quantum computing tasks according to the preset task insertion conditions.

[0121] The parallel execution submodule is used to execute the insertable task and each quantum computing task of the current batch in parallel through the current quantum chip when there is an insertable task.

[0122] In this embodiment, when the current batch of quantum computing tasks is being executed, if there are insertable tasks in the second quantum computing tasks of the next batch, the current batch of quantum computing tasks and the insertable tasks are executed in parallel by the quantum chip, further improving the task throughput and data processing efficiency of the quantum chip.

[0123] In some other optional implementations of this embodiment, the quantum computing task scheduling device 200 may further include a first judgment module, which is used to: obtain multiple second quantum computing tasks of the next batch; determine whether there are insertable tasks in the multiple second quantum computing tasks according to preset task insertion conditions; when there are insertable tasks, execute the insertable tasks and each quantum computing task in parallel through the current quantum chip.

[0124] In this embodiment, when the current batch of quantum computing tasks is being executed, if there are insertable tasks in the second quantum computing tasks of the next batch, the current batch of quantum computing tasks and the insertable tasks are executed in parallel by the quantum chip, further improving the task throughput and data processing efficiency of the quantum chip.

[0125] In some optional implementations of this embodiment, the task determination submodule may include: a generation unit, a subgraph determination unit, a current determination unit, a time determination unit, and a task determination unit, wherein:

[0126] A generating unit is used to generate, for each second quantum computing task, a second logical quantum circuit and a second logical topology graph corresponding to the second quantum computing task.

[0127] The subgraph determination unit is used to determine whether there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph through a subgraph matching algorithm and a two-dimensional packing algorithm, wherein the physical topology graph contains the physical topology subgraphs corresponding to each quantum computing task of the current batch.

[0128] The current determination unit is used to determine the task execution time of the current batch according to the logical quantum circuits of each quantum computing task of the current batch, and obtain the execution time of the current batch.

[0129] A time determination unit is used to determine a second task execution time of a second quantum computing task according to a second logical quantum circuit.

[0130] The task determination unit is used to determine that the second quantum computing task is an insertable task when the task execution time, the executed time and the second task execution time meet the preset time conditions and the second physical topology subgraph corresponding to the second logical topology graph exists in the physical topology graph.

[0131] In this embodiment, it is determined whether there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph, and whether the second quantum computing task affects the final completion time of multiple quantum computing tasks in the current batch is determined through the task execution time, the executed time and the second task execution time of the second quantum computing task in the current batch. It can be accurately determined whether the second quantum task is an insertable task, and thus it can be determined whether to insert the second quantum computing task into the multiple quantum computing tasks in the current batch.

[0132] In some optional implementations of this embodiment, the quantum computing tasks included in each batch are divided according to the order of arrival time of the quantum computing tasks; then the quantum computing task scheduling device 200 may also include: a single task acquisition module, a single task execution module, a single task marking module and a task batching module, wherein:

[0133] A single task acquisition module is used to obtain quantum computing tasks to be scheduled.

[0134] A single task execution module is used to execute quantum computing tasks when there is no batch being executed and no waiting tasks.

[0135] A single task marking module is used to mark a quantum computing task as a waiting task when there is a batch being executed or a waiting task.

[0136] The task batching module is used to divide the waiting tasks into a batch when the expected waiting time of the waiting tasks is greater than the preset time, and schedule the quantum computing tasks in the batch according to the subgraph matching algorithm and the two-dimensional packing algorithm.

[0137] In this embodiment, when the quantum computing task can be executed directly, the task is executed directly; when the task is in a waiting state and the expected waiting time is greater than the preset time, small batch scheduling is performed in an assembly line manner to avoid the quantum computing task being in a waiting state for a long time and unable to be executed.

[0138] In some other optional implementations of this embodiment, the quantum computing tasks included in each batch are divided according to the order of arrival time of the quantum computing tasks; the quantum computing task scheduling device 200 may also include a second judgment module, which is used to: obtain the quantum computing tasks to be scheduled; when there is no batch being executed and there is no waiting task, execute the quantum computing task; when there is a batch being executed or there is a waiting task, mark the quantum computing task as a waiting task; when the expected waiting time of the waiting task is greater than the preset time, divide the waiting task into a batch, and schedule the quantum computing tasks in the batch according to the subgraph matching algorithm and the two-dimensional band packing algorithm.

[0139] In this embodiment, when the quantum computing task can be executed directly, the task is executed directly; when the task is in a waiting state and the expected waiting time is greater than the preset time, small batch scheduling is performed in an assembly line manner to avoid the quantum computing task being in a waiting state for a long time and unable to be executed.

[0140] To solve the above technical problems, the present application also provides a computer device. Figure 6 , Figure 6 This is a basic structural block diagram of the computer device in this embodiment.

[0141] The computer device is a quantum computer device, which may include an operating system, a classical processor, a quantum processor, and a memory. The operating system is a manager of hardware resources, and the operating system has a task scheduler that can assign quantum computing tasks to the quantum bits of the quantum processor for execution. The quantum processor has a quantum chip and a measurement and control device, wherein the quantum chip includes multiple physical quantum bits, which are responsible for executing quantum computing tasks; the measurement and control device is used to measure the physical quantum bits to obtain quantum computing results.

[0142] The classical processor may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip in some embodiments. The classical processor is generally used to control the overall operation of the computer device. In this embodiment, the classical processor is used to run the computer-readable instructions stored in the memory or process data, such as running the computer-readable instructions in the quantum computing task scheduling method.

[0143] Among them, the classical processor can perform the following steps: obtain multiple quantum computing tasks of the current batch; generate logical quantum circuits corresponding to each quantum computing task respectively, wherein the logical quantum circuits contain logical quantum bits and quantum gates applied to the logical quantum bits; generate logical topological graphs corresponding to each quantum computing task according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generate a physical topological graph based on the coupling relationship between physical quantum bits on the quantum chip; calculate each logical topological graph and physical topological graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph; the quantum processor can perform the following steps: execute the quantum computing tasks corresponding to each logical topological graph in parallel through the physical quantum bits corresponding to each physical topological subgraph to obtain the quantum computing results.

[0144] It should be noted that the figure only shows the basic structure of the quantum computer device, but it should be understood that it is not required to implement all the components shown, and more or fewer components may be implemented instead. For example, the computer device may also include a network interface, which may include a wireless network interface or a wired network interface, and the network interface is generally used to establish a communication connection between the computer device and other electronic devices. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, except Figure 6 The structure shown in the figure includes, but is not limited to, a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc.

[0145] The memory includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (for example, SD or DX memory, etc.), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, disk, optical disk, etc. In some embodiments, the memory can be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory can also be an external storage device of the computer device, such as a plug-in hard disk equipped on the computer device, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. Of course, the memory can also include both the internal storage unit of the computer device and its external storage device. In this embodiment, the memory can be used to store the operating system and various application software installed on the computer device, such as computer-readable instructions of the quantum computing task scheduling method, etc. In addition, the memory can also be used to temporarily store various types of data that have been output or are to be output.

[0146] The computer device provided in this embodiment can execute the above-mentioned quantum computing task scheduling method. Here, the quantum computing task scheduling method can be the quantum computing task scheduling method of each of the above-mentioned embodiments.

[0147] In this embodiment, multiple quantum computing tasks of the current batch are obtained, and logical quantum circuits corresponding to each quantum computing task are generated respectively; logical topological graphs corresponding to each quantum computing task are generated according to the logical quantum bits contained in each logical quantum circuit and the quantum gates applied to the logical quantum bits, and a physical topological graph is generated based on the coupling relationship between the physical quantum bits on the quantum chip; each logical topological graph and the physical topological graph are calculated by a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph, wherein the subgraph matching algorithm ensures that the physical topological subgraph has the same topological structure as the logical topological graph, so that the quantum computing task corresponding to the logical topological graph can be executed; the two-dimensional packing algorithm ensures that the physical quantum bits on the quantum chip can be maximized and the generation of resource fragments can be reduced, so that as many quantum computing tasks as possible can be executed in parallel, thereby improving the data processing efficiency and task throughput of the quantum chip.

[0148] The present application also provides another implementation, namely, providing a computer-readable storage medium, which is a quantum computer-readable storage medium, and which stores computer-readable instructions, which can be executed by at least one processor to enable the at least one processor to perform the steps of the quantum computing task scheduling method as described above.

[0149] In this embodiment, multiple quantum computing tasks of the current batch are obtained, and logical quantum circuits corresponding to each quantum computing task are generated respectively; logical topological graphs corresponding to each quantum computing task are generated according to the logical quantum bits contained in each logical quantum circuit and the quantum gates applied to the logical quantum bits, and a physical topological graph is generated based on the coupling relationship between the physical quantum bits on the quantum chip; each logical topological graph and the physical topological graph are calculated by a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topological subgraphs corresponding to each logical topological graph in the physical topological graph, wherein the subgraph matching algorithm ensures that the physical topological subgraph has the same topological structure as the logical topological graph, so that the quantum computing task corresponding to the logical topological graph can be executed; the two-dimensional packing algorithm ensures that the physical quantum bits on the quantum chip can be maximized and the generation of resource fragments can be reduced, so that as many quantum computing tasks as possible can be executed in parallel, thereby improving the data processing efficiency and task throughput of the quantum chip.

[0150] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0151] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to perform equivalent replacement of some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. A quantum computing task scheduling method, characterized in that: The steps include: Get multiple quantum computing tasks in the current batch; Generate logical quantum circuits corresponding to each quantum computing task respectively, wherein the logical quantum circuits include logical quantum bits and quantum gates applied to the logical quantum bits; Generate a logical topology diagram corresponding to each of the quantum computing tasks according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and generate a physical topology diagram based on the coupling relationship between the physical quantum bits on the quantum chip; Calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph; Through the physical quantum bits corresponding to each physical topology subgraph, the quantum computing tasks corresponding to each logical topology subgraph are executed in parallel to obtain a quantum computing result; The step of calculating each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph comprises: For each logical topology graph, the logical topology graph and the physical topology graph are calculated according to a preset subgraph matching algorithm to obtain at least one candidate subgraph of the logical topology graph in the physical topology graph; The physical topology subgraph corresponding to the logical topology graph is determined in the at least one candidate subgraph by using a preset two-dimensional binning algorithm.

2. The quantum computing task scheduling method according to claim 1, characterized in that: The step of generating the logical topology graphs corresponding to the quantum computing tasks respectively according to the logical quantum bits and quantum gates included in each logical quantum circuit, and generating the physical topology graph based on the coupling relationship between the physical quantum bits on the quantum chip includes: The logical quantum bits contained in each of the logical quantum circuits are respectively used as nodes, and the logical quantum bits to which the two-bit quantum gates or multi-bit quantum gates are applied are connected through connecting lines to obtain a logical topology diagram corresponding to each of the quantum computing tasks; The physical quantum bits on the quantum chip are used as nodes, and the coupled physical quantum bits are connected by connecting lines to obtain a physical topological map of the quantum chip.

3. The quantum computing task scheduling method according to claim 1, characterized in that: After the step of calculating the logical topology map and the physical topology map according to the preset sub-graph matching algorithm, the method further includes: When there is no candidate subgraph corresponding to the logical topology graph in the physical topology graph, counting the number of available quantum bits in the physical topology graph; When the number of available quantum bits is greater than or equal to the number of logical quantum bits of the logical topology diagram, performing line conversion on the logical topology diagram; The logical topology graph and the physical topology graph after line conversion are calculated by the subgraph matching algorithm to obtain at least one candidate subgraph.

4. The quantum computing task scheduling method according to claim 1, characterized in that: After the step of executing the quantum computing tasks corresponding to the logical topology graphs respectively in parallel by using the physical quantum bits corresponding to the physical topology subgraphs, the method further includes: Obtaining multiple second quantum computing tasks of the next batch; According to a preset task insertion condition, determining whether there is an insertable task in the plurality of second quantum computing tasks; When there is an insertable task, the insertable task and the quantum computing tasks of the current batch are executed in parallel by the current quantum chip.

5. The quantum computing task scheduling method according to claim 4, characterized in that: The step of judging whether there is an insertable task in the plurality of second quantum computing tasks according to the preset task insertion condition comprises: For each second quantum computing task, generating a second logic quantum circuit and a second logic topology graph corresponding to the second quantum computing task; By using the subgraph matching algorithm and the two-dimensional box packing algorithm, it is determined whether there is a second physical topology subgraph corresponding to the second logical topology graph in the physical topology graph, wherein the physical topology graph contains the physical topology subgraphs corresponding to the quantum computing tasks of the current batch; Determine the task execution time of the current batch according to the logical quantum circuits of each quantum computing task of the current batch, and obtain the execution time of the current batch; the task execution time is the length of time required for the quantum chip to complete all the quantum computing tasks of the current batch; Determine a second task execution time of the second quantum computing task according to the second logic quantum circuit; When the task execution time, the executed time and the second task execution time meet a preset time condition, and a second physical topology subgraph corresponding to the second logical topology graph exists in the physical topology graph, the second quantum computing task is determined to be an insertable task.

6. The quantum computing task scheduling method according to claim 1, characterized in that: The quantum computing tasks contained in each batch are divided according to the order of arrival time of the quantum computing tasks. The method further includes: Get the quantum computing tasks to be scheduled; When there is no batch being executed and no waiting task, execute the quantum computing task; Otherwise, marking the quantum computing task as a waiting task; When the expected waiting time of the waiting task is greater than the preset time, the waiting task is divided into a batch, and the quantum computing tasks in the batch are scheduled according to the subgraph matching algorithm and the two-dimensional packing algorithm.

7. A quantum computing task scheduling device, characterized in that: include: The task acquisition module is used to obtain multiple quantum computing tasks in the current batch; A circuit generation module is used to generate a logical quantum circuit corresponding to each quantum computing task, wherein the logical quantum circuit includes a logical quantum bit and a quantum gate applied to the logical quantum bit; A topology map generation module is used to generate a logical topology map corresponding to each of the quantum computing tasks according to the logical quantum bits and quantum gates contained in each logical quantum circuit, and to generate a physical topology map based on the coupling relationship between the physical quantum bits on the quantum chip; A subgraph determination module, used to calculate each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph; A task execution module, used to execute the quantum computing tasks corresponding to each of the logical topology graphs in parallel through the physical quantum bits corresponding to each of the physical topology subgraphs, to obtain a quantum computing result; The calculating of each logical topology graph and the physical topology graph according to a preset subgraph matching algorithm and a two-dimensional packing algorithm to determine the physical topology subgraphs corresponding to each logical topology graph in the physical topology graph includes: For each logical topology graph, the logical topology graph and the physical topology graph are calculated according to a preset subgraph matching algorithm to obtain at least one candidate subgraph of the logical topology graph in the physical topology graph; The physical topology subgraph corresponding to the logical topology graph is determined in the at least one candidate subgraph by using a preset two-dimensional binning algorithm.

8. A computer device, characterized in that: The computer device is a quantum computer, which includes a memory, a classical processor and a quantum processor. The memory stores computer-readable instructions. When the quantum computer executes the computer-readable instructions, the steps of the quantum computing task scheduling method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, which, when executed by a quantum computer, implement the steps of the quantum computing task scheduling method according to any one of claims 1 to 6.

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