A receiving and storing device and method for multi-packet serial data based on FPGA

Abstract

This invention belongs to the field of data transmission and network communication technology, and discloses an FPGA-based device and method for receiving and storing multi-packet serial data. It receives data packets with various tags through a serial data interface and stores them separately in specific double buffers according to their tag numbers for later retrieval. Storing data packets with different tag numbers in separate buffers improves the efficiency of the host computer in reading specific data packets; the double buffer mechanism enhances the stability and reliability of data transmission and improves the security of the data reading process.

Description

Technical Field

[0001] This invention belongs to the field of data transmission and network communication technology, and particularly relates to an FPGA-based device and method for receiving and storing multi-packet serial data. Background Technology

[0002] For typical serial data reception methods, sequential storage is usually used. The host computer cannot easily read the specific data packets it is most interested in. At the same time, when the serial data interface continuously receives different types of data packets, if the host computer cannot read the received data in time, the received data in the storage area will be overwritten by the subsequently received data, resulting in data loss and damage to data packet integrity, which is not conducive to secure data transmission. Summary of the Invention

[0003] The purpose of this invention is to provide an FPGA-based device and method for receiving and storing multi-packet serial data, which enables the reception of multiple data packets with different tags through a single serial data interface and stores them in different double-buffered storage areas for the host computer to read, thus ensuring the integrity and secure transmission of multiple data packets.

[0004] The technical solution of the present invention: In order to achieve the above-mentioned objectives, the present invention adopts the following technical solution.

[0005] A multi-packet serial data receiving and storage device based on FPGA, the receiving and storage device comprising: a serial data receiving and parsing module 1, a FIFO buffer module 2, an address decoding module 3, a multi-channel dual buffer control module 4, a data storage control module 5, and a RAM data storage area 6; The data output terminal of the serial data receiving and parsing module 1 is connected to the data input terminal of the FIFO buffer module 2, the address decoding module 3, and the multi-channel dual buffer control module 4; The data input terminal of FIFO buffer module 2 is connected to the data output terminal of serial data receiving and parsing module 1, and the data output terminal of FIFO buffer module 2 is connected to the data input terminal of data storage control module 5. The data input terminal of the address decoding module 3 is connected to the data output terminal of the serial data receiving and parsing module 1, and the data output terminal of the address decoding module 3 is connected to the input terminals of the multi-channel dual-buffer control module 4 and the data storage module 5. The data input terminal of the multi-channel dual-buffer control module 4 is connected to the serial data receiving and parsing module 1, the address decoding module 3, and the data output terminal of the host computer. The data output terminal of the multi-channel dual-buffer control module 4 is connected to the RAM data storage area 6 and the data input terminal of the host computer. The data input terminal of the data storage control module 5 is connected to the data output terminals of the FIFO cache module 2 and the address decoding module 3; the data output terminal of the data storage control module 5 is connected to the data input terminal of the RAM data storage area 6. The data input terminal of RAM data storage area 6 is connected to the data output terminals of multi-channel dual-buffer control module 4 and data storage control module 5, and the data output terminal of RAM data storage area 6 is connected to the data input terminal of the host computer.

[0006] The features and further improvements of the technical solution of this invention are as follows: The serial data receiving and parsing module 1 is used to convert the received serial data stream into parallel data, and to parse the parallel data into data packets, parse out the label number of the data packet, and send a storage area request signal get_e to the multi-channel dual buffer control module; after the data packet is received, it is also used to send a data commit signal commit_e to the multi-channel dual buffer control module. FIFO cache module 2 is used to cache the parsed parallel data; Address decoding module 3 is used to decode the write channel number write_id and the starting address of the corresponding RAM storage area based on the parsed data packet label number; The multi-channel dual-buffer control module 4 is used to control the dual-buffer switching signal according to the state of the control signal. Data storage control module 5 is used to store the parallel data in the FIFO cache module into the double buffer storage area according to the storage address decoded by the address decoding module. RAM data storage area 6 is used to store the received data.

[0007] Technical Solution Two: A method for receiving and storing multi-packet serial data based on FPGA, implemented using the device described in technical solution one, the method comprising: S1, the serial data receiving and parsing module 1 converts the received serial data stream into parallel data, performs data packet parsing on the parallel data, parses out the label number of the data packet, and sends a storage area request signal get_e to the multi-channel dual buffer control module; after the data packet is received, it is also used to send a data commit signal commit_e to the multi-channel dual buffer control module. S2, FIFO cache module 2 caches the parsed parallel data; S3, the address decoding module 3 decodes the write channel number write_id and the starting address of the corresponding RAM storage area based on the parsed data packet label number; S4, the multi-channel dual-buffer control module 4 controls the dual-buffer switching signal according to the state of the control signal; the control signal includes: the memory area request signal get_e and the data commit signal commit_e from the serial data receiving and parsing module 1, the write channel number write_id from the address decoding module 3, the read channel number read_id from the host computer, the lock signal lock_buffer_e, and the unlock signal unlock_buffer_e; S5, the data storage control module 5 stores the parallel data in the FIFO cache module into the double buffer storage area according to the storage address decoded by the address decoding module; S6, RAM data storage area 6 stores the received data.

[0008] The features and further improvements of the second technical solution of the present invention are as follows: (1) In S1, the serial data receiving and parsing module 1 will send the storage area request signal get_e only after parsing a valid label number; after the serial data receiving and parsing module 1 completes the reception of the current data packet, it will perform CRC verification, and will send the data commit signal commit_e only after the CRC verification is correct.

[0009] (2) In S2, the FIFO buffer module buffers the parallel data before parsing the label number of the data packet. If the label number parsed by the serial data receiving and parsing module 1 is invalid, the data in the FIFO buffer module is cleared.

[0010] (3) In S4, when the multi-channel dual-buffer control module 4 receives the write channel number write_id and the data commit signal commit_e, it sends the data ready flag of the channel to the host computer; After receiving the data ready flag, the host computer will send the read channel number read_id and the lock signal lock_buffer_e to the multi-channel dual buffer control module before reading the data; after reading the data, it will send the read channel number read_id and the unlock signal unlock_buffer_e to the multi-channel dual buffer control module. If the current read channel double buffer is in an unlocked state, upon receiving the lock_buffer_e signal, the channel double buffer will switch to a locked state; if the current channel double buffer is in a locked state, upon receiving the unlock_buffer_e signal, the data ready flag will be reset, and the channel double buffer will switch to an unlocked state. When the multi-channel dual buffer control module 4 receives the write channel number write_id and the data commit signal commit_e again, if the current channel dual buffer is in the unlocked state, the dual buffer switching signal will be toggled; if the current channel dual buffer is in the locked state, the channel dual buffer will be put into the suspended state. When a double buffer in a suspended state receives the unlock signal unlock_buffer_e for the channel, it will release from the suspended state and toggle the double buffer switching signal, while sending the ready flag for the channel number data to the host computer; when a double buffer in a suspended state receives the memory area request signal get_e for the channel, it will release from the suspended state.

[0011] (4) In S5, data packets with different label numbers will be stored in a pre-defined RAM storage area.

[0012] This invention provides a method for receiving and storing multi-packet serial data based on FPGA. It enables the reception of multiple data packets with different tags through a single serial data interface, and stores each packet according to its tag number in a specific double buffer for later retrieval. Compared with existing technologies, the advantages of this invention are: storing data packets with different tag numbers in specific buffers improves the efficiency of the host computer in reading specific data packets; and the double buffer mechanism improves the stability and reliability of data transmission and enhances the security of the data reading process. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of an apparatus for receiving and storing multi-packet serial data based on FPGA, provided in an embodiment of the present invention. Detailed Implementation

[0014] The present invention will now be described in further detail with reference to the accompanying drawings.

[0015] This invention provides an FPGA-based device for receiving and storing multi-packet serial data, such as... Figure 1 As shown, the device includes a serial data receiving and parsing module 1, a FIFO buffer module 2, an address decoding module 3, a multi-channel dual buffer control module 4, a data storage control module 5, and a RAM data storage area 6; The data output terminal of the serial data receiving and parsing module 1 is connected to the data input terminal of the FIFO buffer module 2, the address decoding module 3, and the multi-channel dual buffer control module 4; The data input terminal of FIFO buffer module 2 is connected to the data output terminal of serial data receiving and parsing module 1, and the data output terminal of FIFO buffer module 2 is connected to the data input terminal of data storage control module 5. The data input terminal of the address decoding module 3 is connected to the data output terminal of the serial data receiving and parsing module 1, and the data output terminal of the address decoding module 3 is connected to the input terminals of the multi-channel dual-buffer control module 4 and the data storage module 5. The data input terminal of the multi-channel dual-buffer control module 4 is connected to the serial data receiving and parsing module 1, the address decoding module 3, and the data output terminal of the host computer. The data output terminal of the multi-channel dual-buffer control module 4 is connected to the RAM data storage area 6 and the data input terminal of the host computer. The data input terminal of the data storage control module 5 is connected to the data output terminals of the FIFO cache module 2 and the address decoding module 3; the data output terminal of the data storage control module 5 is connected to the data input terminal of the RAM data storage area 6. The data input terminal of RAM data storage area 6 is connected to the data output terminals of multi-channel dual-buffer control module 4 and data storage control module 5, and the data output terminal of RAM data storage area 6 is connected to the data input terminal of the host computer.

[0016] This invention also provides a method for receiving and storing multi-packet serial data based on FPGA. The method is implemented using the receiving and storage device of technical solution one, and includes: S1, the serial data receiving and parsing module is used to convert the received serial data stream into parallel data, and to parse the parallel data into data packets, parse out the label number of the data packet, and send a storage area request signal get_e to the multi-channel dual buffer controller; after the data packet is received, it sends a data commit signal commit_e to the multi-channel dual buffer controller. S2, the FIFO cache module is used to cache the parsed parallel data; S3, the address decoding module decodes the write channel number write_id and the starting address of the corresponding RAM storage area based on the parsed data packet label; S4, the multi-channel dual-buffer controller controls the dual-buffer switching signal according to the state of the 6 input control signals; S5, the data storage control module stores the parallel data in the FIFO cache module into the double buffer storage area according to the address decoded by the address decoding module; In S1, the memory access request signal get_e will only be sent after a valid label number has been parsed. In S1, after the serial data receiving and parsing module 1 completes the reception of the current data packet, it needs to perform CRC verification. Only after the CRC verification is correct will it send the data commit signal commit_e. In S2, the FIFO caching module can cache parallel data before parsing the label number of the data packet; In S2, if the label number parsed by the serial data receiving and parsing module 1 is invalid, the data in the FIFO buffer module will be cleared. In S4, the multi-channel dual-buffer controller is controlled by 3 groups of 6 input control signals, including the current write channel number write_id, the current read channel number read_id, the lock signal lock_buffer_e, the unlock signal unlock_buffer_e, the memory area request signal get_e, and the data commit signal commit_e. In S4, before reading data, the host computer will send the read channel number and the lock signal lock_buffer_e to the multi-channel dual buffer controller; after reading data, it will send the read channel number and the unlock signal unlock_buffer_e to the multi-channel dual buffer controller. In S4, if the current read channel double buffer is in an unlocked state, the channel double buffer will switch to a locked state after receiving the lock signal lock_buffer_e; if the current channel double buffer is in a locked state, the channel double buffer will switch to an unlocked state after receiving the unlock signal unlock_buffer_e. In S4, when the write channel number and data commit signal commit_e are received; If the current channel double buffer is in an unlocked state, the double buffer switching signal is toggled, and a ready flag for data in that channel is sent to the host computer; if the current channel double buffer is in a locked state, the channel double buffer is put into a suspended state. In S4, when a suspended double buffer receives the unlock signal unlock_buffer_e for the channel, it will release from the suspended state and toggle the double buffer switching signal, while sending the ready flag for the channel number data to the host computer; when a suspended double buffer receives the memory area request signal get_e for the channel, it will release from the suspended state. In S5, data packets with a specific label number will be stored in RAM memory at a specific address.

[0017] Example 1 This invention provides a method for receiving and storing multi-packet serial data based on FPGA. The device includes a serial data receiving and parsing module 1, a FIFO buffer module 2, an address decoding module 3, a multi-channel dual buffer control module 4, a data storage control module 5, and a RAM data storage area 6.

[0018] The data output terminal of the serial data receiving and parsing module 1 is connected to the input terminals of the FIFO buffer module 2, the address decoding module 3, and the multi-region dual buffer controller 4; the data input terminal of the FIFO buffer module 2 is connected to 1, and the data output terminal is connected to 5; the data input terminal of the address decoding module 3 is connected to 1, and the data output terminal is connected to 5; the data input terminal of the multi-region dual buffer controller 4 is connected to 1, and the output terminal is connected to 6; the data input terminal of the data storage control module 5 is connected to 2 and 3, and the data output terminal is connected to 6; the data input terminal of the RAM data storage area 6 is connected to 4 and 5.

[0019] The serial data receiving and parsing module 1 is used to convert the received serial data into parallel data and parse the data packets to obtain the label of the data packets; FIFO buffer module 2 is used to buffer the parallel data in 1; in particular, if 1 parses the currently received data packet label number as invalid, the data in the FIFO buffer module is cleared. The address decoding module 3 decodes the channel number id and the starting address of the corresponding RAM storage area based on the parsed data packet label number; The multi-region dual-buffer controller 4 generates a data ready flag and controls the dual-buffer switching signal based on the current read / write channel number, write data commit request signal, and read data unlock / unlock signal. When the write channel number is fixed, the write data commit request signal only affects the data ready flag and dual-buffer switching signal of the current write channel. When the read channel is fixed, the read data unlock / unlock signal only affects the data ready flag and dual-buffer switching signal of the current read channel. When the write channel and read channel are the same channel, the write data commit request signal and the read data unlock / unlock signal jointly affect the data ready flag and dual-buffer switching signal of the current channel. The data storage control module 5, based on the storage start address decoded by the address decoding module 3 and the current double buffer switching signal, stores the parallel data in the FIFO cache module into the double buffer storage area 6. Example 2 This invention provides a method for receiving and storing multi-packet serial data based on FPGA, the method comprising: Step 1: The serial data receiving and parsing module 1 receives new serial data and completes the serial-to-parallel conversion and parsing of the data packet, including the packet header, packet length, and label number, etc. Step 2: Write the parallel data into FIFO buffer module 2; Step 3: The address decoding module 3 decodes the channel number id corresponding to the data packet and the starting address of the RAM storage area corresponding to the data packet based on the data packet label number parsed by the serial data receiving and parsing module 1. Step 4: After the serial data receiving and parsing module 1 parses the label number of the current data packet, if it is valid, it sends a storage area request signal get_e to the multi-area double buffer controller 4; the address decoding module 3 decodes the write data channel number write_id to the multi-area double buffer controller 4. Step 5: The multi-region dual-buffer controller 4 controls the dual-buffer switching signal based on the current input signal status. Step 5: The data storage control module 5, based on the storage start address decoded by the address decoding module 3 and the current double buffer switching signal, stores the parallel data in the FIFO cache module into the double buffer storage area 6. Step 6: After the serial data receiving and parsing module 1 completes the reception of the current data packet, it performs CRC verification. If the verification is correct, it sends a data commit signal commit_e to the multi-area dual buffer controller 4. The multi-area dual buffer controller 4 completes the control of the dual buffer switching signal according to the current input signal status and sends a data ready signal to the host computer. Step 7: After receiving the data ready signal, the host computer sends the read channel number to the multi-region dual buffer controller 4, and then sends the read data lock signal lock_e to the multi-region dual buffer controller 4; after the host computer finishes reading the data in the buffer, it sends the read data unlock signal unlock_e to the multi-region dual buffer controller 4 to release the space of the channel; the multi-region dual buffer controller 4 completes the control of the dual buffer switching signal according to the current input signal status.

[0020] The present invention provides a method for receiving and storing multi-packet serial data based on FPGA. It enables the reception of multiple data packets with different tags through a single serial data interface and stores them in specific double buffers according to their tag numbers for later reading, thereby improving the efficiency of the host computer in reading specific data packets. The double buffer mechanism improves the stability and reliability of data transmission and enhances the security of the data reading process.

Claims

1. A device for receiving and storing multi-packet serial data based on FPGA, characterized in that, The receiving and storage device includes: a serial data receiving and parsing module (1), a FIFO buffer module (2), an address decoding module (3), a multi-channel dual buffer control module (4), a data storage control module (5), and a RAM data storage area (6). The data output terminal of the serial data receiving and parsing module (1) is connected to the data input terminal of the FIFO buffer module (2), the address decoding module (3), and the multi-channel dual buffer control module (4); The data input terminal of the FIFO buffer module (2) is connected to the data output terminal of the serial data receiving and parsing module (1), and the data output terminal of the FIFO buffer module (2) is connected to the data input terminal of the data storage control module (5). The data input terminal of the address decoding module (3) is connected to the data output terminal of the serial data receiving and parsing module (1), and the data output terminal of the address decoding module (3) is connected to the input terminals of the multi-channel dual buffer control module (4) and the data storage control module (5). The data input terminal of the multi-channel dual buffer control module (4) is connected to the serial data receiving and parsing module (1), the address decoding module (3) and the data output terminal of the host computer. The data output terminal of the multi-channel dual buffer control module (4) is connected to the RAM data storage area (6) and the data input terminal of the host computer. The data input terminal of the data storage control module (5) is connected to the data output terminals of the FIFO cache module (2) and the address decoding module (3); the data output terminal of the data storage control module (5) is connected to the data input terminal of the RAM data storage area (6); The data input terminal of the RAM data storage area (6) is connected to the data output terminal of the multi-channel dual buffer control module (4) and the data storage control module (5), and the data output terminal of the RAM data storage area (6) is connected to the data input terminal of the host computer. The serial data receiving and parsing module (1) is used to convert the received serial data stream into parallel data, and to parse the parallel data into data packets, parse out the label number of the data packet, and send a storage area request signal get_e to the multi-channel dual buffer control module; after the data packet is received, it is also used to send a data commit signal commit_e to the multi-channel dual buffer control module. FIFO cache module (2) is used to cache the parsed parallel data; The address decoding module (3) is used to decode the write channel number write_id and the starting address of the corresponding RAM storage area based on the parsed data packet label number; The multi-channel dual-buffer control module (4) is used to control the dual-buffer switching signal according to the state of the control signal; The data storage control module (5) is used to store the parallel data in the FIFO cache module into the double buffer storage area according to the storage address decoded by the address decoding module; data packets with different label numbers will be stored in the pre-defined RAM storage area; RAM data storage area (6) is used to store the received data.

2. A method for receiving and storing multi-packet serial data based on FPGA, implemented using the device as described in claim 1, characterized in that, The method includes: S1, the serial data receiving and parsing module (1) converts the received serial data stream into parallel data, performs data packet parsing on the parallel data, parses out the label number of the data packet, and sends a storage area request signal get_e to the multi-channel dual buffer control module; after the data packet is received, it is also used to send a data commit signal commit_e to the multi-channel dual buffer control module. S2, the FIFO cache module (2) caches the parsed parallel data; S3, the address decoding module (3) decodes the write channel number write_id and the starting address of the corresponding RAM storage area based on the parsed data packet label number; S4, the multi-channel dual buffer control module (4) controls the dual buffer switching signal according to the state of the control signal; the control signal includes: the memory area request signal get_e and the data commit signal commit_e from the serial data receiving and parsing module (1), the write channel number write_id from the address decoding module (3), the read channel number read_id from the host computer, the lock signal lock_buffer_e, and the unlock signal unlock_buffer_e; S5, the data storage control module (5) stores the parallel data in the FIFO cache module into the double buffer storage area according to the storage address decoded by the address decoding module; in S5, data packets with different label numbers will be stored in the pre-defined RAM storage area; S6, RAM data storage area (6) stores the received data.

3. The method for receiving and storing multi-packet serial data based on FPGA according to claim 2, characterized in that, In S1, the serial data receiving and parsing module (1) will send the memory area request signal get_e only after parsing a valid label number. After the serial data receiving and parsing module (1) completes the reception of the current data packet, it performs CRC verification. Only after the CRC verification is correct will it send the data commit signal commit_e.

4. The method for receiving and storing multi-packet serial data based on FPGA according to claim 3, characterized in that, In S2, the FIFO buffer module buffers parallel data before parsing the label number of the data packet. If the label number parsed by the serial data receiving and parsing module (1) is invalid, the data in the FIFO buffer module is cleared.

5. The method for receiving and storing multi-packet serial data based on FPGA according to claim 2, characterized in that, In S4, When the multi-channel dual-buffer control module (4) receives the write channel number write_id and the data commit signal commit_e, it sends the data ready flag for that channel to the host computer. After receiving the data ready flag, the host computer will send the read channel number read_id and the lock signal lock_buffer_e to the multi-channel dual buffer control module before reading the data; after reading the data, it will send the read channel number read_id and the unlock signal unlock_buffer_e to the multi-channel dual buffer control module. If the current channel double buffer is in an unlocked state, upon receiving the lock_buffer_e signal, the channel double buffer will switch to a locked state; if the current channel double buffer is in a locked state, upon receiving the unlock_buffer_e signal, the data ready flag will be reset, and the channel double buffer will switch to an unlocked state. When the multi-channel dual buffer control module (4) receives the write channel number write_id and the data commit signal commit_e again, if the current channel dual buffer is in the unlocked state, the dual buffer switching signal will be flipped. At the same time, if the current channel dual buffer is in the locked state, the channel dual buffer will be in the suspended state. When a double buffer in a suspended state receives the unlock signal unlock_buffer_e for the channel, it will release from the suspended state and toggle the double buffer switching signal, while sending the data ready flag for the channel to the host computer; when a double buffer in a suspended state receives the memory area request signal get_e for the channel, it will release from the suspended state.

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