An integrated capacitor and a method of manufacturing the same

Abstract

The application provides an integrated capacitor and a preparation method thereof. The integrated capacitor comprises a substrate, a dielectric layer, a lower plate layer, a first dielectric layer, a second dielectric layer, a contact hole, a solder pad and an upper plate layer. The dielectric layer covers the upper surface of the substrate. The lower plate layer is located on the upper surface of the dielectric layer, and the length of the lower plate layer in the X direction is less than the length of the dielectric layer. The first dielectric layer covers the exposed surface of the lower plate layer. The second dielectric layer covers the upper surface of the first dielectric layer. The contact hole is located in the second dielectric layer above the lower plate layer and has a bottom surface exposing the lower plate layer. The solder pad covers the inner wall and bottom surface of the contact hole and is electrically connected with the lower plate layer. The upper plate layer is located on the upper surface of the second dielectric layer above the lower plate layer, and the upper plate layer is spaced apart from the solder pad. The first dielectric layer covering the lower plate layer is formed at low temperature, and then the second dielectric layer of high-temperature process is formed, so that the effective area change of the lower plate layer caused by the pollution of the furnace tube is avoided, and the frequency and cost of maintaining the furnace tube are reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to an integrated capacitor and its preparation method. Background Technology

[0002] With the development of integrated circuit manufacturing technology, the integration level of integrated circuits is getting higher and higher, and the size of electronic components in integrated circuits is getting smaller and smaller. The requirements for each electronic device in integrated circuits are getting higher and higher. As a commonly used component in integrated circuits, the size of integrated capacitors has a significant impact on their breakdown voltage.

[0003] Integrated capacitors used in integrated circuits typically consist of a lower electrode layer and SiN. x The capacitor consists of a dielectric layer and an upper electrode layer, such as... Figure 1 The diagram shown is a cross-sectional view of an integrated capacitor, including a substrate 01, a dielectric layer 02, a lower electrode layer 03, a capacitor dielectric layer 04, a solder pad 05, and an upper electrode layer 06. Due to SiN... x SiN2 has a high dielectric constant, a mature fabrication process, and low manufacturing cost, making it a commonly used dielectric layer material for capacitors. High-temperature formed SiN2... x The dielectric layer of a capacitor can achieve a breakdown voltage field strength of up to 15 MV / cm, but high-temperature SiN formation is required. x Simultaneous melting and partial vaporization of the capacitor dielectric layer causes furnace tube contamination and changes in the effective electrode area of ​​the lower electrode layer, thus affecting the device's breakdown resistance.

[0004] Therefore, there is an urgent need to find a method for preparing integrated capacitors that can form the capacitor dielectric layer at high temperatures while avoiding furnace tube contamination and melting of the lower electrode layer. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an integrated capacitor and its preparation method, which solves the problems of furnace tube contamination and changes in the effective plate area of ​​the lower plate layer caused by the high-temperature process of forming the capacitor dielectric layer in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for manufacturing an integrated capacitor, comprising the following steps:

[0007] A substrate is provided, and a dielectric layer is formed on the upper surface of the substrate;

[0008] A lower electrode layer of a predetermined thickness is formed on the upper surface of the dielectric layer, wherein the length of the lower electrode layer in the X direction is less than the length of the dielectric layer in the X direction;

[0009] A first dielectric layer is formed covering the exposed surface of the lower electrode layer and the exposed upper surface of the dielectric layer. A second dielectric layer is formed on the upper surface of the first dielectric layer. The first dielectric layer is formed by a low-temperature process not exceeding 350°C, and the second dielectric layer is formed by a high-temperature process not lower than 650°C.

[0010] A contact hole is formed in the second dielectric layer above the lower electrode layer, the contact hole penetrating the second dielectric layer and the first dielectric layer to expose the upper surface of the lower electrode layer;

[0011] A solder pad is formed to cover the inner wall and bottom surface of the contact hole and to be electrically connected to the lower electrode layer. An upper electrode layer is formed on the upper surface of the second dielectric layer above the lower electrode layer. The upper electrode layer and the solder pad are spaced apart by a predetermined distance.

[0012] Optionally, the method for forming the first dielectric layer includes plasma-enhanced chemical vapor deposition; the method for forming the second dielectric layer includes low-pressure chemical vapor deposition.

[0013] Optionally, after forming the first dielectric layer and before forming the second dielectric layer, the method further includes a step of planarizing the upper surface of the first dielectric layer.

[0014] Optionally, the material of the first dielectric layer includes SiN. x The material of the second dielectric layer includes SiN x .

[0015] Optionally, the temperature range for forming the second dielectric layer is 700°C to 900°C.

[0016] Optionally, the process may further include forming an insulating dielectric layer before forming the solder pad and the upper electrode layer.

[0017] Optionally, the material of the insulating medium layer includes one of polyimide and silicon dioxide.

[0018] Optionally, the insulating medium layer covers the upper surface of the second medium layer, and the insulating medium layer has a first opening and a second opening spaced apart. The first opening is located in the insulating medium layer above the contact hole and communicates with the contact hole. The second opening is located in the insulating medium layer above the lower electrode layer, and the bottom surface of the second opening exposes the upper surface of the second medium layer above the lower electrode layer.

[0019] Optionally, the upper electrode layer is formed using an air bridge process.

[0020] The present invention also provides an integrated capacitor, comprising:

[0021] Substrate;

[0022] A dielectric layer covering the upper surface of the substrate;

[0023] The lower electrode layer is located on the upper surface of the dielectric layer, and the length of the lower electrode layer in the X direction is less than the length of the dielectric layer in the X direction.

[0024] A first dielectric layer covers the exposed surface of the lower electrode layer and the upper surface of the dielectric layer. The first dielectric layer is formed using a low-temperature process with a temperature not exceeding 350°C.

[0025] The second dielectric layer covers the upper surface of the first dielectric layer, and the second dielectric layer is formed using a high-temperature process of not less than 650°C;

[0026] A contact hole is located in the second dielectric layer above the lower electrode layer. The contact hole penetrates the second dielectric layer and the first dielectric layer to expose the upper surface of the lower electrode layer.

[0027] The upper electrode layer includes a solder pad and an upper electrode layer. The solder pad covers the inner wall and bottom surface of the contact hole and is electrically connected to the lower electrode layer. The upper electrode layer is located on the upper surface of the second dielectric layer above the lower electrode layer. The upper electrode layer and the solder pad are spaced apart by a preset distance.

[0028] As described above, the integrated capacitor and its fabrication method of the present invention form a first dielectric layer covering the exposed surface of the lower electrode layer before forming the high-temperature second dielectric layer, and use a low-temperature process to form the first dielectric layer. This prevents the lower electrode layer from vaporizing and causing furnace tube contamination during the formation of the first dielectric layer, and also avoids the lower electrode layer from melting and affecting its conductivity. The material of the first dielectric layer is the same as that of the second dielectric layer. The first dielectric layer covers the lower electrode layer to avoid furnace tube contamination and changes in the effective electrode area of ​​the lower electrode layer caused by the high-temperature process of forming the second dielectric layer, thus ensuring the breakdown voltage of the device and reducing the frequency of furnace tube maintenance for forming the second dielectric layer, thereby reducing maintenance costs. In addition, an isolation dielectric layer including the first opening and the second opening is formed on the upper surface of the second dielectric layer, and the upper electrode layer is formed on the bottom surface of the second opening, or the upper electrode layer is formed using an air bridge process. This prevents premature edge breakdown of the integrated capacitor's electrode edges, ensuring the withstand voltage of the integrated capacitor and possessing high industrial application value. Attached Figure Description

[0029] Figure 1 The diagram shows a cross-sectional view of an integrated capacitor.

[0030] Figure 2The diagram shows the process flow charts for the fabrication methods of the integrated capacitors in Embodiments 1 and 2 of the present invention.

[0031] Figure 3 The diagram shows a cross-sectional view of the integrated capacitor fabrication method according to Embodiments 1 and 2 of the present invention after the dielectric layer is formed.

[0032] Figure 4 The diagram shows a cross-sectional structure after the lower electrode layer is formed, illustrating the fabrication method of the integrated capacitor according to Embodiments 1 and 2 of the present invention.

[0033] Figure 5 The diagram shows a cross-sectional structure after the formation of the first dielectric layer in the method for fabricating the integrated capacitor according to Embodiments 1 and 2 of the present invention.

[0034] Figure 6 The diagram shows a cross-sectional structure after the formation of the second dielectric layer in the method for fabricating the integrated capacitor according to Embodiments 1 and 2 of the present invention.

[0035] Figure 7 The diagram shows a cross-sectional structure after the contact hole is formed in the method for fabricating the integrated capacitor according to Embodiments 1 and 2 of the present invention.

[0036] Figure 8 The diagram shows a cross-sectional view of the integrated capacitor fabrication method according to Embodiments 1 and 2 of the present invention after forming the first and second openings.

[0037] Figure 9 The diagram shows a cross-sectional structure of the integrated capacitor fabrication method according to Embodiment 1 of the present invention after the upper electrode layer is formed on the bottom surface of the second opening.

[0038] Figure 10 The diagram shown is a cross-sectional view of the integrated capacitor fabrication method according to Embodiment 2 of the present invention after the formation of the bottom conductive layer.

[0039] Figure 11 The diagram shows a cross-sectional view of the integrated capacitor fabrication method according to Embodiment 2 of the present invention after the formation of the conductive pillar.

[0040] Figure 12 The diagram shown is a cross-sectional view of the integrated capacitor fabrication method according to Embodiment 2 of the present invention after the formation of the top conductive layer.

[0041] Figure 13 The diagram shows a cross-sectional structure after removing the first and second shielding layers in the method for fabricating an integrated capacitor according to Embodiment 2 of the present invention.

[0042] Explanation of icon numbers

[0043] 01 Substrate

[0044] 02 Dielectric layer

[0045] 03 Lower electrode layer

[0046] 04 Capacitor Dielectric Layer

[0047] 05 Solder pad

[0048] 06 Upper electrode layer

[0049] 1 Substrate

[0050] 2 Dielectric layer

[0051] 3 Lower electrode layer

[0052] 4 First dielectric layer

[0053] 5 Second dielectric layer

[0054] 51 Contact Hole

[0055] 6 solder pads

[0056] 7 Upper electrode layer

[0057] 71 Bottom Conductive Layer

[0058] 72 Conductive support

[0059] 73 Top conductive layer

[0060] 74 First Shielding Layer

[0061] 741 Third Opening

[0062] 75 Second Shielding Layer

[0063] 751 Fourth Opening

[0064] 8. Isolation medium layer

[0065] 81 First Opening

[0066] 82 Second opening Detailed Implementation

[0067] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0068] Please see Figures 2 to 13It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] Example 1

[0070] This embodiment provides a method for manufacturing an integrated capacitor, such as... Figure 2-9 The diagram shown is a process flow chart of the fabrication method of the integrated capacitor, including the following steps:

[0071] S1: A substrate 1 is provided, and a dielectric layer 2 is formed on the upper surface of the substrate 1;

[0072] Specifically, such as Figure 3 The diagram shown is a cross-sectional view of the dielectric layer 2 after its formation. The dielectric layer 2 is made of silicon nitride, silicon oxide, or other suitable dielectric materials. In this embodiment, SiN is used. x The layer serves as the dielectric layer 2.

[0073] Specifically, the substrate 1 is used to provide a process platform for forming an integrated capacitor, and the material of the substrate 1 includes silicon, silicon germanium, germanium, silicon carbide, or other suitable materials.

[0074] Specifically, the method for forming the dielectric layer 2 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0075] S2: A lower electrode layer 3 of a predetermined thickness is formed on the upper surface of the dielectric layer 2, wherein the length of the lower electrode layer 3 in the X direction is less than the length of the dielectric layer 2 in the X direction.

[0076] Specifically, such as Figure 4 The diagram shows a cross-sectional view of the lower electrode layer 3 after its formation. The material of the lower electrode layer 3 includes one of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, and heavily doped polycrystalline silicon, or other suitable conductive materials. In this embodiment, a titanium thin film layer is used as the lower electrode layer 3. Because titanium has a high melting point (approximately 1668°C), furnace tube contamination is avoided during the formation of the first dielectric layer 4.

[0077] Specifically, the methods for forming the lower electrode layer 3 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, evaporation, electroplating, electroless plating, or other suitable methods.

[0078] S3: Form a first dielectric layer 4 covering the exposed surface of the lower electrode layer 3 and the exposed upper surface of the dielectric layer 2, and form a second dielectric layer 5 on the upper surface of the first dielectric layer 4. The first dielectric layer 4 is formed by a low-temperature process not exceeding 350°C, and the second dielectric layer 5 is formed by a high-temperature process not lower than 650°C.

[0079] As an example, such as Figure 5 The diagram shown is a cross-sectional view of the structure after the formation of the first dielectric layer 4. The method for forming the first dielectric layer 4 includes plasma-enhanced chemical vapor deposition (PECVD) or other suitable low-temperature deposition processes. In this embodiment, the first dielectric layer 4 is formed using a low-temperature deposition process with PECVD.

[0080] Specifically, the first dielectric layer 4 is formed using a low-temperature deposition process not exceeding 350°C to prevent the material of the lower electrode layer 3 from partially vaporizing at higher temperatures during the formation of the first dielectric layer 4, thus contaminating the furnace tube.

[0081] Specifically, the material of the first dielectric layer 4 includes SiN. x Or other suitable dielectric materials with low dielectric constants. In this embodiment, SiN is formed using a low-temperature process. x As the first dielectric layer 4, and due to the SiN formed under low-temperature process x The thin film has a low dielectric constant and is formed only using low-temperature SiN processes. x Thin films are used as the dielectric layer of integrated capacitors. However, integrated capacitors have a low breakdown field strength (approximately 10 MV / cm), making them unsuitable for fabricating high-voltage integrated capacitors.

[0082] As an example, after the first dielectric layer 4 is formed and before the second dielectric layer 5 is formed, the method further includes a step of planarizing the upper surface of the first dielectric layer 4.

[0083] Specifically, the upper surface of the first dielectric layer 4 is planarized to reduce defects on the surface of the first dielectric layer 4, making the surface of the first dielectric layer 4 smooth and facilitating the subsequent formation of the second dielectric layer 5.

[0084] Specifically, the method for planarizing the upper surface of the first dielectric layer 4 includes chemical mechanical polishing (CMP) or other suitable planarization methods.

[0085] As an example, such as Figure 6 The diagram shown is a cross-sectional view of the structure after the formation of the second dielectric layer 5. The method for forming the second dielectric layer 5 includes low-pressure chemical vapor deposition or other suitable methods. In this embodiment, low-pressure chemical vapor deposition in a high-temperature deposition process is used to form the second dielectric layer 5.

[0086] As an example, the temperature range for forming the second dielectric layer 5 is 700°C to 900°C. In this embodiment, the second dielectric layer 5 is formed at a high temperature of 800°C.

[0087] Specifically, the second dielectric layer 5 formed by low-pressure chemical vapor deposition in a high-temperature environment has better dielectric properties.

[0088] As an example, the material of the second dielectric layer 5 includes SiN. x Or other suitable high-dielectric materials. In this embodiment, SiN with high dielectric properties formed under high-temperature conditions is used. x This serves as the second dielectric layer 5.

[0089] Specifically, by using the second dielectric layer 5 formed by low-pressure chemical vapor deposition under high temperature environment as the capacitor dielectric layer of the integrated capacitor, the breakdown field strength of the integrated capacitor can reach 15MV / cm, which is convenient for manufacturing high-voltage integrated capacitors.

[0090] Specifically, since the first dielectric layer 4 covers the exposed surface of the lower electrode layer 3, the first dielectric layer 4 and the dielectric layer 2 together wrap the lower electrode layer 3. This prevents the lower electrode layer 3 from melting and deforming due to temperature during the formation of the second dielectric layer 5 at high temperatures, which would cause changes in the effective area of ​​the lower electrode layer 3 and affect the performance of the device. At the same time, it prevents the lower electrode layer 3 from partially vaporizing, which would contaminate the furnace tube used to form the second dielectric layer 5. This reduces the maintenance frequency of the furnace tube used to form the second dielectric layer 5, saves maintenance costs, and avoids the problem of contamination of the process furnace tube affecting the quality of subsequent batch deposition of the second dielectric layer 5, thus ensuring the quality of the formed second dielectric layer 5.

[0091] S4: A contact hole 51 is formed in the second dielectric layer 5 above the lower electrode layer 3. The contact hole 51 penetrates the second dielectric layer 5 and the first dielectric layer 4 to expose the upper surface of the lower electrode layer 3.

[0092] Specifically, such as Figure 7 The diagram shows a cross-sectional view of the contact hole 51 after its formation. The methods for forming the contact hole 51 include dry etching, wet etching, or other suitable etching methods. In this embodiment, to obtain a better hole shape, plasma etching (a type of dry etching) is used to form the contact hole 51.

[0093] Specifically, while ensuring device performance, the opening size of the contact hole 51 can be selected according to the actual situation, and is not limited here.

[0094] S5: Form a pad 6 that covers the inner wall and bottom surface of the contact hole 51 and is electrically connected to the lower electrode layer 3; form an upper electrode layer 7 on the upper surface of the second dielectric layer 5 above the lower electrode layer 3; the upper electrode layer 7 and the pad 6 are spaced apart by a preset distance.

[0095] As a preferred option, the step of forming an isolation dielectric layer 8 is included before forming the solder pad 6 and the upper electrode layer 7.

[0096] Specifically, such as Figure 8 The diagram shows a cross-sectional view of the structure after the formation of the first opening 81 and the second opening 82. The insulating medium layer 8 covers the upper surface of the second medium layer 5. The insulating medium layer 8 has a first opening 81 and a second opening 82 spaced apart. The first opening 81 is located in the insulating medium layer 8 above the contact hole 51 and is connected to the contact hole 51. The second opening 82 is located in the insulating medium layer 8 above the lower electrode layer 3, and the bottom surface of the second opening 82 exposes the upper surface of the second medium layer 5 above the lower electrode layer 3.

[0097] Specifically, the method for forming the isolation medium layer 8 includes spin coating, physical vapor deposition, chemical vapor deposition, or other suitable methods.

[0098] As an example, the material of the insulating dielectric layer 8 includes polyimide (also known as PI) and silicon dioxide, or other suitable dielectric materials. In this embodiment, the PI layer is formed by spin coating and serves as the insulating dielectric layer 8.

[0099] Specifically, while ensuring device performance, the thickness of the isolation dielectric layer 8 can be selected according to the actual situation, and is not limited here.

[0100] Specifically, the method for forming the first opening 81 includes dry etching, wet etching, or other suitable methods; the method for forming the second opening 82 includes dry etching, wet etching, or other suitable methods.

[0101] Specifically, such as Figure 9 The diagram shows a cross-sectional view of the structure after the solder pad 6 and the upper electrode layer 7 are formed. The solder pad 6 covers the inner wall and bottom surface of the contact hole 51, the side wall of the first opening 81, and is electrically connected to the lower electrode layer 3. The upper electrode layer 7 is located on the upper surface of the second dielectric layer 5 (i.e., the bottom surface of the second opening 82) above the lower electrode layer 3.

[0102] Specifically, the methods for forming the solder pad 6 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, evaporation, electroplating, electroless plating, or other suitable methods. In this embodiment, the solder pad 6 is formed by evaporation.

[0103] Specifically, the material of the bonding pad 6 includes one of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, and heavily doped polycrystalline silicon, or other suitable conductive materials.

[0104] Specifically, the solder pad 6 also covers the upper surface of the second dielectric layer 5 surrounding the contact hole 51.

[0105] Specifically, while ensuring the withstand voltage of the device, the distance that the edge of the pad 6 extends from the opening edge of the contact hole 51 in the X direction toward the negative X direction and the X direction can be selected according to the actual situation, and is not limited here.

[0106] Specifically, the methods for forming the upper electrode layer 7 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, evaporation, electroplating, electroless plating, or other suitable methods. In this embodiment, evaporation is used to simultaneously form the upper electrode layer 7 and the bonding pad 6.

[0107] Specifically, the upper electrode layer 7 covers the bottom surface of the second opening 82 to form a capacitor together with the lower electrode layer 3 and the first dielectric layer 4 and the second dielectric layer 5 above the lower electrode layer 3.

[0108] Specifically, the upper electrode layer 7 extends along the X direction on the side away from the solder pad 6, and the upper electrode layer 7 covers the inner wall of the second opening 82 away from the solder pad 6 and the upper surface of the second dielectric layer 5 around the second opening 82. While ensuring device performance, the distance of the upper electrode layer 7 extending along the X direction on the side away from the solder pad 6 can be selected according to the actual situation, and is not limited here.

[0109] Specifically, the solder pad 6 and the upper electrode layer 7 serve as the two electrodes of the integrated capacitor and are electrically connected to the external circuit, respectively.

[0110] Specifically, the isolation dielectric layer 8 is used as the isolation layer, and the upper electrode layer 7 is formed in the second opening in the isolation dielectric layer. The electrode of the integrated capacitor is formed by this isolation process, which avoids premature breakdown at the edge of the integrated capacitor and ensures the withstand voltage value of the capacitor.

[0111] The integrated capacitor fabrication method of this embodiment involves forming a first dielectric layer 4 with a low dielectric constant using a low-temperature process after forming the lower electrode layer 3. This avoids partial vaporization of the lower electrode layer 3 due to high temperatures during the formation of the first dielectric layer 4, which would contaminate the furnace tube used for forming the first dielectric layer 4. It also prevents the lower electrode layer 3 from melting and deforming due to temperature, thus avoiding changes in its effective area. After forming the first dielectric layer 4 covering the exposed surface of the lower electrode layer 3, a second dielectric layer 5 with a high dielectric constant is formed using a high-temperature process. The high-temperature formation of the second dielectric layer increases the breakdown voltage field strength of the device. Due to the protection of the first dielectric layer 4, the lower electrode layer 3 is prevented from deforming and vaporizing at high temperatures, thus avoiding contamination of the furnace tube used for forming the second dielectric layer 3. Simultaneously, the effective electrode area of ​​the lower electrode layer 3 remains unchanged, improving the withstand voltage of the integrated capacitor. The process is simple, reducing the frequency of furnace tube maintenance and lowering maintenance costs. Furthermore, the upper electrode layer 7 employs an isolation process to prevent premature breakdown at the edges of the integrated capacitor, ensuring its withstand voltage.

[0112] Example 2

[0113] This embodiment provides a method for manufacturing an integrated capacitor, such as... Figure 2-8 Figures 10-13 show a process flow diagram of the fabrication method of the integrated capacitor, which includes the following steps:

[0114] S1: A substrate 1 is provided, and a dielectric layer 2 is formed on the upper surface of the substrate 1;

[0115] Specifically, such as Figure 3 The diagram shown is a cross-sectional view of the dielectric layer 2 after its formation. The dielectric layer 2 is made of silicon nitride, silicon oxide, or other suitable dielectric materials. In this embodiment, SiN is used. x The layer serves as the dielectric layer 2.

[0116] Specifically, the substrate 1 is used to provide a process platform for forming an integrated capacitor, and the material of the substrate 1 includes silicon, silicon germanium, germanium, silicon carbide, or other suitable materials.

[0117] Specifically, the method for forming the dielectric layer 2 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0118] S2: A lower electrode layer 3 of a predetermined thickness is formed on the upper surface of the dielectric layer 2, wherein the length of the lower electrode layer 3 in the X direction is less than the length of the dielectric layer 2 in the X direction.

[0119] Specifically, such as Figure 4The diagram shows a cross-sectional view of the lower electrode layer 3 after its formation. The material of the lower electrode layer 3 includes one of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, and heavily doped polycrystalline silicon, or other suitable conductive materials. In this embodiment, a titanium thin film layer is used as the lower electrode layer 3. Because titanium has a high melting point (approximately 1668°C), furnace tube contamination is avoided during the formation of the first dielectric layer 4.

[0120] Specifically, the methods for forming the lower electrode layer 3 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, evaporation, electroplating, electroless plating, or other suitable methods.

[0121] S3: Form a first dielectric layer 4 covering the exposed surface of the lower electrode layer 3 and the exposed upper surface of the dielectric layer 2, and form a second dielectric layer 5 on the upper surface of the first dielectric layer 4. The first dielectric layer 4 is formed by a low-temperature process not exceeding 350°C, and the second dielectric layer 5 is formed by a high-temperature process not lower than 650°C.

[0122] As an example, such as Figure 5 The diagram shown is a cross-sectional view of the structure after the formation of the first dielectric layer 4. The method for forming the first dielectric layer 4 includes plasma-enhanced chemical vapor deposition (PECVD) or other suitable low-temperature deposition processes. In this embodiment, the first dielectric layer 4 is formed using a low-temperature deposition process with PECVD.

[0123] Specifically, the first dielectric layer 4 is formed using a low-temperature deposition process not exceeding 350°C to prevent the material of the lower electrode layer 3 from partially vaporizing at higher temperatures during the formation of the first dielectric layer 4, thus contaminating the furnace tube.

[0124] Specifically, the material of the first dielectric layer 4 includes SiN. x Or other suitable dielectric materials with low dielectric constants. In this embodiment, SiN is formed using a low-temperature process. x As the first dielectric layer 4, and due to the SiN formed under low-temperature process x The thin film has a low dielectric constant and is formed only using low-temperature SiN processes. x Thin films are used as the dielectric layer of integrated capacitors. However, integrated capacitors have a low breakdown field strength (approximately 10 MV / cm), making them unsuitable for fabricating high-voltage integrated capacitors.

[0125] As an example, after the first dielectric layer 4 is formed and before the second dielectric layer 5 is formed, the method further includes a step of planarizing the upper surface of the first dielectric layer 4.

[0126] Specifically, the upper surface of the first dielectric layer 4 is planarized to reduce defects on the surface of the first dielectric layer 4, making the surface of the first dielectric layer 4 smooth and facilitating the subsequent formation of the second dielectric layer 5.

[0127] Specifically, the method for planarizing the upper surface of the first dielectric layer 4 includes chemical mechanical polishing (CMP) or other suitable planarization methods.

[0128] As an example, such as Figure 6 The diagram shown is a cross-sectional view of the structure after the formation of the second dielectric layer 5. The method for forming the second dielectric layer 5 includes low-pressure chemical vapor deposition or other suitable methods. In this embodiment, low-pressure chemical vapor deposition in a high-temperature deposition process is used to form the second dielectric layer 5.

[0129] As an example, the temperature range for forming the second dielectric layer 5 is 700°C to 900°C. In this embodiment, the second dielectric layer 5 is formed at a high temperature of 800°C.

[0130] Specifically, the second dielectric layer 5 formed by low-pressure chemical vapor deposition in a high-temperature environment has better dielectric properties.

[0131] As an example, the material of the second dielectric layer 5 includes SiN. x Or other suitable high-dielectric materials. In this embodiment, SiN with high dielectric properties formed under high-temperature conditions is used. x This serves as the second dielectric layer 5.

[0132] Specifically, by using the second dielectric layer 5 formed by low-pressure chemical vapor deposition under high temperature environment as the capacitor dielectric layer of the integrated capacitor, the breakdown field strength of the integrated capacitor can reach 15MV / cm, which is convenient for manufacturing high-voltage integrated capacitors.

[0133] Specifically, since the first dielectric layer 4 covers the exposed surface of the lower electrode layer 3, the first dielectric layer 4 and the dielectric layer 2 together wrap the lower electrode layer 3. This prevents the lower electrode layer 3 from melting and deforming due to temperature during the formation of the second dielectric layer 5 at high temperatures, which would cause changes in the effective area of ​​the lower electrode layer 3 and affect the performance of the device. At the same time, it prevents the lower electrode layer 3 from partially vaporizing, which would contaminate the furnace tube used to form the second dielectric layer 5. This reduces the maintenance frequency of the furnace tube used to form the second dielectric layer 5, saves maintenance costs, and avoids the problem of contamination of the process furnace tube affecting the quality of subsequent batch deposition of the second dielectric layer 5, thus ensuring the quality of the formed second dielectric layer 5.

[0134] S4: A contact hole 51 is formed in the second dielectric layer 5 above the lower electrode layer 3. The contact hole 51 penetrates the second dielectric layer 5 and the first dielectric layer 4 to expose the upper surface of the lower electrode layer 3.

[0135] Specifically, such as Figure 7 The diagram shows a cross-sectional view of the contact hole 51 after its formation. The methods for forming the contact hole 51 include dry etching, wet etching, or other suitable etching methods. In this embodiment, to obtain a better hole shape, plasma etching (a type of dry etching) is used to form the contact hole 51.

[0136] Specifically, while ensuring device performance, the opening size of the contact hole 51 can be selected according to the actual situation, and is not limited here.

[0137] S5: Form a pad 6 that covers the inner wall and bottom surface of the contact hole 51 and is electrically connected to the lower electrode layer 3; form an upper electrode layer 7 on the upper surface of the second dielectric layer 5 above the lower electrode layer 3; the upper electrode layer 7 and the pad 6 are spaced apart by a preset distance.

[0138] As an example, the upper electrode layer 7 is formed using an air bridge process to prevent premature breakdown at the electrode edges of the integrated capacitor.

[0139] Specifically, the upper electrode layer 7 formed by the air bridge process includes multiple bottom conductive layers 71, multiple conductive pillars 72, and a top conductive layer 73. The bottom conductive layers 71 are located on the upper surface of the second dielectric layer 5, and at least one bottom conductive layer 71 is located above the lower electrode layer 3. The bottom end of one conductive pillar 72 is in contact with the upper surface of one bottom conductive layer 71, and the top end of each conductive pillar 72 is electrically connected to the top conductive layer 73.

[0140] Specifically, such as Figure 10 , Figure 11 , Figure 12 and Figure 13The figures shown are cross-sectional structural diagrams after the formation of the bottom conductive layer 71, the formation of the conductive pillar 72, and the formation of the top conductive layer 73, respectively. The formation of the upper electrode layer 7 using an air process includes the following steps: forming a patterned first shielding layer 74 on the upper surface of the second dielectric layer 5 to obtain a plurality of third openings 741 that expose the upper surface of the second dielectric layer 5; forming a bottom conductive layer 71 that fills the third openings 741; forming a second shielding layer 75 that covers the first shielding layer 74 and the upper surface of the bottom conductive layer 71, and patterning the second shielding layer 75 to obtain a fourth opening 751 whose bottom surface exposes the upper surface of the bottom conductive layer 71, forming a conductive pillar 72 that fills the fourth opening 751; forming a top conductive layer 73 on the upper surface of the second shielding layer 75, with the bottom surface of the top conductive layer 73 in contact with the top surface of the conductive pillar 72. In this embodiment, the bottom conductive layer 71, the conductive pillar 72, and the top conductive layer 73 are formed sequentially by vapor deposition.

[0141] Specifically, the material of the first masking layer 74 includes photoresist or other suitable masking materials; the material of the second masking layer 75 includes photoresist or other suitable masking materials.

[0142] Specifically, the bonding pads 6 can be formed simultaneously with the formation of the underlying conductive layer 71 to simplify the process steps and reduce manufacturing costs.

[0143] Specifically, such as Figure 13 The diagram shown is a cross-sectional view of the structure after removing the first shielding layer 74 and the second shielding layer 75. After the upper electrode layer 7 is formed using the air bridge process, the method further includes the step of removing the first shielding layer 74 and the second shielding layer 75 to release the upper electrode layer 7, which has a bridge-shaped cross-section.

[0144] Specifically, since the isolation dielectric layer 8, including the first opening 81 and the second opening 82, is formed on the upper surface of the second dielectric layer 5, and the upper electrode layer 7, which is spaced at a preset distance from the solder pad 6, is formed using an air bridge process, the edge of the integrated capacitor is prevented from breaking down prematurely, thus ensuring the withstand voltage of the capacitor.

[0145] The integrated capacitor fabrication method of this embodiment involves forming a first dielectric layer 4 with a low dielectric constant using a low-temperature process after forming the lower electrode layer 3. This avoids partial vaporization of the lower electrode layer 3 due to high temperatures during the formation of the first dielectric layer 4, which would contaminate the furnace tube used for forming the first dielectric layer 4. It also prevents the lower electrode layer 3 from melting and deforming due to temperature, thus avoiding changes in its effective area. After forming the first dielectric layer 4 covering the exposed surface of the lower electrode layer 3, a second dielectric layer 5 with a high dielectric constant is formed using a high-temperature process. The high-temperature formation of the second dielectric layer increases the breakdown voltage field strength of the device. Due to the protection of the first dielectric layer 4, the lower electrode layer 3 is prevented from deforming and vaporizing at high temperatures, thus avoiding contamination of the furnace tube used for forming the second dielectric layer 3. Simultaneously, the effective electrode area of ​​the lower electrode layer 3 remains unchanged, improving the withstand voltage of the integrated capacitor. The process is simple, reducing the frequency of furnace tube maintenance and lowering maintenance costs. Furthermore, the upper electrode layer 7 uses an air-bridge process to prevent premature breakdown at the edges of the integrated capacitor, ensuring its withstand voltage.

[0146] Example 3

[0147] This embodiment provides an integrated capacitor, such as Figure 9 and Figure 13 As shown, two integrated capacitors based on Embodiment 1 and Embodiment 2 are illustrated, including a substrate 1, a dielectric layer 2, a lower electrode layer 3, a first dielectric layer 4, a second dielectric layer 5, a contact hole 51, a solder pad 6, and an upper electrode layer 7. The dielectric layer 2 covers the upper surface of the substrate 1; the lower electrode layer 3 is located on the upper surface of the dielectric layer 2, and the length of the lower electrode layer 3 in the X direction is less than the length of the dielectric layer 2 in the X direction; the first dielectric layer 4 covers the exposed surface of the lower electrode layer 3 and the upper surface of the dielectric layer 2, and the first dielectric layer 4 is made of a low dielectric material with a dielectric strength not exceeding 35. The process involves forming the material at a low temperature of 0°C; the second dielectric layer 5 covers the upper surface of the first dielectric layer 4, and the second dielectric layer 5 is formed using a high temperature process of not less than 650°C; the contact hole 51 is located in the second dielectric layer 5 above the lower electrode layer 3, and the contact hole 51 penetrates the second dielectric layer 5 and the first dielectric layer 4 to expose the upper surface of the lower electrode layer 3; the solder pad 6 covers the inner wall and bottom surface of the contact hole 5 and is electrically connected to the lower electrode layer 3; the upper electrode layer 7 is located on the upper surface of the second dielectric layer 5 above the lower electrode layer 3, and there is a predetermined distance between the upper electrode layer 7 and the solder pad 6.

[0148] Specifically, while ensuring device performance, the thickness of the substrate 1 can be selected according to the actual situation, and is not limited here.

[0149] Specifically, while ensuring device performance, the thickness of the dielectric layer 2 can be selected according to the actual situation, and is not limited here.

[0150] Specifically, while ensuring device performance, the size and thickness of the lower electrode layer 3 can be selected according to actual conditions, and are not limited here.

[0151] Specifically, while ensuring device performance, the thickness of the first dielectric layer 4 can be set according to the actual situation, and is not limited here.

[0152] Specifically, while ensuring device performance, the thickness of the second dielectric layer 5 can be selected according to the actual situation, and is not limited here.

[0153] Specifically, the solder pad 6 extends along the edge in the X direction to the top of the second dielectric layer 5 and covers the upper surface of the second dielectric layer 5.

[0154] Specifically, the upper surface of the second dielectric layer 5 is also provided with an isolation dielectric layer 8, which has a first opening 81 and a second opening 82. The first opening 81 is connected to the contact hole 51, and the second opening is located above the lower electrode layer 3. The bottom surface of the second opening 82 exposes the upper surface of the second dielectric layer 5.

[0155] Specifically, the side of the upper electrode layer 7 away from the solder pad 7 extends to the top of the isolation medium layer 8 around the second opening 82 and covers the upper surface of the isolation medium layer 8.

[0156] Specifically, while ensuring the voltage withstand performance of the device, the spacing between the upper electrode layer 7 and the solder pad 6 can be set according to the actual situation, and is not limited here; the distance of the side of the upper electrode layer 7 away from the solder pad 6 extending along the X direction can be set according to the actual situation, and is not limited here.

[0157] Specifically, in order to prevent edge breakdown of the plates of the integrated capacitor and ensure the withstand voltage of the capacitor, the upper plate layer 7 is formed using an air bridge process.

[0158] Specifically, the upper electrode layer 7 formed using the air bridge process includes multiple bottom conductive layers 71, multiple conductive pillars 72, and a top conductive layer 73. The bottom conductive layers 71 are located on the upper surface of the second dielectric layer 5, and at least one bottom conductive layer 71 is located above the lower electrode layer 3, forming the integrated capacitor together with the lower electrode layer 3, the first dielectric layer 4 located above the lower electrode layer, and the second dielectric layer 5. The bottom end of one conductive pillar 72 is in contact with the upper surface of one bottom conductive layer 71, and the top end of each conductive pillar 72 is electrically connected to the top conductive layer 73. The conductive pillars 72 are used to support the top conductive layer 73. In this embodiment, there are two bottom conductive layers 71 and two conductive pillars 72.

[0159] Specifically, while ensuring device performance, the thickness and size of the bottom conductive layer 71 can be set according to actual conditions and are not limited here; the thickness and size of the top conductive layer 73 can be set according to actual conditions and are not limited here.

[0160] Specifically, while ensuring that the conductive support 72 can support the top conductive layer 73, the height and size of the conductive support 72 can be set according to the actual situation, and are not limited here.

[0161] Specifically, since the upper electrode layer 7 covers the bottom surface of the second opening 82 in the isolation dielectric layer 8 and is spaced at a preset distance from the solder pad 6, premature breakdown of the edge of the integrated capacitor is avoided, thus ensuring the withstand voltage value of the capacitor.

[0162] The integrated capacitor in this embodiment improves the capacitance value by providing a first dielectric layer 4 with a low dielectric constant covering the exposed surface of the lower electrode layer 3 above the lower electrode layer 3, and a second dielectric layer 5 with a high dielectric constant on the upper surface of the first dielectric layer 4. At the same time, by providing an isolation dielectric layer 8 on the upper surface of the second dielectric layer 5, and forming an upper electrode layer 7 covering the bottom surface of the second opening 82 in the isolation dielectric layer 8, or by using an air bridge process to form the upper electrode layer 7, the withstand voltage value of the capacitor is guaranteed, and premature breakdown of the capacitor plates is prevented.

[0163] In summary, the integrated capacitor and its fabrication method of the present invention, by forming a first dielectric layer with a low dielectric constant covering the exposed surface of the lower electrode layer using a low-temperature process after forming the lower electrode layer, and then forming a second dielectric layer with a high dielectric constant on the upper surface of the first dielectric layer using a high-temperature process, avoids the vaporization and melting deformation of the lower electrode layer caused by the high-temperature process, ensuring that the effective electrode area of ​​the lower electrode layer remains unchanged, preventing contamination of the furnace tube during the formation of the second dielectric layer, reducing the maintenance frequency of the furnace tube, and thus reducing maintenance costs. Furthermore, the use of the high dielectric constant second dielectric layer increases the capacitance and withstand voltage of the integrated capacitor. Simultaneously, by providing an isolation dielectric layer including a first opening and a second opening on the upper surface of the second dielectric layer, and forming the upper electrode layer on the bottom surface of the second opening, or by using an air-bridge process to form the upper electrode layer, premature edge breakdown of the integrated capacitor's electrodes is prevented, ensuring the withstand voltage of the integrated capacitor. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0164] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an integrated capacitor, characterized in that, Includes the following steps: A substrate is provided, and a dielectric layer is formed on the upper surface of the substrate; A lower electrode layer of a predetermined thickness is formed on the upper surface of the dielectric layer, wherein the length of the lower electrode layer in the X direction is less than the length of the dielectric layer in the X direction; A first dielectric layer is formed covering the exposed surface of the lower electrode layer and the exposed upper surface of the dielectric layer. A second dielectric layer is formed on the upper surface of the first dielectric layer. The first dielectric layer is formed by a low-temperature process not exceeding 350°C, and the second dielectric layer is formed by a high-temperature process not lower than 650°C. A contact hole is formed in the second dielectric layer above the lower electrode layer, the contact hole penetrating the second dielectric layer and the first dielectric layer to expose the upper surface of the lower electrode layer; A solder pad is formed to cover the inner wall and bottom surface of the contact hole and to be electrically connected to the lower electrode layer. An upper electrode layer is formed on the upper surface of the second dielectric layer above the lower electrode layer. The upper electrode layer and the solder pad are spaced apart by a predetermined distance.

2. The method for fabricating an integrated capacitor according to claim 1, characterized in that: The method for forming the first dielectric layer includes plasma-enhanced chemical vapor deposition; the method for forming the second dielectric layer includes low-pressure chemical vapor deposition.

3. The method for fabricating an integrated capacitor according to claim 1, characterized in that: After the first dielectric layer is formed and before the second dielectric layer is formed, the method further includes a step of planarizing the upper surface of the first dielectric layer.

4. The method for fabricating an integrated capacitor according to claim 1, characterized in that: The material of the first dielectric layer includes SiN x The material of the second dielectric layer includes SiN x .

5. The method for fabricating an integrated capacitor according to claim 1, characterized in that: The temperature range for forming the second dielectric layer is 700℃~900℃.

6. The method for fabricating an integrated capacitor according to claim 1, characterized in that: The process includes forming an isolation dielectric layer before forming the solder pad and the upper electrode layer.

7. The method for fabricating an integrated capacitor according to claim 6, characterized in that: The material of the isolation medium layer includes one of polyimide and silicon dioxide.

8. The method for fabricating an integrated capacitor according to claim 6, characterized in that: The insulating medium layer covers the upper surface of the second medium layer. The insulating medium layer has a first opening and a second opening spaced apart. The first opening is located in the insulating medium layer above the contact hole and communicates with the contact hole. The second opening is located in the insulating medium layer above the lower electrode layer, and the bottom surface of the second opening exposes the upper surface of the second medium layer above the lower electrode layer.

9. The method for fabricating an integrated capacitor according to claim 1, characterized in that: The upper electrode layer is formed using an air bridge process.

10. An integrated capacitor, characterized in that, include: Substrate; A dielectric layer covering the upper surface of the substrate; The lower electrode layer is located on the upper surface of the dielectric layer, and the length of the lower electrode layer in the X direction is less than the length of the dielectric layer in the X direction. A first dielectric layer covers the exposed surface of the lower electrode layer and the upper surface of the dielectric layer. The first dielectric layer is formed using a low-temperature process with a temperature not exceeding 350°C. The second dielectric layer covers the upper surface of the first dielectric layer, and the second dielectric layer is formed using a high-temperature process of not less than 650°C; A contact hole is located in the second dielectric layer above the lower electrode layer. The contact hole penetrates the second dielectric layer and the first dielectric layer to expose the upper surface of the lower electrode layer. The upper electrode layer includes a solder pad and an upper electrode layer. The solder pad covers the inner wall and bottom surface of the contact hole and is electrically connected to the lower electrode layer. The upper electrode layer is located on the upper surface of the second dielectric layer above the lower electrode layer. The upper electrode layer and the solder pad are spaced apart by a preset distance.

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