Active element substrate

Abstract

An active element substrate includes a substrate, a buffer layer, a first metal oxide pattern, a first gate insulating structure, a second semiconductor layer, a second gate insulating structure, a first gate electrode, a second gate electrode, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The first metal oxide pattern is on the buffer layer and includes a first semiconductor layer and a first oxygen barrier layer. The first gate insulating structure is on the first metal oxide pattern. The second semiconductor layer is on the first gate insulating structure. The first oxygen barrier layer at least partially overlaps the second semiconductor layer. The second gate insulating structure is on the second semiconductor layer and the first gate insulating structure. The first gate electrode and the second gate electrode are on the second gate insulating structure and overlap the first semiconductor layer and the second semiconductor layer, respectively.

Description

TECHNICAL FIELD

[0001] The present invention relates to an active device substrate. BACKGROUND

[0002] Generally, an electronic device usually contains many active or passive devices for different purposes. For example, in some display devices, various forms of thin film transistors can be included to meet different requirements. In order to manufacture thin film transistors with different characteristics, multiple deposition processes and multiple doping processes are often performed, which results in high production cost and long production time of the display device. In addition, in the manufacture of thin film transistors, the resistivity of the semiconductor channel layer must be strictly controlled to improve the performance of the display device. SUMMARY

[0003] The present invention provides an active device substrate, which can preferably control the resistivity of the semiconductor layer.

[0004] At least one embodiment of the present invention provides an active device substrate. The active device substrate includes a substrate, a buffer layer, a first metal oxide pattern, a first gate insulating structure, a second semiconductor layer, a second gate insulating structure, a first gate electrode, a second gate electrode, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The buffer layer is on the substrate. The first metal oxide pattern is on the buffer layer and includes a first semiconductor layer and a first oxygen barrier layer. The first gate insulating structure is on the first metal oxide pattern and the buffer layer. The second semiconductor layer is on the first gate insulating structure. The first oxygen barrier layer at least partially overlaps the second semiconductor layer. The second gate insulating structure is on the second semiconductor layer and the first gate insulating structure. The first gate electrode and the second gate electrode are on the second gate insulating structure and overlap the first semiconductor layer and the second semiconductor layer, respectively. The first source electrode and the first drain electrode are electrically connected to the first semiconductor layer. The second source electrode and the second drain electrode are electrically connected to the second semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a cross-sectional view of an active device substrate according to an embodiment of the present invention;

[0006] Figures 2A-2D is a cross-sectional view of a manufacturing method of an active device substrate according to Figure 1

[0007] Figure 3 is a cross-sectional view of an active device substrate according to an embodiment of the present invention;

[0008] Figure 4 is a cross-sectional view of an active device substrate according to an embodiment of the present invention;

[0009] Figure 5 ​FIG. 1 is a cross-sectional view of an active device substrate according to an embodiment of the present application.

[0010] Figure 6 FIG. 2 is a cross-sectional view of an active device substrate according to an embodiment of the present application.

[0011] Symbol explanation

[0012] 10, 20, 30, 40, 50: active device substrate

[0013] 100: substrate

[0014] 110: barrier layer

[0015] 120: buffer layer

[0016] 130: first gate insulating structure

[0017] 133: first gate dielectric layer

[0018] 135: second gate dielectric layer

[0019] 140: second gate insulating structure

[0020] 143: third gate dielectric layer

[0021] 145: fourth gate dielectric layer

[0022] 150: interlayer dielectric layer

[0023] ch1: first channel region

[0024] ch2: second channel region

[0025] ch2a1: first upper region

[0026] ch2a2: second upper region

[0027] ch2b: lower region

[0028] D1: first drain

[0029] D2: second drain

[0030] dr1: first drain region

[0031] dr2: second drain region

[0032] G1: first gate

[0033] G2: second gate

[0034] GP: gap

[0035] L: length

[0036] MOP, MOP': first metal oxide pattern

[0037] ND: normal direction

[0038] OB1: first oxygen barrier layer

[0039] OB2: second oxygen barrier layer

[0040] OS1, OS1': first semiconductor layer

[0041] OS2, OS2': second semiconductor layer

[0042] P: doping process

[0043] S1: first source

[0044] S2: second source

[0045] sr1: first source region

[0046] sr2: second source region

[0047] T1: first thin film transistor

[0048] T2: second thin film transistor

[0049] V1: first contact hole

[0050] V2: second contact hole

[0051] V3: third contact hole

[0052] V4: fourth contact hole DETAILED DESCRIPTION

[0053] Figure 1 is a cross-sectional schematic view of an active device substrate 10 according to an embodiment of the present application. Referring to Figure 1 , the active device substrate 10 includes a substrate 100, a buffer layer 120, a first metal oxide pattern MOP, a first gate insulating structure 130, a second semiconductor layer OS2, a second gate insulating structure 140, a first gate G1, a second gate G2, a first source S1, a first drain D1, a second source S2, and a second drain D2. In this embodiment, the active device substrate 10 further includes a barrier layer 110 and an interlayer dielectric layer 150.

[0054] The substrate 100 can be made of glass, quartz, organic polymer, or non-transparent / reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable material), or other applicable material. If conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problem. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil, or other flexible material.

[0055] The barrier layer 110 and the buffer layer 120 are located on the substrate 100. In some embodiments, the barrier layer 110 is covered on the substrate 100, and the buffer layer 120 is located on the barrier layer 110.

[0056] In some embodiments, the barrier layer 110 contains hydrogen element. For example, the material of the barrier layer 110 includes hydrogen-containing silicon nitride (or hydrogenated silicon nitride) or other suitable material. In some embodiments, the barrier layer 110 can be used to block ions in the substrate 100, so as to avoid the diffusion of ions in the substrate 100 upward. In some embodiments, the buffer layer 120 contains oxygen element. For example, the buffer layer 120 includes oxygen-containing insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable material. In some embodiments, the thickness of the barrier layer 110 is 100 angstroms to 3000 angstroms, and the thickness of the buffer layer 120 is 100 angstroms to 3000 angstroms.

[0057] The first thin film transistor T1 and the second thin film transistor T2 are located on the substrate 100. In some embodiments, the first thin film transistor T1 and the second thin film transistor T2 are located on the buffer layer 120. The first thin film transistor T1 includes a first semiconductor layer OS1, a first gate G1, a first source S1, and a first drain D1. The second thin film transistor T2 includes a second semiconductor layer OS2, a second gate G2, a second source S2, and a second drain D2. The specific structure of the first thin film transistor T1 and the second thin film transistor T2 will be described later.

[0058] The first metal oxide pattern MOP is located on the buffer layer 120, and the buffer layer 120 is located between the first metal oxide pattern MOP and the substrate 100. The first metal oxide pattern MOP includes a first semiconductor layer OS1 and a first oxygen barrier layer OB1, and contacts a top surface of the buffer layer 120. The first semiconductor layer OS1 and the first oxygen barrier layer OB1 include the same material. The first semiconductor layer OS1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1. In some embodiments, a resistivity of the first channel region ch1 and a resistivity of the first oxygen barrier layer OB1 are greater than a resistivity of the first source region sr1 and a resistivity of the first drain region dr1.

[0059] The first gate insulating structure 130 is located on the first metal oxide pattern MOP and the buffer layer 120. The first gate insulating structure 130 includes a first gate dielectric layer 133 and a second gate dielectric layer 135. The first gate dielectric layer 133 is located on the first metal oxide pattern MOP. The second gate dielectric layer 135 is located on the first gate dielectric layer 133. In this embodiment, both the first semiconductor layer OS1 and the first oxygen barrier layer OB1 are located between the first gate dielectric layer 133 and the buffer layer 120.

[0060] The second semiconductor layer OS2 is located on the first gate insulating structure 130. In some embodiments, a second metal oxide pattern is located on the first gate insulating structure 130, and the second metal oxide pattern includes the second semiconductor layer OS2. The second semiconductor layer OS2 includes a second source region sr2, a second drain region dr2, and a second channel region ch2 located between the second source region sr2 and the second drain region dr2. In some embodiments, a resistivity of the second channel region ch2 is greater than a resistivity of the second source region sr2 and a resistivity of the second drain region dr2.

[0061] The first oxygen barrier layer OB1 at least partially overlaps the second semiconductor layer OS2 in a normal direction ND of a surface of the substrate 100. In this embodiment, the first oxygen barrier layer OB1 continuously extends from below the second drain region dr2 to below the second source region sr2, and the entire second channel region ch2 overlaps the first oxygen barrier layer OB1.

[0062] In some embodiments, the materials of the first semiconductor layer OS1 and the second semiconductor layer OS2 include quaternary metal compounds such as indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or oxides including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), tungsten (W), or lanthanide-doped metal oxides (e.g., Ln-IZO). In some embodiments, the first semiconductor layer OS1 and the second semiconductor layer OS2 include the same material. In other embodiments, the first semiconductor layer OS1 and the second semiconductor layer OS2 include different materials. In some embodiments, the first channel region ch1 of the first semiconductor layer OS1 has a different (greater or smaller) carrier mobility than the second channel region ch2 of the second semiconductor layer OS2.

[0063] The second gate insulating structure 140 is located on the second semiconductor layer OS2 and the first gate insulating structure 130. The second gate insulating structure 140 includes a third gate dielectric layer 143 and a fourth gate dielectric layer 145. The third gate dielectric layer 143 is located on the second semiconductor layer OS2. The fourth gate dielectric layer 145 is located on the third gate dielectric layer 143. In the present embodiment, the second semiconductor layer OS2 is located between the second gate dielectric layer 135 and the third gate dielectric layer 143.

[0064] In some embodiments, the buffer layer 120, the first gate dielectric layer 133, the second gate dielectric layer 135, and the third gate dielectric layer 143 contain oxygen elements. For example, the buffer layer 120, the first gate dielectric layer 133, the second gate dielectric layer 135, and the third gate dielectric layer 143 include oxygen-containing insulating materials such as oxides or oxynitrides, e.g., silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the material of the fourth gate dielectric layer 145 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials.

[0065] In some embodiments, the buffer layer 120 and / or the first gate insulating structure 130 will supplement oxygen to the first semiconductor layer OS1 and the first oxygen barrier layer OB1, causing the resistivity of the first semiconductor layer OS1 and the first oxygen barrier layer OB1 to rise. In some embodiments, the first gate insulating structure 130 and / or the second gate insulating structure 140 will supplement oxygen to the second semiconductor layer OS2, causing the resistivity of the second semiconductor layer OS2 to rise.

[0066] In some embodiments, the thicker the thickness of the oxygen-containing insulating layer under the metal oxide (including the first semiconductor layer OS1, the first oxygen-blocking layer OB1, and the second semiconductor layer OS2), the more oxygen atoms will diffuse into the metal oxide. In the present embodiment, the oxygen-containing insulating layer under the second semiconductor layer OS2 includes the buffer layer 120 in addition to the first gate insulating structure 130. Therefore, to avoid too many oxygen atoms from entering the second semiconductor layer OS2, the first oxygen-blocking layer OB1 is disposed under the second semiconductor layer OS2 to reduce the probability of oxygen atoms in the buffer layer 120 diffusing into the second semiconductor layer OS2, thereby avoiding the problem of the second drain region dr2 and the second source region sr2 of the second semiconductor layer OS2 having too high resistivity and improving the performance of the second thin-film transistor T2.

[0067] The first gate G1 and the second gate G2 are located on the second gate insulating structure 140 and overlap the first channel region ch1 of the first semiconductor layer OS1 and the second channel region ch2 of the second semiconductor layer OS2, respectively. The first gate insulating structure 130 and the second gate insulating structure 140 are located between the first gate G1 and the first semiconductor layer OS1. The second gate insulating structure 140 is located between the second gate G2 and the second semiconductor layer OS2. In some embodiments, the first gate G1 and the second gate G2 belong to the same film layer, thereby reducing the cost required by the manufacturing process. In some embodiments, the thickness of the insulating material between the first gate G1 and the first semiconductor layer OS1 is greater than the thickness of the insulating material between the second gate G2 and the second semiconductor layer OS2, thereby making the first thin-film transistor T1 and the second thin-film transistor T2 have different characteristics.

[0068] The interlayer dielectric layer 150 is located on the second gate insulating structure 140 and covers the first gate G1 and the second gate G2. In some embodiments, the material of the interlayer dielectric layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials.

[0069] The first contact hole V1 and the second contact hole V2 pass through the interlayer dielectric layer 150, the first gate insulating structure 130, and the second gate insulating structure 140. The first drain D1 and the first source S1 are located on the interlayer dielectric layer 150 and are filled into the first contact hole V1 and the second contact hole V2, respectively, to electrically connect the first semiconductor layer OS1. The first drain D1 and the first source S1 are connected to the first drain region dr1 and the first source region sr1 of the first semiconductor layer OS1, respectively.

[0070] The third contact hole V3 and the fourth contact hole V4 pass through the interlayer dielectric layer 150 and the second gate insulating structure 140. The second drain D2 and the second source S2 are located on the interlayer dielectric layer 150 and fill the third contact hole V3 and the fourth contact hole V4, respectively, to electrically connect the second semiconductor layer OS2. The second drain D2 and the second source S2 are connected to the second drain region dr2 and the second source region sr2 of the second semiconductor layer OS2, respectively.

[0071] Figures 2A-2D is a cross-sectional schematic view of a manufacturing method of the active element substrate 10. Figure 1

[0072] Referring to Figure 2A A first metal oxide pattern MOP' is formed on the buffer layer 120. In the present embodiment, the first metal oxide pattern MOP' includes a first semiconductor layer OS1' and a first oxygen barrier layer OB1. In some embodiments, the manufacturing process temperature when forming the first metal oxide pattern MOP' is room temperature (for example, 25 degrees Celsius) to 400 degrees Celsius.

[0073] Referring to Figure 2B A first gate insulating structure 130 is formed on the first metal oxide pattern MOP'. In some embodiments, the method of forming the first gate insulating structure 130 includes sequentially depositing a first gate dielectric layer 133 and a second gate dielectric layer 135.

[0074] A second semiconductor layer OS2' is formed on the second gate dielectric layer 135. In some embodiments, the manufacturing process temperature when forming the second semiconductor layer OS2' is room temperature to 300 degrees Celsius. In some embodiments, the second semiconductor layer OS2' and the first semiconductor layer OS1' include different materials, and the carrier mobility of the second semiconductor layer OS2' is higher than the carrier mobility of the first semiconductor layer OS1'.

[0075] Referring to Figure 2C A second gate insulating structure 140 is formed on the first gate insulating structure 130 and the second semiconductor layer OS2'. In some embodiments, the method of forming the second gate insulating structure 140 includes sequentially depositing a third gate dielectric layer 143 and a fourth gate dielectric layer 145.

[0076] ​The first gate G1 and the second gate G2 are formed on the second gate insulating structure 140. Then, the first semiconductor layer OS1' and the second semiconductor layer OS2' are doped by a doping process P with the first gate G1 and the second gate G2 as masks to form the first semiconductor layer OS1 including the first source region sr1, the first drain region dr1 and the first channel region ch1, and the second semiconductor layer OS2 including the second source region sr2, the second drain region dr2 and the second channel region ch2. In some embodiments, the doping process P is, for example, a hydrogen plasma process or other suitable process. After the doping process P, the resistivity of the first source region sr1, the first drain region dr1, the second source region sr2 and the second drain region dr2 is less than the resistivity of the first channel region ch1 and the second channel region ch2.

[0077] In the present embodiment, the first oxygen blocking layer OB1 is shielded by the second semiconductor layer OS2' during the doping process P, and thus the first oxygen blocking layer OB1 is not doped during the doping process P. Therefore, after the doping process P, the resistivity of the first oxygen blocking layer OB1 is greater than the resistivity of the first source region sr1, the first drain region dr1, the second source region sr2 and the second drain region dr2.

[0078] The buffer layer 120, the first gate insulating structure 130 and the second gate insulating structure 140 provide oxygen elements during the process and increase the resistivity of the first semiconductor layer OS1 and the second semiconductor layer OS2. In the present embodiment, the first oxygen blocking layer OB1 can reduce the probability of oxygen atoms in the buffer layer 120 entering the second source region sr2 and the second drain region dr2, thereby avoiding the problem of excessively high resistivity of the second source region sr2 and the second drain region dr2.

[0079] In the present embodiment, the first gate G1 and the second gate G2 belong to the same patterned layer, and the first semiconductor layer OS1 and the second semiconductor layer OS2 can be doped by the same doping process P, thereby saving the cost of the process.

[0080] Please refer to Figure 2D The interlayer dielectric layer 150 is formed on the fourth gate dielectric layer 145. Then, an etching process is performed to form the first contact hole V1, the second contact hole V2, the third contact hole V3 and the fourth contact hole V4.

[0081] Finally, please refer to Figure 1The first drain D1, the first source S1, the second drain D2, and the second source S2 are formed on the interlayer dielectric layer 150 and filled into the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4, respectively. Thus, the active element substrate 10 is substantially completed.

[0082] In the present embodiment, the first gate insulating structure 130 covers the entire upper surface of the first semiconductor layer OS1, and the second gate insulating structure 140 covers the entire upper surface of the second semiconductor layer OS2, but the present application is not limited thereto. In other embodiments, the first gate insulating structure 130 and the second gate insulating structure 140 are etched with the first gate G1 and the second gate G2 as masks, so that the first gate insulating structure 130 and the second gate insulating structure 140 are exposed to the first semiconductor layer OS1 and the second semiconductor layer OS2. In this case, the interlayer dielectric layer 150 formed subsequently can directly contact the first semiconductor layer OS1 and the second semiconductor layer OS2, so that the first semiconductor layer OS1 and the second semiconductor layer OS2 can be doped by hydrogen elements in the interlayer dielectric layer 150. In some embodiments, when the first semiconductor layer OS1 and the second semiconductor layer OS2 are doped by hydrogen elements in the interlayer dielectric layer 150, the hydrogen plasma doping process can be omitted, and the interlayer dielectric layer 150 directly contacts the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2.

[0083] Figure 3 is a cross-sectional view of an active element substrate 20 according to an embodiment of the present application. It must be noted that, Figure 3 the embodiments of Figures 1-2D the element numbers and parts of the embodiments of

[0084] Figure 3 the active element substrate 20 of Figure 1 the main difference between the active element substrate 20 and the active element substrate 10 of

[0085] Please refer to Figure 3The first oxygen barrier layer OB1 and the second oxygen barrier layer OB2 are separated from each other, and the first oxygen barrier layer OB1 and the second oxygen barrier layer OB2 respectively overlap the second drain region dr2 and the second source region sr2 of the second semiconductor layer OS2 in the normal direction ND of the surface of the substrate 100. At least part of the second channel region ch2 of the second semiconductor layer OS2 does not overlap the first metal oxide pattern MOP in the normal direction ND. In this embodiment, the first oxygen barrier layer OB1 continuously extends from below the second drain region dr2 to below the second channel region ch2, and the second oxygen barrier layer OB2 continuously extends from below the second source region sr2 to below the second channel region ch2. In other words, part of the first oxygen barrier layer OB1 and part of the second oxygen barrier layer OB2 overlap the second channel region ch2 in the normal direction ND, but the present application is not limited thereto. In other embodiments, the first oxygen barrier layer OB1 and the second oxygen barrier layer OB2 do not overlap the second channel region ch2 in the normal direction ND at all.

[0086] In some embodiments, the gap GP between the first oxygen barrier layer OB1 and the second oxygen barrier layer OB2 is less than the length L of the second gate G2. In some embodiments, the gap GP between the first oxygen barrier layer OB1 and the second oxygen barrier layer OB2 is greater than 0.5 microns

[0087] In this embodiment, by the provision of the first oxygen barrier layer OB1 and the second oxygen barrier layer OB2, the probability of oxygen atoms in the buffer layer 120 entering the second source region sr2 and the second drain region dr2 can be reduced, thereby improving the performance of the second thin film transistor T2.

[0088] Figure 4 is a cross-sectional view of an active device substrate 30 according to an embodiment of the present application. It must be noted that, Figure 4 the embodiments of Figure 3 the element numbers and some contents of the embodiments of the element numbers and some contents of the embodiments of

[0089] the element numbers and some contents of the embodiments of Figure 4 the active device substrate 30 of Figure 3 the active device substrate 20 of The main difference between the active device substrate 30 and the active device substrate 20 is that the second semiconductor layer OS2 has a stepped structure in the active device substrate 30.

[0090] Please refer to Figure 4The first gate insulating structure 130 is conformally formed on the first oxygen-blocking layer OB1 and the second oxygen-blocking layer OB2. Therefore, the first gate insulating structure 130 has a stepped structure corresponding to the gap GP between the first oxygen-blocking layer OB1 and the second oxygen-blocking layer OB2. Similarly, the second semiconductor layer OS2 is conformally formed on the first gate insulating structure 130. Therefore, the second semiconductor layer OS2 also has a stepped structure corresponding to the gap GP between the first oxygen-blocking layer OB1 and the second oxygen-blocking layer OB2.

[0091] In the present embodiment, the second channel region of the second semiconductor layer OS2 includes a first upper region ch2a1, a lower region ch2b, and a second upper region ch2a2. The lower region ch2b is located between the first upper region ch2a1 and the second upper region ch2a2. The height position of the lower region ch2b is lower than the height positions of the first upper region ch2a1 and the second upper region ch2a2, with respect to the substrate 100. The first upper region ch2a1, the lower region ch2b, and the second upper region ch2a2 constitute a stepped structure. In the present embodiment, the portion of the second channel region extending along the vertical direction (the normal direction ND) can reduce the hot carrier effect of the second semiconductor layer OS2 due to the lateral electric field near the second drain D2.

[0092] Figure 5 is a cross-sectional schematic view of an active device substrate 40 according to an embodiment of the present application. It must be noted that, Figure 5 the embodiments of Figure 4 the element reference numerals and parts of the embodiments of the element reference numerals and parts of the embodiments of

[0093] the element reference numerals and parts of the embodiments of Figure 5 the active device substrate 40 of Figure 4 the active device substrate 30 of the active device substrate 30 of

[0094] the active device substrate 30 of Figure 5 The first oxygen-blocking layer OB1 overlaps one of the second source region sr2 and the second drain region dr2 in the normal direction ND of the surface of the substrate 100, and the first oxygen-blocking layer OB1 continuously extends from below at least one of the second source region sr2 and the second drain region dr2 to below the second channel region ch2. The other of the second source region sr2 and the second drain region dr2 does not overlap the first metal oxide pattern MOP in the normal direction ND of the surface of the substrate 100.

[0095] In this embodiment, the first oxygen barrier layer OB1 overlaps the second drain region dr2, and the first oxygen barrier layer OB1 extends continuously from below the second drain region dr2 to below the second channel region ch2. The second source region sr2 does not overlap the first metal oxide pattern MOP.

[0096] The first gate insulating structure 130 is conformally formed on the first oxygen barrier layer OB1, and therefore, the first gate insulating structure 130 has a stepped structure corresponding to the first oxygen barrier layer OB1. Similarly, the second semiconductor layer OS2 is conformally formed on the first gate insulating structure 130, and therefore, the second semiconductor layer OS2 also has a stepped structure corresponding to the first oxygen barrier layer OB1.

[0097] In this embodiment, the second channel region of the second semiconductor layer OS2 includes a first upper region ch2a1 and a lower region ch2b that are connected to each other. With the substrate 100 as a reference, the lower region ch2b is positioned at a lower height than the first upper region ch2a1, thus forming a stepped structure between the first upper region ch2a1 and the lower region ch2b. In this embodiment, a portion of the second channel region extends along the vertical direction (normal direction ND), which can reduce the hot carrier effect generated by the lateral electric field near the second drain D2 in the second semiconductor layer OS2.

[0098] Figure 6 This is a schematic cross-sectional view of an active element substrate 50 according to an embodiment of the present invention. It should be noted that... Figure 6 The embodiments follow Figures 1-2D The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0099] Figure 6 Active component substrate 50 and Figure 1 The main difference between the active element substrate 10 and the active element substrate 50 is that the first source S1, the first drain D1, the first gate G1, the second source S2, the second drain D2 and the second gate G2 belong to the same film layer, which can reduce the cost of the manufacturing process.

[0100] In some embodiments, before forming the first source S1, first drain D1, first gate G1, second source S2, second drain D2, and second gate G2, other photoresist patterns are additionally formed, and the doping fabrication process of the first semiconductor layer OS1 and the second semiconductor layer OS2 is performed using these other photoresist patterns as masks. Then, the aforementioned photoresist patterns are removed. Finally, the first source S1, first drain D1, first gate G1, second source S2, second drain D2, and second gate G2 are formed.

[0101] In summary, by setting an oxygen barrier layer, the resistivity of the semiconductor layer can be better controlled, thereby improving the performance of thin-film transistors.

Claims

1. An active element substrate, comprising: substrate; A buffer layer is located on the substrate; A first metal oxide pattern is located on the buffer layer and includes a first semiconductor layer and a first oxygen barrier layer. A first gate insulating structure is located on the first metal oxide pattern and the buffer layer; A second semiconductor layer is located on the first gate insulating structure, wherein the first oxygen barrier layer at least partially overlaps the second semiconductor layer; The second gate insulating structure is located on the second semiconductor layer and the first gate insulating structure. The first gate and the second gate are located on the second gate insulating structure and are respectively superimposed on the first semiconductor layer and the second semiconductor layer; The first source and the first drain are electrically connected to the first semiconductor layer; as well as The second source and the second drain are electrically connected to the second semiconductor layer.

2. The active element substrate as claimed in claim 1, wherein the first gate and the second gate belong to the same film layer.

3. The active element substrate as claimed in claim 2, wherein the first source, the first drain, the first gate, the second source, the second drain, and the second gate belong to the same film layer.

4. The active element substrate of claim 1, wherein the first semiconductor layer includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region, and the second semiconductor layer includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region, wherein the first oxygen barrier layer extends continuously from below at least one of the second source region and the second drain region to below the second channel region.

5. The active element substrate of claim 4, wherein the first metal oxide pattern further includes a second oxygen barrier layer, the first oxygen barrier layer and the second oxygen barrier layer are separated from each other, and the first oxygen barrier layer and the second oxygen barrier layer overlap the second drain region and the second source region respectively in the normal direction of the surface of the substrate.

6. The active element substrate of claim 5, wherein the gap between the first oxygen barrier layer and the second oxygen barrier layer is less than the length of the second gate.

7. The active element substrate as claimed in claim 5, wherein the gap between the first oxygen barrier layer and the second oxygen barrier layer is greater than 0.5 micrometers.

8. The active element substrate as claimed in claim 4, wherein the resistivity of the first oxygen barrier layer is greater than the resistivity of the first source region and the resistivity of the first drain region.

9. The active element substrate of claim 1, wherein the second semiconductor layer comprises a stepped structure.

10. The active element substrate of claim 1, wherein the first gate insulating structure includes a first gate dielectric layer and a second gate dielectric layer, and the second gate insulating structure includes a third gate dielectric layer and a fourth gate dielectric layer.

11. The active element substrate of claim 1, wherein the first semiconductor layer includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region, and the second semiconductor layer includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region, wherein the first oxygen barrier layer extends continuously from below the second drain region to below the second source region.

12. The active element substrate of claim 1, wherein the first semiconductor layer includes a first source region, a first drain region, and a first channel region located between the first source region and the first drain region, and the second semiconductor layer includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region, wherein one of the second source region and the second drain region does not overlap with the first metal oxide pattern in the normal direction of the surface of the substrate.

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