Method for manufacturing MOSFET device, device and equipment thereof

Abstract

The present invention provides a method for manufacturing a MOSFET device, comprising: forming a MOSFET device structure having a gate trench; the MOSFET device structure includes a substrate and an epitaxial layer formed on the substrate; a field oxide layer formed on the inner wall of the gate trench and on the surface of the epitaxial layer outside the gate trench; forming a shielding gate; wherein the top of the shielding gate is a flat surface. Forming an intergate oxide layer and a gate; the intergate oxide layer is formed on the flat surface of the shielding gate, and the gate is formed on the intergate oxide layer; sequentially forming a body ion implantation layer and a source ion implantation layer in the epitaxial layer around the gate, sequentially forming an interlayer dielectric layer and a metal aluminum layer on the top of the gate, and forming a contact hole. This technical solution solves the problem of how to manufacture a shielding gate with a flat surface, and achieves the technical effect of ensuring that the device has better electrical properties.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for manufacturing a MOSFET device, and a method for manufacturing the device and equipment thereof. Background Art

[0002] Currently in SGT / Trench MOS products, due to the existence of vertical device trenches, when filling polysilicon,

[0003] Due to the presence of the trench, a seam will be formed below the top of the trench when the polysilicon is formed. This seam will be magnified during polysilicon etching, thereby affecting device performance.

[0004] To ensure effective polysilicon filling, the device's trench angle is typically controlled to less than 89 degrees. This process influences the inability to achieve a perfectly straight trench angle. This results in a smaller width of the bottom polysilicon when filling non-perpendicular trenches. This, in turn, reduces the device's charge coupling capability in lateral two-dimensional charge-coupled devices (CCDs), further impacting device performance. Consequently, reducing feature size becomes a challenge, and developing a method for producing flat polysilicon has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0005] The present invention provides a method for manufacturing a MOSFET device, and a method for manufacturing the device and the device thereof, so as to solve the problem of how to manufacture a shielding grid with a flat surface.

[0006] According to a first aspect of the present invention, a method for manufacturing a MOSFET device is provided, comprising: forming a MOSFET device structure having a gate trench; the MOSFET device structure comprising a substrate and an epitaxial layer formed on the substrate; the gate trench being formed in the epitaxial layer; and a field oxide layer being formed on an inner wall of the gate trench and on a surface of the epitaxial layer outside the gate trench;

[0007] A shielding gate is formed, wherein the shielding gate is formed at the bottom of the gate trench; the field oxide layer is formed between the shielding gate and the epitaxial layer; wherein the top of the shielding gate is a flat surface.

[0008] forming an inter-gate oxide layer and a gate; the inter-gate oxide layer is formed on the flat surface of the shielding gate, and the gate is formed on the inter-gate oxide layer and fills the top of the gate trench;

[0009] A body ion implantation layer and a source ion implantation layer are sequentially formed in the epitaxial layer around the gate, an interlayer dielectric layer and a metal aluminum layer are sequentially formed on the top of the gate, and a contact hole is formed; the contact hole penetrates the body ion implantation layer, the source ion implantation layer, the interlayer dielectric layer and the edge of the metal aluminum layer away from the gate.

[0010] Optionally, forming the shielding gate specifically includes:

[0011] Depositing a gate material in the gate trench; wherein the gate trench includes a gap;

[0012] forming an oxide layer in the gap;

[0013] The gate material at the top of the gate trench and the gate material on the surface of the epitaxial layer outside the gate trench are removed to form the shielding gate at the bottom of the gate trench.

[0014] Optionally, the oxide layer is formed in the gap by performing low-temperature thermal oxidation on the gate material in the gate trench, so that the oxide layer is formed in the gap to fill the gap.

[0015] Optionally, removing the gate material at the top of the gate trench and the gate material on the surface of the epitaxial layer outside the gate trench to form the shielding gate at the bottom of the gate trench specifically includes:

[0016] The gate material on the surface of the field oxide layer outside the gate trench, the gate material at the top of the gate trench and the oxide layer in the gap are etched to form the shielding gate with a flat surface at the bottom of the gate trench.

[0017] Optionally, removing the gate material at the top of the gate trench and the gate material on the surface of the epitaxial layer outside the gate trench to form the shielding gate at the bottom of the gate trench specifically includes:

[0018] CMP polishing the gate material deposited on the surface of the field oxide layer outside the gate trench;

[0019] The gate material at the top of the gate trench and the oxide layer in the gap are etched to form the shielding gate with a flat surface at the bottom of the gate trench.

[0020] Optionally, the gate material at the top of the gate trench and the oxide layer in the gap are etched, and the etching selection ratio of the gate material to the oxide layer is 75:1, so that a flat surface is formed on the top of the shielding gate after etching.

[0021] Optionally, forming the inter-gate oxide layer and the gate specifically includes:

[0022] forming the inter-gate oxide layer on the top of the shielding gate;

[0023] Depositing a gate material in the gate trench on top of the inter-gate oxide layer;

[0024] The gate material on the surface of the field oxide layer outside the gate trench is etched to form the gate; wherein the top of the gate is a flat surface.

[0025] According to a second aspect of the present invention, there is provided a MOSFET device manufactured using the method for manufacturing a MOSFET device according to any one of the first aspects of the present invention, comprising:

[0026] A MOSFET device structure having a gate trench, the MOSFET device comprising a substrate and an epitaxial layer formed on the substrate; the gate trench is formed in the epitaxial layer; a field oxide layer is formed on an inner wall of the gate trench and on a surface of the epitaxial layer outside the gate trench;

[0027] A shielding gate is formed at the bottom of the gate trench; the field oxide layer is formed between the shielding gate and the epitaxial layer; wherein the top of the shielding gate is a flat surface;

[0028] an intergate oxide layer and a gate, wherein the intergate layer is formed on a flat surface of the shielding gate;

[0029] Body region ion implantation layer, source region ion implantation layer, interlayer dielectric layer, metal aluminum layer and contact holes.

[0030] Optionally, a gap is included under the flat surface of the shielding gate; and the gap is filled with an oxide layer.

[0031] Optionally, the top of the gate is a flat surface.

[0032] Optionally, the gate is made of polysilicon.

[0033] Optionally, the oxide layer is silicon dioxide.

[0034] Optionally, the characteristic size of the MOSFET device is between 0.5-0.8um pitch.

[0035] According to a third aspect of the present invention, there is provided a method for manufacturing an electronic device, comprising the method for manufacturing a MOSFET device according to any one of the first aspects of the present invention.

[0036] According to a fourth aspect of the present invention, there is provided an electronic device comprising the MOSFET device according to any one of the second aspects of the present invention.

[0037] The present invention provides a method for manufacturing a MOSFET device, which forms a shielding gate with a flat surface, and then forms an inter-gate oxide layer on the top of the shielding gate, so that a gate with a flat surface is formed on the top of the inter-gate oxide layer. It can be seen that the technical solution provided by the present invention solves the problem of how to manufacture a shielding gate with a flat surface, thereby achieving the technical effect of ensuring that the device has better electrical properties.

[0038] Furthermore, the problem of how to form a gate with a smooth surface is solved. Compared to the prior art method of forming a gate on a shielded gate with a severe V-shaped morphology, this method allows the device's characteristic dimensions to be further reduced while ensuring that the shielded gate has a certain thickness in smaller device structures. This further reduces the device's characteristic dimensions while ensuring the shielded gate's charge coupling capability, thereby ensuring the device's breakdown voltage and avoiding breakdown. Of course, the technical solution provided by the present invention ensures that the shielded gate has a certain thickness in smaller device structures, thus further reducing the characteristic dimensions of devices fabricated using the technical solution provided by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 This is a flow chart of a method for manufacturing a MOSFET device provided by one embodiment of the present invention;

[0041] Figure 2-7 Schematic diagram of a device structure at different process stages according to a method for manufacturing a MOSFET device provided by a specific embodiment of the present invention;

[0042] Description of reference numerals:

[0043] 101- epitaxial layer;

[0044] 102-field oxygen layer;

[0045] 103-gate material;

[0046] 104- oxide layer;

[0047] 105-intergate oxide layer;

[0048] 106-gate;

[0049] 107-body ion implantation layer;

[0050] 108-source region ion implantation layer;

[0051] 109-interlayer dielectric layer;

[0052] 110-Metal layer. DETAILED DESCRIPTION

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0054] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0055] The traditional manufacturing process of SGT / Trench mos products includes:

[0056] 1. Providing a substrate and forming an epitaxial layer on the substrate;

[0057] 2. Etching the epitaxial layer to form a gate trench;

[0058] 3. Forming a field oxide layer; the field oxide is formed on the inner wall of the gate trench and the surface of the epitaxial layer;

[0059] 4. depositing a gate material in the gate trench; wherein a gap is formed in the gate material deposited in the gate trench;

[0060] 5. Etching the gate material in the gate trench to form a bottom shield gate; wherein, since there are gaps in the gate material deposited in the gate trench, the gaps are enlarged during etching, resulting in the angle of the top of the etched shield gate being less than 89° rather than a right angle (i.e., the surface is "V"-shaped and uneven);

[0061] 6. An inter-gate oxide layer is formed on the top of the shielding gate;

[0062] 7. forming a gate electrode formed on the top of the inter-gate oxide layer, wherein the angle of the top of the gate electrode is also less than 89° rather than a right angle (i.e., the angle of the top of the gate electrode formed by shielding the top of the gate electrode is less than 89°);

[0063] 8. A body ion implantation layer and a source ion implantation layer are sequentially formed in the epitaxial layer around the gate, an interlayer dielectric layer and a metal aluminum layer are sequentially formed on top of the gate, and a contact hole is formed; the contact hole penetrates the body ion implantation layer, the source ion implantation layer, the interlayer dielectric layer and the edge of the metal aluminum layer away from the gate.

[0064] Therefore, in SGT / Trench MOS products, due to the presence of the trench, a seam will inevitably form below the top of the trench during polysilicon formation. This seam will be magnified during polysilicon etching, making it impossible to make the shield gate into a flat surface, thus affecting device performance.

[0065] To solve this problem, existing technologies, when filling polysilicon, in order to adapt to the uneven surface of the shielding gate and ensure the filling effect of the polysilicon, so that the trench angle cannot be made too straight, usually control the trench angle of the device to be less than 89 degrees (that is, the angle of the top of the gate made on the top of the shielding gate is less than 89 degrees). As a result, when filling the non-right-angle trench, the thickness of the bottom polysilicon shielding gate is relatively small, which reduces the charge coupling ability of the device. Therefore, in lateral two-dimensional charge-coupled devices, in order to avoid gaps, the width of the gate trench is usually made larger. Therefore, while ensuring the distance between two adjacent gate trenches, it becomes difficult to further reduce the feature size of the device. In traditional SGT / Trench MOS products, the SGT size is between 0.8-1.2um pitch. It can be seen that the technical problems existing in the prior art are: the surface of the shielding gate is uneven and has a serious V-mouth morphology, and in order to adapt to the gap of the shielding gate, the groove angle of the device (that is, the angle of the top of the gate after the shielding gate and the gate are formed in the gate groove) is reduced from 90° to below 89°, and a right-angled groove cannot be made.

[0066] In view of this, the inventors of this application oxidize the polysilicon material filled in the gate trench by thermal oxidation to fill the gaps in the polysilicon with an oxide layer, so that a shielded gate with a flat surface is formed after etching the polysilicon; thereby achieving the technical effect of ensuring that the device has better electrical properties; and finally forming a flat surface angle at the top of the gate, so that the groove angle can be 90°, ensuring that the thickness of the polysilicon shielded gate is greater than the thickness of the shielded gate when the groove angle is less than 89°, thereby achieving the technical effect of ensuring the shielded gate charge coupling capability of the SGT, and then ensuring the breakdown voltage of the device and avoiding breakdown. Furthermore, the device of this application avoids gaps, so the gate trench width can be reduced, so that when the distance between the gate trenches is constant, the device size can be further reduced.

[0067] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0068] Please refer to Figure 1-Figure 7 According to one embodiment of the present invention, a method for manufacturing a MOSFET device is provided. The flowchart of the method for manufacturing a MOSFET device is shown in FIG. Figure 1 As shown, the method includes:

[0069] S11: forming a MOSFET device structure having a gate trench; the MOSFET device structure includes a substrate and a bottom portion of the gate trench; the field oxide layer 102 is formed on the shielding gate and the epitaxial layer 101 on the substrate; the gate trench is formed in the epitaxial layer 101; the field oxide layer 102 is formed on the inner wall of the gate trench and the surface of the epitaxial layer 101 outside the gate trench, as shown in FIG. Figure 3 As shown;

[0070] S12: forming a shielding gate, wherein the shielding gate is formed at the bottom of the gate trench; wherein the field oxide layer 102 is formed between the shielding gate and the epitaxial layer 101. Of course, as in the conventional structure of the device in the prior art, a field oxide layer 102 is also formed on the inner wall of the gate trench at the top of the shielding gate; wherein the top of the shielding gate is a flat surface, as shown in FIG6 ;

[0071] S13: forming an inter-gate oxide layer 105 and a gate 106; the inter-gate oxide layer 105 is formed on the flat surface of the shielding gate, and the gate 106 is formed on the inter-gate oxide layer 105 and fills the top of the gate trench. Since the top of the shielding gate is a flat surface, the top of the gate 106 is also a flat surface. Figure 7 As shown;

[0072] S14: a body ion implantation layer 107 and a source ion implantation layer 108 are sequentially formed in the epitaxial layer 101 around the gate 106, an interlayer dielectric layer 109 and a metal aluminum layer 110 are sequentially formed on top of the gate 106, and a contact hole is formed; the contact hole penetrates the body ion implantation layer 107, the source ion implantation layer 108, the interlayer dielectric layer 109 and the edge of the metal aluminum layer 110 away from the gate 106, and the MOSFET device finally formed is as follows: Figure 2 shown.

[0073] The present invention provides a method for manufacturing a MOSFET device, which forms a shielding gate with a flat surface, and then forms an inter-gate oxide layer 105 on the top of the shielding gate, so that a gate 106 with a flat surface is formed on the top of the inter-gate oxide layer 105. It can be seen that the technical solution provided by the present invention solves the problem of how to manufacture a shielding gate with a flat surface, thereby achieving the technical effect of ensuring that the device has better electrical properties.

[0074] Furthermore, the problem of how to form a gate 106 with a smooth surface is solved; compared with the prior art, which forms a severe V-shaped shielding gate surface, the feature size of the device can be further reduced, while at the same time ensuring that the shielding gate of the smaller device structure has a certain thickness;

[0075] Thus, while the device feature size is further reduced, the shield gate charge coupling capability is maintained, thereby ensuring the device breakdown voltage and avoiding breakdown. Of course, the technical solution provided by the present invention can ensure that the shield gate of a smaller device structure has a certain thickness, so the feature size of the device manufactured using the technical solution provided by the present invention can be further reduced.

[0076] In one embodiment, step S12, forming the shielding gate specifically includes:

[0077] S121: depositing a gate material 103 in the gate trench; wherein the gate trench includes a gap, such as Figure 4 As shown;

[0078] S122: forming an oxide layer 104 in the gap, such as Figure 5 As shown;

[0079] When the gate material 103 is deposited, a gap is formed at the bottom of the gate trench. When the gate material 103 is etched, the gap is enlarged. Therefore, in step S122, an oxide layer 104 is formed in the gap to fill the gap. When etching, the etching selectivity of the gate material 103 and the oxide layer 104 is selected to form a shield gate with a smooth surface.

[0080] In one embodiment, in step S122, the oxide layer 104 is formed in the gap by performing low-temperature thermal oxidation on the gate material 103 in the gate trench, so that the oxide layer 104 is formed in the gap to fill the gap;

[0081] S123: removing the gate material 103 at the top of the gate trench and the gate material 103 on the surface of the epitaxial layer 101 outside the gate trench to form the shielding gate at the bottom of the gate trench; Figure 6 shown.

[0082] In a specific embodiment, in step S123, removing the gate material 103 at the top of the gate trench and the gate material 103 on the surface of the epitaxial layer 101 outside the gate trench to form the shielding gate at the bottom of the gate trench specifically includes:

[0083] The gate material 103 on the surface of the field oxide layer 102 outside the gate trench, the gate material 103 at the top of the gate trench, and the oxide layer 104 in the gap are etched to form the shielding gate with a smooth surface at the bottom of the gate trench.

[0084] In another specific embodiment, in step S123, removing the gate material 103 at the top of the gate trench and the gate material 103 on the surface of the epitaxial layer 101 outside the gate trench to form the shielding gate at the bottom of the gate trench specifically includes:

[0085] S1231: CMP polishing the gate material 103 deposited on the surface of the field oxide layer 102 outside the gate trench;

[0086] S1232: Etching the gate material 103 at the top of the gate trench and the oxide layer 104 in the gap to form the shielding gate with a smooth surface at the bottom of the gate trench.

[0087] In S1232, the etching flatness requirement of the top of the shielding gate is met. When etching the gate material 103 at the top of the gate trench and the oxide layer 104 in the gap, the etching flatness requirement is met by adjusting the etching rates of the gate material 103 and the oxide layer 104. In a preferred embodiment, the etching selectivity ratio of the gate material 103 and the oxide layer 104 is 75:1, so that a flat surface is formed on the top of the shielding gate after etching.

[0088] After the gate material 103 is oxidized, its volume expands, so the oxide layer 104 can serve as a good gap filling material.

[0089] In one embodiment, step S13, forming the inter-gate oxide layer 105 and the gate 106, specifically includes:

[0090] S131: forming the inter-gate oxide layer 105 on the top of the shielding gate;

[0091] S132: depositing a gate material 103 in the gate trench on top of the inter-gate oxide layer 105;

[0092] S133: etching the gate material 103 on the surface of the field oxide layer 102 outside the gate trench to form the gate 106; wherein the top of the gate 106 is a flat surface.

[0093] Secondly, according to an embodiment of the present invention, a MOSFET device is also provided, such as Figure 2 As shown; manufactured using the manufacturing method of the MOSFET device according to any one of the aforementioned embodiments of the present invention, comprising:

[0094] A MOSFET device structure with a gate trench, the MOSFET device comprising a substrate and an epitaxial layer 101 formed on the substrate; the gate trench is formed in the epitaxial layer 101; a field oxide layer 102 is formed on the inner wall of the gate trench and on the surface of the epitaxial layer 101 outside the gate trench;

[0095] A shielding gate is formed at the bottom of the gate trench; the field oxide layer 102 is formed between the shielding gate and the epitaxial layer 101; wherein the top of the shielding gate is a flat surface;

[0096] an inter-gate oxide layer 105 and a gate 106, wherein the inter-gate layer is formed on a flat surface of the shielding gate;

[0097] Body ion implantation layer 107, source ion implantation layer 108, interlayer dielectric layer 109, metal aluminum layer 110 and contact holes.

[0098] The present invention provides a MOSFET device, which forms a shielding gate with a flat surface, and then forms an inter-gate oxide layer 105 on the top of the shielding gate, so that a gate 106 with a flat surface is formed on the top of the inter-gate oxide layer 105; the problem of how to make a shielding gate with a flat surface is solved, thereby achieving the technical effect of ensuring that the device has better electrical properties. Further, the problem of how to form a gate 106 with a flat surface is solved; compared with the shielding gate surface that forms a severe V-shaped morphology in the prior art, the characteristic size of the device can be further reduced, and at the same time, the shielding gate of the smaller device structure can be guaranteed to have a certain thickness; thereby, while the characteristic size of the device is further reduced, the shielding gate charge coupling capability is guaranteed, and the breakdown voltage of the device is guaranteed to avoid breakdown. Of course, the technical solution provided by the present invention can ensure that the shielding gate of the smaller device structure has a certain thickness, so the characteristic size of the device made using the technical solution provided by the present invention can be further reduced.

[0099] The characteristic size of the MOSFET device manufactured using the technical solution provided by the present invention is between 0.5-0.8 um pitch.

[0100] In one embodiment, a gap is included under the flat surface of the shielding gate; and the gap is filled with an oxide layer.

[0101] In one embodiment, the top of the gate 106 is a flat surface.

[0102] Specifically, the gate material is polysilicon; the oxide layer 104 is silicon dioxide.

[0103] In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing the MOSFET device according to any one of the aforementioned embodiments of the present invention.

[0104] Finally, according to an embodiment of the present invention, an electronic device is provided, comprising the MOSFET device according to any one of the aforementioned embodiments of the present invention.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a MOSFET device, characterized in that: include: forming a MOSFET device structure having a gate trench; The MOSFET device structure includes a substrate and an epitaxial layer formed on the substrate; The gate trench is formed in the epitaxial layer; a field oxide layer formed on an inner wall of the gate trench and on a surface of the epitaxial layer outside the gate trench; forming a shielding gate, wherein the shielding gate is formed at the bottom of the gate trench; the field oxide layer is formed between the shielding gate and the epitaxial layer; wherein the top of the shielding gate is a flat surface; forming an inter-gate oxide layer and a gate; the inter-gate oxide layer is formed on the flat surface of the shielding gate, and the gate is formed on the inter-gate oxide layer and fills the top of the gate trench; A body ion implantation layer and a source ion implantation layer are sequentially formed in the epitaxial layer around the gate, an interlayer dielectric layer and a metal aluminum layer are sequentially formed on the top of the gate, and a contact hole is formed; the contact hole penetrates the body ion implantation layer, the source ion implantation layer, the interlayer dielectric layer, and an edge of the metal aluminum layer away from the gate; The forming of the shielding gate specifically includes: Depositing a gate material in the gate trench; wherein the gate trench includes a gap; forming an oxide layer in the gap by performing low-temperature thermal oxidation on the gate material in the gate trench, so that the oxide layer is formed in the gap to fill the gap; The gate material at the top of the gate trench and the gate material on the surface of the epitaxial layer outside the gate trench are removed to form the shielding gate at the bottom of the gate trench.

2. The method for manufacturing a MOSFET device according to claim 1, wherein: Removing the gate material at the top of the gate trench and the gate material on the surface of the epitaxial layer outside the gate trench to form the shielding gate at the bottom of the gate trench specifically includes: The gate material on the surface of the field oxide layer outside the gate trench, the gate material at the top of the gate trench and the oxide layer in the gap are etched to form the shielding gate with a flat surface at the bottom of the gate trench.

3. The method for manufacturing a MOSFET device according to claim 1, wherein: Removing the gate material at the top of the gate trench and the gate material on the surface of the epitaxial layer outside the gate trench to form the shielding gate at the bottom of the gate trench specifically includes: CMP polishing the gate material deposited on the surface of the field oxide layer outside the gate trench; The gate material at the top of the gate trench and the oxide layer in the gap are etched to form the shielding gate with a flat surface at the bottom of the gate trench.

4. The method for manufacturing a MOSFET device according to claim 2 or 3, wherein: The gate material at the top of the gate trench and the oxide layer in the gap are etched, with an etching selectivity ratio of the gate material to the oxide layer being 75:1, so that a flat surface is formed on the top of the shielding gate after etching.

5. The method for manufacturing a MOSFET device according to claim 4, wherein: Forming the inter-gate oxide layer and the gate specifically includes: forming the inter-gate oxide layer on the top of the shielding gate; Depositing a gate material in the gate trench on top of the inter-gate oxide layer; The gate material on the surface of the field oxide layer outside the gate trench is etched to form the gate; wherein the top of the gate is a flat surface.

6. A MOSFET device, characterized in that: The MOSFET device is manufactured using the manufacturing method of any one of claims 1 to 5, comprising: A MOSFET device structure having a gate trench, the MOSFET device comprising a substrate and an epitaxial layer formed on the substrate; the gate trench is formed in the epitaxial layer; a field oxide layer is formed on an inner wall of the gate trench and on a surface of the epitaxial layer outside the gate trench; A shielding gate is formed at the bottom of the gate trench; the field oxide layer is formed between the shielding gate and the epitaxial layer; wherein the top of the shielding gate is a flat surface; an intergate oxide layer and a gate, wherein the intergate layer is formed on a flat surface of the shielding gate; Body region ion implantation layer, source region ion implantation layer, interlayer dielectric layer, metal aluminum layer and contact holes.

7. The MOSFET device according to claim 6, wherein: A gap is provided under the flat surface of the shielding grid; the gap is filled with an oxide layer.

8. The MOSFET device according to claim 7, wherein: The top of the gate is a flat surface.

9. The MOSFET device according to claim 8, wherein: The gate is made of polysilicon.

10. The MOSFET device according to claim 9, wherein: The oxide layer is silicon dioxide.

11. The MOSFET device according to claim 9, wherein: The characteristic size of the MOSFET device is between 0.5-0.8 um pitch.

12. A method for manufacturing an electronic device, characterized in that: A method for manufacturing a MOSFET device comprising the steps of:

13. An electronic device, characterized in that: A MOSFET device comprising any one of claims 6 to 11.

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