Dual three-phase harmonic suppression transceiver

Abstract

An architecture for a dual three-phase transmitter and receiver is proposed that can achieve harmonic performance similar to that of an N-phase system with a higher N value while using a lower VCO frequency. A first three-phase clock signal and a second shifted three-phase clock signal are generated. Components of the first of these clock signals are each mixed with components of the three-phase input signal of the same phase, wherein the resulting three signals are mixed to form a first intermediate signal. Components of the second three-phase clock signal are each mixed with anti-phase components of the three three-phase input signals of the same phase, wherein the three signals are mixed to form a second intermediate signal. The intermediate signals can be amplified and combined separately to provide outputs. In a differential implementation, an n-side output can be generated similarly by switching the roles of the three-phase input and its inversion.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 032,591, filed on May 30, 2020 by Jiang et al., entitled “DUAL 3-PHASE HARMONICREJIECTION TRANSCEIVER,” which is incorporated by reference in its entirety. Technical Field

[0002] The present disclosure generally relates to architectures for reducing unwanted harmonic content in transceivers. Background Art

[0003] In wireless terminals such as cellular phones, there are often undesirable harmonic signals (harmonics) generated by the local oscillator clock that may interfere with signal processing. On the transmitter side, these harmonics can be mixed back to a carrier frequency close to the desired signal through nonlinearity and produce near-channel distortion and may affect other nearby wireless terminals using the same or nearly the same carrier frequency. On the receiver side, blocking signals at clock harmonic frequencies close to the desired signal can fall above the desired signal frequency through a down-conversion process when mixed back to the baseband frequency to reduce the signal-to-noise and distortion ratio of the received signal. It is desirable to minimize the impact of these clock harmonics as much as possible. Summary of the invention

[0004] According to one aspect of the present disclosure, a transmitter having a three-phase signal source is configured to provide three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals, and includes a frequency synthesizer and a harmonic rejection mixer. The frequency synthesizer is configured to generate a first three-phase clock signal having three clock signals, each of which has a phase corresponding to one of the input signals of the three-phase input signal, and to generate a second three-phase clock signal having three clock signals, each of which has a phase corresponding to one of the inverted input signals of the three-phase input signal. The harmonic rejection mixer includes: a first group of three mixers, each of which is configured to receive one of the clock signals of the first three-phase clock signal and mix one of the clock signals of the first three-phase clock signal with one of the input signals of the corresponding phase; and a second group of three mixers, each of which is configured to receive one of the clock signals of the second three-phase clock signal and mix one of the clock signals of the second three-phase clock signal with one of the inverted input signals of the corresponding phase. The harmonic rejection mixer is also configured to form a first intermediate signal by combining outputs of a first set of three mixers, to form a second intermediate signal by combining outputs of a second set of three mixers, and to combine the first intermediate signal and the second intermediate signal to form a first output signal of the harmonic rejection mixer.

[0005] Optionally, in the aforementioned aspect, the transmitter further comprises a first variable gain amplifier and a second variable gain amplifier. The first variable gain amplifier is configured to: receive the first intermediate signal; and amplify the first intermediate signal before combining the first intermediate signal and the second intermediate signal to form the first output signal of the harmonic rejection mixer. The second variable gain amplifier is configured to: receive the second intermediate signal; and amplify the second intermediate signal before combining the first intermediate signal and the second intermediate signal to form the first output signal of the harmonic rejection mixer.

[0006] Optionally, in any of the aforementioned aspects, the harmonic rejection mixer further includes a second mixing section, including: a third group of three mixers, each mixer being configured to receive one of the clock signals in the first three-phase clock signal and mix one of the clock signals in the first three-phase clock signal with an inverted input signal of one of the input signals of the corresponding phase; and a fourth group of three mixers, each mixer being configured to receive one of the clock signals of the second three-phase clock signal and mix one of the clock signals of the second three-phase clock signal with one of the inverted input signals of the corresponding phase as its inverted input signal. The harmonic rejection mixer is configured to: form a third intermediate signal by combining the outputs of the third group of three mixers, form a fourth intermediate signal by combining the outputs of the fourth group of three mixers, and combine the third intermediate signal and the fourth intermediate signal to form a second output signal of the harmonic rejection mixer.

[0007] Optionally, in the aforementioned aspect, the transmitter further includes an inductive coupler, comprising: a first coil configured to: receive a first output signal of the harmonic rejection mixer at a first terminal, and receive a second output signal of the harmonic rejection mixer at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single-ended output for the transmitter and a second terminal connected to ground.

[0008] Optionally, in the aforementioned aspect, the transmitter further comprises a power amplifier configured to receive and amplify the single-ended output.

[0009] Optionally, in the aforementioned aspect, the transmitter further comprises an antenna configured to receive and transmit a single-ended output.

[0010] Optionally, in any of the aforementioned aspects, the three-phase signal source is configured to receive an input signal in an in-phase / quadrature format and generate therefrom three input signals forming the three-phase input signal and an inverted input signal of each of the three input signals.

[0011] Optionally, in any of the aforementioned aspects, the frequency synthesizer includes: a voltage-controlled oscillator configured to generate an oscillator signal; a first three-phase generator configured to generate a first three-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and a second three-phase generator connected to the delay circuit and configured to generate a second three-phase clock signal from the delayed oscillator signal.

[0012] Optionally, in the aforementioned aspect, the frequency synthesizer comprises a phase-locked loop comprising a voltage-controlled oscillator.

[0013] Optionally, in any one of the two aforementioned aspects, the voltage-controlled oscillator is configured to generate an oscillator signal having a frequency that is 3 / 2 of a frequency of the three-phase clock signal.

[0014] Optionally, in the aforementioned aspect, the delay circuit introduces a 90° phase shift into the oscillator signal.

[0015] Optionally, in any one of the aforementioned two aspects, the frequency synthesizer is configured to generate a three-phase clock signal, wherein a duty cycle of each of the three clock signals is 1 / 3.

[0016] According to another aspect of the present disclosure, a method for sending a signal is provided, comprising: receiving three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals; receiving a first three-phase clock signal having three clock signals and a second three-phase clock signal having three clock signals, each of the three clock signals of the first three-phase clock signal having a phase corresponding to one of the input signals of the three-phase input signal, and each of the three clock signals of the second three-phase clock signal having a phase corresponding to one of the inverted input signals of the three-phase input signal; and generating a first output signal from the three input signals forming the three-phase input signal and the inverted input signal of each of the three input signals and from the first three-phase clock signal and the second three-phase clock signal. The first output signal is generated by the following operations: for each of the three clock signals of the first three-phase clock signal, mixing the clock signal with the input signal of the corresponding phase; for the three clock signals of the first three-phase clock signal, combining the mixed clock signal and the input signal to form a first intermediate signal; for each of the three clock signals of the second three-phase clock signal, mixing the clock signal with the inverted input signal of the corresponding phase; for the three clock signals of the second three-phase clock signal, combining the mixed clock signal and the inverted input signal to form a second intermediate signal; and combining the first intermediate signal and the second intermediate signal to generate the first output signal.

[0017] Optionally, in the aforementioned aspect, the method further comprises amplifying the first intermediate signal and the second intermediate signal respectively before combining the first intermediate signal and the second intermediate signal to generate the first output signal.

[0018] Optionally, in any one of the two aforementioned aspects, the method also includes: generating a second output signal from three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals and from a first three-phase clock signal and a second three-phase clock signal, by: for each of the three clock signals of the first three-phase clock signal, mixing the clock signal with an inverted input signal of a corresponding phase; for the three clock signals of the first three-phase clock signal, combining the mixed clock signal and the inverted input signal to form a third intermediate signal; for each of the three clock signals of the second three-phase clock signal, mixing the clock signal with one of the inverted input signals of a corresponding phase as its inverted input signal; for the three clock signals of the second three-phase clock signal, combining the mixed clock signal and the input signal to form a fourth intermediate signal; and combining the third intermediate signal and the fourth intermediate signal to generate a first output signal.

[0019] Optionally, in the aforementioned aspect, the method further includes: applying the first output signal and the second output signal to the first terminal and the second terminal of the first coil of the inductive coupler, respectively; receiving and amplifying the output from the second coil of the inductive coupler inductively coupled to the first coil; and sending the amplified output.

[0020] Optionally, in any of the aforementioned aspects of the method of sending a signal, the method also includes: receiving an input signal in an in-phase / quadrature format; and generating three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals from the input signal.

[0021] Optionally, in any of the aforementioned aspects of the method of sending a signal, the method also includes: generating an oscillator signal by a voltage-controlled oscillator; generating a first three-phase clock signal from the oscillator signal; delaying the oscillator signal; and generating a second three-phase clock signal from the delayed oscillator signal.

[0022] Optionally, in the aforementioned aspect, the voltage-controlled oscillator is configured to generate an oscillator signal having a frequency that is 3 / 2 of a frequency of the three-phase clock signal.

[0023] Optionally, in the aforementioned aspect, delaying the oscillator signal comprises introducing a 90° phase shift into the oscillator signal.

[0024] Optionally, in any of the aforementioned three aspects, the method also includes: generating a first three-phase clock signal, wherein the duty cycle of each of the three clock signals is 1 / 3; and generating a second three-phase clock signal, wherein the duty cycle of each of the three clock signals is 1 / 3.

[0025] According to an additional aspect of the present disclosure, a receiver includes: a frequency synthesizer configured to generate a first three-phase clock signal having three clock signals; and a second three-phase clock signal having three clock signals, the three clock signals of the second three-phase clock including a clock signal having a 180° phase shift with one of the three clock signals of the first three-phase clock signal; and a harmonic rejection mixer. The harmonic rejection mixer includes a first mixing section, the first mixing section including: a first group of three mixers, each mixer configured to receive and mix one of the clock signals of the first three-phase clock signal and an input signal to generate one of the three signals of a three-phase first output signal; and a second group of three mixers, each mixer configured to receive and mix one of the clock signals of the second three-phase clock signal and an input signal to generate one of the three signals of a three-phase second output signal, each of the second output signals being an inversion of a corresponding signal of the first three-phase output signal.

[0026] Optionally, in the aforementioned aspect, the receiver further comprises a differential three-phase to quadrature converter configured to receive the first three-phase output signal and the second three-phase output signal and convert the first three-phase output signal and the second three-phase output signal into an in-phase / quadrature format.

[0027] Optionally, in any of the aforementioned aspects of the receiver, the receiver also includes: a first low-noise amplifier, which is configured to receive and amplify an input signal; and provide the amplified input signal to a first group of three mixers; and a second low-noise amplifier, which is configured to receive and amplify the input signal; and provide the amplified input signal to a second group of three mixers.

[0028] Optionally, in the aforementioned aspect, the first low noise amplifier and the second low noise amplifier are configured to provide an amplified input signal as a differential output, and the first group of three mixers and the second group of three mixers respectively receive the positive side outputs of the first low noise amplifier and the second low noise amplifier: the harmonic suppression mixer also includes: a second mixing part, the second mixing part includes: a third group of three mixers, each mixer is configured to receive and mix one of the clock signals of the first three-phase clock signal and the negative side output of the first low noise amplifier to generate one of the three signals of the three-phase negative side first output signal; and a fourth group of three mixers, each mixer is configured to receive and mix one of the clock signals of the second three-phase clock signal and the negative side output of the low noise amplifier to generate one of the three signals of the three-phase negative side second output signal, each signal in the negative side second output signal is the inversion of the corresponding signal of the first negative side three-phase output signal.

[0029] Optionally, in any one of the two aforementioned aspects of the receiver, the receiver further comprises an antenna configured to receive an input signal and provide it to the first low noise amplifier and the second low noise amplifier.

[0030] Optionally, in any of the aforementioned aspects of the receiver, the frequency synthesizer includes: a voltage-controlled oscillator configured to generate an oscillator signal; a first three-phase generator configured to generate a first three-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and a second three-phase generator connected to the delay circuit and configured to generate a second three-phase clock signal from the delayed oscillator signal.

[0031] Optionally, in the aforementioned aspect, the frequency synthesizer comprises a phase-locked loop comprising a voltage-controlled oscillator.

[0032] Optionally, in any one of the aforementioned two aspects of the receiver, the voltage-controlled oscillator is configured to generate an oscillator signal having a frequency that is 3 / 2 of a frequency of the three-phase clock signal.

[0033] Optionally, in the aforementioned aspect, the delay circuit introduces a 90° phase shift into the oscillator signal.

[0034] Optionally, in any one of the aforementioned two aspects of the receiver, the frequency synthesizer is configured to generate a three-phase clock signal, wherein a duty cycle of each of the three clock signals is 1 / 3.

[0035] According to another aspect of the present disclosure, a method for receiving a signal is provided, comprising: receiving an input signal; receiving a first three-phase clock signal having three clock signals and a second three-phase clock signal having three clock signals, each of the three clock signals of the first three-phase clock signal having a phase corresponding to one of the input signals of the three-phase input signal, and each of the three clock signals of the second three-phase clock signal having a phase corresponding to one of the inverted input signals of the three-phase input signal; and generating three first output signals forming a three-phase first output signal and an inverted output signal of each of the three first output signals from the input signal and from the first three-phase clock signal and the second three-phase clock signal, each of the three first output signals having a phase corresponding to one of the three clock signals. The three first output signals are generated by the following operations: for each of the three clock signals of the first three-phase clock signal in a corresponding one of the first group of three mixers, the clock signal is mixed with the input signal to generate a three-phase first output signal; and for each of the three clock signals of the second three-phase clock signal in a corresponding one of the second group of three mixers, the clock signal is mixed with the input signal to generate an inverted output signal of each of the three first output signals.

[0036] Optionally, in the aforementioned aspect of the method of receiving a signal, the method further includes converting the three-phase first output signal and an inverted output signal of each of the three first output signals into an in-phase / quadrature format.

[0037] Optionally, in any of the aforementioned aspects of the method for receiving a signal, the method also includes: amplifying the input signal in a first low-noise amplifier and a second low-noise amplifier, respectively; providing the amplified input signal from the first low-noise amplifier to be mixed with a corresponding first three-phase clock signal to generate a three-phase first output signal; and providing the amplified input signal from the second low-noise amplifier to be mixed with a corresponding second three-phase clock signal to generate an inverted output signal for each of the three first output signals.

[0038] Optionally, in the aforementioned aspect, the first low noise amplifier and the second low noise amplifier are configured to provide an amplified input signal as a differential output, and the first group of three mixers and the second group of three mixers respectively receive the positive side outputs of the first low noise amplifier and the second low noise amplifier, and the method also includes: for each of the three clock signals of the first three-phase clock signal in a corresponding one of the third group of three mixers, mixing the clock signal with the negative side output of the first low noise amplifier to generate one of the three signals of the three-phase negative side first output signal; and for each of the three clock signals of the second three-phase clock signal in a corresponding one of the fourth group of three mixers, mixing the clock signal with the negative side output of the low noise amplifier to generate one of the three signals of the three-phase negative side second output signal, each of the negative side second output signals is the inversion of the corresponding signal of the first negative side three-phase output signal.

[0039] Optionally, in any one of the two aforementioned aspects, the method further comprises receiving an input signal from an antenna and providing it to the first low noise amplifier and the second low noise amplifier.

[0040] Optionally, in any of the aforementioned aspects of the method for receiving a signal, the method further includes: generating an oscillator signal by a voltage-controlled oscillator; generating a first three-phase clock signal from the oscillator signal; delaying the oscillator signal; and generating a second three-phase clock signal from the delayed oscillator signal.

[0041] Optionally, in the aforementioned aspect, the voltage-controlled oscillator is configured to generate an oscillator signal having a frequency that is 3 / 2 of a frequency of the three-phase clock signal.

[0042] Optionally, in the aforementioned aspect, delaying the oscillator signal comprises introducing a 90° phase shift into the oscillator signal.

[0043] Optionally, in any of the aforementioned three aspects of the method for receiving a signal, the method also includes: generating a first three-phase clock signal, wherein a duty cycle of each of the three clock signals is 1 / 3; and generating a second three-phase clock signal, wherein a duty cycle of each of the three clock signals is 1 / 3.

[0044] This summary is provided to introduce a series of concepts in a simplified form, which are further described below in the detailed description. This summary is neither intended to identify the key features or essential features of the claimed subject matter nor to help determine the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all of the shortcomings noted in the background technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Aspects of the present disclosure are illustrated by way of example and not limitation in the accompanying figures, in which like reference numerals indicate elements.

[0046] Figure 1 A wireless network for communicating data is shown.

[0047] Figure 2 It can be used in Figure 1 Block diagram of a wireless communication system used in a network in FIG.

[0048] Figure 3 is a block diagram of a first embodiment of a dual three-phase transmitter showing improved harmonic suppression.

[0049] Figure 4 It shows the Figure 3 Timing diagram of each clock and its duty cycle for the frequency synthesizer block.

[0050] Figure 5 Shows Figure 3 Simulation results of the performance of the power amplifier of the implementation scheme.

[0051] Figure 6 It is shown Figure 3 Flowchart of a first embodiment of the operation of a transceiver in an embodiment of the present invention.

[0052] Figure 7 is a block diagram of a first embodiment of a dual three-phase receiver showing improved harmonic suppression.

[0053] Fig. 8A An example of a strong blocking frequency present at the second harmonic of the carrier frequency of the desired receiver signal is shown.

[0054] Figure 8B Shows Figure 7 The receiver is targeted at Fig. 8A The output of the input.

[0055] Fig. 9 It is shown Figure 7 A flowchart of an implementation of the operation of a receiver in an implementation. DETAILED DESCRIPTION

[0056] The present disclosure will now be described with reference to the accompanying drawings, Figure 1Generally relates to techniques for reducing unwanted harmonic content from transmitters and receivers. The following dual three-phase transmitter and receiver embodiments are proposed, which can generate a local oscillator clock signal from a voltage-controlled oscillator operating at a frequency of 3 / 2 of the local oscillator frequency, and can reduce unwanted harmonics at a level that usually requires the voltage-controlled oscillator to operate at twice the local oscillator frequency (or higher). In the architecture described below, a first three-phase clock signal and a second shifted three-phase clock signal are generated. The components of the first clock signal of these clock signals are each mixed with the components of the three-phase input signal of the same phase, wherein the resulting three signals are mixed to form a first intermediate signal. The components of the second three-phase clock signal are each mixed with the anti-phase components of the three three-phase input signals of the same phase, wherein the resulting three signals are mixed to form a second intermediate signal. The two intermediate signals can be amplified and combined to provide outputs respectively. In a differential embodiment, the n-side output can be generated similarly by switching the roles of the three-phase input and its anti-phase.

[0057] It should be understood that the current embodiments of the present disclosure can be implemented in many different forms, and the scope of the claims should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments fully convey the embodiments of the present disclosure to those skilled in the art. In fact, the present disclosure is intended to cover substitutions, modifications and equivalents of these embodiments within the scope and spirit of the present disclosure as defined by the appended claims. In addition, in the following detailed description of the current embodiments of the present disclosure, many specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the current embodiments of the present disclosure can be practiced without such specific details.

[0058] Figure 1 A wireless network for transmitting data is shown. The communication system 10 includes, for example, user equipment 11A to 11C, radio access networks (RAN) 12A to 12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private data packet networks and public data packet networks, including corporate intranets. Although a specific number of these components or elements are shown in the figure, any number of these components or elements may be included in the system 10.

[0059] In one embodiment, the wireless network may be a fifth generation (5G) network, the 5G network including at least one 5G base station, the 5G base station using orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (ms) (e.g., 100 or 200 microseconds) to communicate with a communication device. In general, reference to a base station may refer to any of an eNB and a 5G base station (gNB). In addition, the network may also include a network server for processing information received from a communication device via at least one eNB or gNB base station.

[0060] The system 10 enables multiple wireless users to transmit and receive data and other content. The system 10 may implement one or more channel access methods such as, but not limited to, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0061] User equipment (UE) 11A to 11C are configured to operate and / or communicate in the system 10. For example, the user equipment 11A to 11C are configured to send and / or receive wireless signals or wired signals. Each user equipment 11A to 11C represents any suitable end-user device, and may include such devices (or may be referred to as): user equipment / device, wireless transmit / receive unit (UE), mobile station, fixed or mobile user unit, pager, cellular phone, personal digital assistant (PDA), smart phone, laptop computer, computer, touch pad, wireless sensor, wearable device or consumer electronic device.

[0062] In the depicted embodiment, the RANs 12A to 12B include one or more base stations 17A, 17B (collectively referred to as base stations 17), respectively. Each of the base stations 17 is configured to wirelessly interface with one or more of the UEs 11A, 11B, 11C to enable access to the core network 13, the PSTN 14, the Internet 15, and / or other networks 16. For example, the base station (BS) 17 may include one or more of some well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (evolved NodeB, eNB), a next generation (fifth generation) (5G) NodeB (gNB), a home NodeB, a home eNodeB, a site controller, an access point (AP), or a wireless router or a server, a router, a switch, or other processing entity with a wired or wireless network.

[0063] In one embodiment, base station 17A forms part of RAN 12A, which may include other base stations, elements and / or devices. Similarly, base station 17B forms part of RAN 12B, which may include other base stations, elements and / or devices. Each of base stations 17 operates to send and / or receive wireless signals within a specific geographic area or region (sometimes referred to as a "cell"). In some embodiments, multiple-input multiple-output (MIMO) technology with multiple transceivers for each cell may be employed.

[0064] The base station 17 communicates with one or more of the user equipment 11A to 11C over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology.

[0065] It is envisioned that the system 10 may use multi-channel access functionality, including, for example, a solution in which the base station 17 and the user equipment 11A to 11C are configured to implement the Long Term Evolution (LTE), LTE Advanced (LTE-A) and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base station 17 and the user equipment 11A to 11C are configured to implement UMTS, HSPA or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may also be used.

[0066] The RANs 12A to 12B communicate with the core network 13 to provide voice, data, applications, voice over Internet Protocol (VoIP) or other services to the user devices 11A to 11C. It should be understood that the RANs 12A to 12B and / or the core network 13 may communicate directly or indirectly with one or more other RANs (not shown). The core network 13 may also serve as a gateway access to other networks such as the PSTN 14, the Internet 15, and other networks 16. In addition, some or all of the user devices 11A to 11C may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and / or protocols.

[0067] The RANs 12A to 12B may also include millimeter and / or microwave access points (APs). The APs may be part of the base station 17 or may be located remote from the base station 17. The APs may include, but are not limited to, connection points (mmW CPs) or base stations 17 capable of mmW communications (e.g., mmW base stations). The mmW APs may send and receive signals in a frequency range of, for example, from 24 GHz to 100 GHz, but are not required to operate throughout the range. As used herein, the term base station is used to refer to a base station and / or a wireless access point.

[0068] although Figure 1 An example of a communication system is shown, but the Figure 1 Various changes may be made. For example, the communication system 10 may include any number of user equipment, base stations, networks or other components of any appropriate configuration. It should also be understood that the term user equipment may refer to any type of wireless device that communicates with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target devices, device-to-device (D2D) user equipment, machine-type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptop computers, PDAs, iPads, tablet computers, mobile terminals, smart phones, laptop embedded equipped (laptop embedded equipped, LEE), laptop mounted equipment (laptop mounted equipment, LME) and USB dongles.

[0069] Figure 21 is a block diagram of a wireless communication system 100, such as a mobile handset or user equipment 11A to 11C or a base station 17, showing some of the elements discussed with respect to the following figures. To transmit an output signal from the circuit elements of the processor 111, the transmitter (transmitter, Tx) RF / analog section 101 up-converts the output signal from a baseband or intermediate frequency (IF) range to a radio frequency (RF) range according to the structure of the Tx digital baseband block 107, and also amplifies and filters the output transmit signal before providing the transmit signal to the antenna 105. The transmitter (Tx) RF / analog section 101 may also be configured to perform other processing to prepare the output transmit signal. The output signal generated by the Tx digital baseband block 107 is in an in-phase / quadrature (I / Q) format as an in-phase signal I Tx and the quadrature signal Q Tx is provided to the Tx RF / Analog section 101. Although the Tx digital baseband block 107 Figure 2 1. Although shown as separate blocks from the Tx RF / Analog portion 101 in FIG. 1 , these elements may be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination of these, depending on the implementation.

[0070] The signal is received by antenna 105 and provided to a receiver (Rx) RF / analog section 102. The Rx section 102 performs any necessary or desired signal processing, such as down-conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering, before passing the signal to other elements on the device represented at processor 111. Figure 2 In the embodiment of the present invention, the output of the Rx RF / analog section 102 is in I / Q format, and the Rx digital baseband section 117 converts it into a received signal provided to the processor. Figure 2 102, but depending on the implementation, these elements may be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination of these. Figure 2 The Tx RF / analog section 101 and the Rx RF / analog section 102 are shown as separate elements, but depending on the implementation, the transmitter and receiver paths may share many elements or be implemented as a combined transceiver. Hereinafter, "transceiver" may be used generally to refer to a combined transmitter / receiver, separate transceiver and receiver sections, or implementations in which one or more components (e.g., a local oscillator) are shared between the transmitter and receiver.

[0071] In transceivers such as mobile phones, it is common to have unwanted clock harmonics generated from the local oscillator. On the transmitter side, these clock harmonics can be mixed back to frequencies close to the desired signal through nonlinearity and produce close-channel distortion (e.g., CIM2, CIM3, CIM5, where CIMx is the x-order counter intermodulation), and also affect other nearby wireless terminals using close carrier frequencies. On the receiver side, blocking signals at frequencies close to the clock harmonics of the desired signal may fall above the desired signal frequency when down-converted when mixed back to the baseband frequency and degrade the received signal. Therefore, it is desirable to reduce the impact of these unwanted clock harmonics as much as possible.

[0072] Typically, some of these unwanted harmonics can be removed by a multiphase (N-phase) mixer design, where N is appropriately chosen, where the higher the value of N, the more harmonics will be removed. Thus, a high value of N is preferred for harmonic suppression. However, for an N-phase mixer design, a high value of N requires the oscillator (e.g., a voltage controlled oscillator or VCO) to operate at a high frequency. (Typically, the minimum VCO frequency is f LO *N / 2, where f LO is the local oscillator carrier frequency. ) This results in high power dissipation in the VCO and can make VCO design challenging.

[0073] An implementation of a harmonic rejection mixer (HRM) mixer is given below, which can operate at a lower value of N=3, thereby reducing the VCO frequency requirements while suppressing more harmonics than a conventional three-phase HRM. In order to transmit orthogonal IQ signals (signals in in-phase / quadrature or IQ format), a minimum value of N=3 is used, i.e., a three-phase system. Due to the smaller value of N, a three-phase system is generally preferred. For 5G cellular systems, the carrier frequency (as currently defined) can be 7.15GHz. With a three-phase system, the VCO can operate as low as fcarrier*N / 2=7.15GHz*3 / 2=10.725GHz, which is not difficult to design. However, conventional three-phase systems do not suppress the second clock harmonic and the fourth harmonic, which will be converted to CIM2 / CIM4 in the transmitter case by a single-ended power amplifier and may not meet the specifications of certain standards. In addition, depending on the front-end configuration, the second harmonic itself may cause the transmitter system to fail to meet the spurious emission specifications at the second harmonic frequency.

[0074] The following are embodiments of a transmitter and receiver that use a three-phase system while suppressing more clock harmonics than a standard three-phase system. Even though the standard three-phase system has the advantage of lowering the maximum operating frequency of the voltage controlled oscillator, the lack of suppression of the second and fourth harmonics is a serious problem and makes the standard three-phase not very useful in cellular systems. The embodiments given below use a dual three-phase system in which the two three-phase systems are offset by 60 degrees from each other. In this dual three-phase system, the VCO can be operated at a frequency of 3 / 2 the carrier frequency (f VCO =fcarrier*3 / 2) while suppressing the second, third and fourth harmonics. This means that the dual three-phase system has the harmonic suppression characteristics of a six-phase system, while the maximum frequency of the VCO is only the maximum frequency of a standard three-phase system. Figure 3 is a block diagram showing the basic concept.

[0075] Figure 3 is a block diagram of a first embodiment of a dual three-phase transmitter exhibiting improved harmonic suppression. Considering a high level Figure 3 , you can Figure 2 The IQ source 107 generated within the Tx digital baseband block 107 provides the signal to be transmitted. The signal from the IQ source 107 is in I / Q format and, as described below, is converted into a differential three-phase signal in a three-phase signal source 241, the components of which provide the source signal in analog three-phase format to the harmonic suppression block HRM 200. The frequency synthesizer 230 provides a dual three-phase clock signal to the HRM 200. The output of the HRM 200 is provided to the antenna 105 through a set of variable gain amplifiers VGA221-i and VGA 223-i, an inductive coupler 251, a power amplifier PA 253 and a filter 255.

[0076] In the IQ signal path, the IQ data from the IQ source 107 is digitally converted into a set of three-phase baseband signals (0, 120, 240) in the conversion block 243. Then, three digital to analog converters (DAC) DAC_0 245-1, DAC_120 245-2 and DAC_240 245-3 convert the three-phase digital signals into analog signals, which are then filtered by low pass filters (LPF) LPF_0 247-1, LPF_120 247-2 and LPF_240 247-3 to remove unwanted distortion and noise. Typically, the DAC and LPF are differential circuits that are relatively unaffected by other noise sources within the transceiver. This means that in addition to the 0, 120 and 240 signals, complementary signals (180, 300, 60) are created and provided to the HRM 200. Components 107 , 243 , 245 - 1 , 245 - 2 , 245 - 3 , 247 - 1 , 247 - 2 , and 247 - 3 together form a differential three-phase signal source 241 .

[0077] In the block of frequency synthesizer 230, VCO 231 can be part of phase-locked loop PLL 233. The VCO can operate at a frequency fVCO=1.5*fLO, where fLO is the local oscillator frequency or carrier frequency. The VCO output is fed to the first three-phase clock generation block 235 to generate clk0, clk120, and clk240. The VCO output is also fed to the 90 degree phase shift block 237 and then fed to the second three-phase generation block 239. Since the three-phase generation block 239 is basically a division by 1.5 operation, the initial 90 degree phase shift will become 60 degrees at the final carrier frequency, which means that clk60, clk180, and clk300 will be generated in block 239. For all six clocks (clk0, clk120, clk240, clk60, clk180 and clk300), in this embodiment, the duty cycle of each clock is 33.33%, so the three clock signals from each of the generation blocks 235 and 239 are non-overlapping and add up to 100%, but the clocks form different blocks overlap.

[0078] Figure 4 is a timing diagram showing each clock from the frequency synthesizer block 230 and its duty cycle. Figure 4 As shown, clk0, clk120 and clk240 form a first set of non-overlapping signals of the three-phase clock signal, and clk60, clk180 and clk300 form a second set of non-overlapping signals of the three-phase clock signal. All six clocks are combined, and they are overlapping clocks.

[0079] Return to Figure 3 , the two p-side intermediate outputs of HRM 200 each enter a corresponding one of VGA 221-1 or VGA-2 221-2. The input to each of these VGAs is the combined output from a set of three mixers, each of which receives one of a set of clock signals from a three-phase generator block 235 or a three-phase clock generator block 239: the input to VGA 221-1 is the combined output of mixer 201 receiving clk0, mixer 202 receiving clk120, and mixer 203 receiving clk240 to produce a first p-side intermediate output; and the input to VGA 221-2 is the combined output of mixer 204 receiving clk60, mixer 205 receiving clk300, and mixer 206 receiving clk180 to produce a second p-side intermediate output. As described above, each of these clock signals has a duty cycle of 1 / 3 or 33%, and are non-overlapping, but add up to 100%.

[0080] A similar arrangement is used for the n-side intermediate outputs of HRM 200, each of which goes into a corresponding VGA 223-1 or one of the VGA-3223-2. The input to each of these VGAs is the combined output from a set of three mixers, each of which receives one of a set of clock signals from a three-phase generator block 235 or a three-phase clock generator block 239: the input to VGA 223-1 is the combined output of mixer 211 receiving clk0, mixer 212 receiving clk120, and mixer 213 receiving clk240 to produce a first n-side intermediate output; and the input to VGA 221-2 is the combined output of mixer 214 receiving clk60, mixer 215 receiving clk300, and mixer 216 receiving clk180 to produce a second n-side intermediate output. As mentioned above, each of these clock signals has a duty cycle of 1 / 3 or 33%, and are non-overlapping, but add up to 100%.

[0081] The harmonic rejection mixer (HRM) 200 combines the output of the LPF with the signal of the dual three-phase LO clock to generate an RF output. Figure 3 As shown, on the p-side, the signals of the three-phase outputs 0, 120 and 240 from the corresponding LPFs 247-1, 247-2 and 247-3 are each mixed with a clock signal of the same phase as the first three-phase clock signal in a corresponding one of the first group of mixers 201, 202 and 203. Likewise, on the p-side, the inverted input signals 180, 300 and 60 from the three-phase outputs of the corresponding LPFs 247-1, 247-2 and 247-3 are each mixed with a clock signal of the same phase as the second three-phase clock signal in a corresponding one of the first group of mixers 206, 205 and 204.

[0082] The n-side of the HRM 200 is arranged similarly to the p-side, but the outputs from each of the LPFs are swapped so that the input signals are mixed with clock signals of opposite phases. In the first set of n-side mixers, the inverted inputs 180, 300, and 60 of the three-phase input signal are mixed with clk0 in mixer 211, clk120 in mixer 212, and clk240 in mixer 213, respectively. In the second set of n-side mixers, the inputs 0, 120, and 240 of the three-phase input signal are mixed with clock signals of the second three-phase clock signal corresponding to the opposite phases of clk180 in mixer 216, clk300 in mixer 215, and clk60 in mixer 214, respectively.

[0083] The RF intermediate outputs from the p-side mixers are amplified and combined by VGAs 221-1 and 221-2 to provide a p-side output signal from the HRM 200, and the RF intermediate outputs from the n-side mixers are similarly amplified and combined by VGAs 223-1 and 223-2 to provide an n-side output signal from the HRM 200. In order to convert the RF outputs from the VGAs to single-ended outputs, an inductive coupler 251 may be used, wherein the combined p-side output and the combined n-side output are connected across a first coil of the inductive coupler 251 and a second coil of the inductive coupler 251, one side of the second coil of the inductive coupler being set to ground and the other side providing a single-ended signal at the output. The power amplifier PA 253 amplifies the single-ended output, and the PA output is filtered by an RF filter 255 to remove unwanted distortion. Finally, the filtered RF output is fed to the antenna 105 for transmission.

[0084] Typically, the mixers within the HRM 200 are passive mixers in cellular applications, which means that overlapping clocks can cause crosstalk between different paths. To avoid this, Figure 3 The use of segmented VGAs 221-1, 221-2, 223-1, and 223-2 is shown so that each individual path has non-overlapping clocks.

[0085] Figure 5 Shows Figure 3 More specifically, Figure 5 The graph of FIG. 1 plots the output at the output of the three-phase power amplifier as a function of frequency, normalized in decibels (dB) such that the desired transmitter (Tx) signal is 0 dB. Figure 5 In the graph, for fast simulation purposes, the desired signal frequency (about 1.2288×10 8Hz) is chosen to be lower than the actual RF target frequency. In the simulation, the 90 degree phase shift block 237 is assumed to be non-ideal (85 degrees is used). In addition to the desired Tx signal, there is a peak drop of about -60dB due to LO leakage and more than -80dB due to image distortion at a slightly lower frequency. The CIM2n and CIM4p spikes are generated due to non-ideal delay values. In summary, it shows that CIM distortion can be significantly reduced even for non-ideal implementations if properly managed.

[0086] Regarding harmonics, for the second-order counter intermodulation, Figure 5 It is shown that the peak CIM2p on the positive side is down by -80dB, the peak CIM2n on the negative side is down by about -60dB, and CIM4p is down by about -90dB. If the phase shift in the phase shift block 237 is close to 90 degrees, these CIM values ​​will be further reduced. There is no third order CIM3 peak, and the only other significant spike is CIM5, which is down by about -100dB. Therefore, Figure 5 The simulation results show that Figure 3 The performance at the output of the dual three-phase HRM architecture power amplifier PA 253 can achieve harmonic suppression comparable to that of a standard six-phase HRM. The spectrum of the system shows that the levels of all CIM distortions are low enough for cellular applications.

[0087] Figure 6 It is shown Figure 3 Flowchart of a first embodiment of the operation of the transceiver in the embodiment of . At 601, the HRM receives N components of N-phase input signals and the inverse of these input signals from the three-phase signal source 241. Figure 3 In an embodiment of the present invention, this includes components of the three-phase input signal (0, 120, 240) and the inverse of these input signals (180, 300, 60). Figure 3 In the embodiment of the present invention, these signals are generated by the three-phase conversion blocks DAC 245-1, 245-2, 245-3 and LPF 247-1, 247-2, 247-3 according to the I / Q signal of the IQ source 107.

[0088] At 603, the frequency synthesizer 230 generates an LO clock signal, and the HRM 200 receives the LO clock signal. The LO clock signal includes three components of the first three-phase clock signal and three components of the second three-phase clock signal. Figure 3In the embodiment of the present invention, the first three-phase clock signal is the clock signals Clk0, Clk120 and Clk240 from the generator block 235, all of which have a duty cycle of 1 / 3, and the second three-phase clock signal is offset by 60 degrees from the first three-phase signal and is the clock signals Clk60, Clk180 and Clk300 from the generator block 239, all of which have a duty cycle of 1 / 3. Figure 6 The flowchart of 601 presents its elements in a particular sequence, but it will be understood that these can all be performed simultaneously (i.e., 601, 603 and subsequent elements are performed simultaneously during operation) to Figure 3 The circuit generates an output signal when it is sent.

[0089] At 605, each clock signal of the first three-phase clock signal is mixed with an input signal of a corresponding phase. Figure 3 In the embodiment of the present invention, in the first set of mixers on the p-side of HRM 200, the input signal components (0, 120, 240) are mixed with the three-phase components (clk0, clk120, clk240) in mixers 201, 202 and 203, respectively. At 607, the outputs of the mixers are combined to form a first intermediate signal on the p-side, which is then amplified in VGA 221-1.

[0090] 609 and 611 are performed simultaneously with 605 and 607. At 609, each clock signal of the second three-phase clock signal is mixed with the inverted input signal of the corresponding phase. Figure 3 In the embodiment of the present invention, in the second set of mixers on the p-side of HRM 200, the shifted input signal components (60, 300, 180) are mixed with the second three-phase components (clk60, clk300, clk180) in mixers 204, 205 and 206, respectively. At 611, the outputs of these mixers are combined to form a second intermediate signal on the p-side, which is then amplified in VGA 221-2. Figure 3 In a double-sided implementation of , two n-side intermediate outputs are generated as described above to complement 605 to 611.

[0091] At 613, Figure 3 In a double-sided embodiment, the first intermediate signal and the second intermediate signal are combined to generate an output signal of the p-side of the HRM 200. The outputs of the VGAs 221-1 and 221-2 are combined to provide an output signal of the p-side of the HRM 200. Figure 3 In a double-sided embodiment of , on the n-side, the intermediate outputs are similarly combined to provide the output signal of the n-side of the HRM 200.

[0092] The output signal is then sent in 615. Figure 3In the double-sided embodiment of , the p-side and n-side outputs are converted to single-sided outputs at the coil of the inductive coupler 251. The single-sided output is then amplified in the power amplifier PA 253, filtered at the filter 255, and then transmitted from the antenna 105.

[0093] As described, the techniques described herein use a dual three-phase transmitter system for better harmonic suppression than a standard three-phase transmitter system. The dual three-phase transmitter system can achieve similar performance in terms of harmonic suppression as a standard six-phase transmitter system. In addition, the dual three-phase system only requires the VCO to run at 1.5 times the carrier frequency or local oscillator frequency, rather than three times the carrier frequency required by the standard six-phase system, which reduces VCO design complexity and power consumption.

[0094] Figure 7 is a block diagram of an embodiment of a dual three-phase receiver system that suppresses blockers at or near the second, third, and fourth clock harmonics. Figure 7 The overall structure of the receiver implementation is similar to Figure 3 The transmitter implementation of FIG. 1 is shown in FIG. 1 , except that the signal paths are roughly inverted. In the receiver implementation presented here, segmented low noise amplifiers (LNAs) are used to avoid overlapping crosstalk.

[0095] More specifically, the frequency synthesizer 730 may have Figure 3 The frequency synthesizer 230 has the same or similar structure, wherein the VCO 731, the PLL 733, the first three-phase generation block 735, the delay block 737 and the second three-phase generation block 739 can operate as described above with respect to the corresponding elements 231, 233, 235, 237 and 239.

[0096] Instead of receiving a three-phase input signal and the inverse of its components, the HRM 700 now generates a three-phase output signal (0, 120, 240), and because Figure 7Also being a double-sided implementation, an inverted value (180, 300, 60) of the three-phase output is also generated. The complementary output signal pairs are used as differential inputs to a set of low-pass filters and analog-to-digital converters. More specifically, the (0, 180) pair is a differential input to LPF_0 747-1, the output of which then enters ADC_0 745-1 to provide the (single-ended) first (0 degree phase) component of the three-phase output. Similarly, the (120, 300) pair is the differential input to LPF_120 747-2, the output of which then enters ADC_120 745-2 to provide a (single-ended) second (120 degree phase) component of the three-phase output; and the (240, 60) pair is the differential input to LPF_240 747-3, the output of which then enters ADC_240745-3 to provide a (single-ended) third (240 degree phase) component of the three-phase output.

[0097] The input to HRM 700 comes from segmented LNAs of LNA 721-1 and LNA-2 721-2, each connected through RF filter 755 to receive a signal from antenna 105. The outputs of LNAs 721-1 and 721-2 are differential, with the p-side output of each going to a corresponding set of p-side mixers in HRM 700, and the n-side output of each going to a corresponding set of n-side mixers in HRM 700.

[0098] In HRM 700, the p-side output from LNA 921-1 enters the first set of p-side mixers 701, 702, and 703 to be mixed with clk0, clk120, and clk240, respectively, to generate output components 0, 120, and 240. The n-side output from LNA 921-1 enters the first set of p-side mixer pairs 711, 712, and 713 to be mixed with clk0, clk120, and clk240, respectively, to generate output components 180, 300, and 60, to generate reverse differential output components 180, 300, and 60.

[0099] Similarly, the p-side output from LNA 921-2 enters the second first group of n-side mixers 711, 712, and 713 to be mixed with clk0, clk120, and clk240, respectively, to generate output components 60, 300, and 180. The n-side output from LNA 921-1 enters the second group of n-side mixer pairs 714, 715, and 716 to be mixed with clk60, clk300, and clk180, respectively, to generate output components 60, 300, and 180, to generate reverse differential output components 240, 300, and 180.

[0100] For the receiver, the problem to be solved is that the maximum VCO frequency of the receiver is required to be at 1.5 times the carrier frequency when there is a strong blocker (i.e., an interfering signal such as another nearby cellular phone) at the antenna that is a harmonic frequency (e.g., at the second harmonic) of the desired receiver signal frequency. This is due to Fig. 8A Shown.

[0101] Fig. 8A An example is shown where a strong blocking frequency exists at the second harmonic of the carrier frequency of the desired receiver signal. Fig. 8A is Figure 7 Graph of the frequency and level of the signal seen at the antenna 105 of the receiver. The signal at fcarrier is the desired receiver signal, where fcarrier corresponds to the local oscillator frequency of the clock signal from the frequency synthesizer block 730. The signal at fcarrier*2 is an example of a strong blocking signal that is close to the second harmonic of the desired signal and has a higher level than the desired signal. With a 1.5x clock, the receiver will be a three-phase system, which means that the strong blocker close to the second harmonic will be converted into a baseband signal through the down-conversion process and fall into the desired channel, and in a standard three-phase receiver system, will reduce the signal-to-noise ratio of the receiver. Depending on the blocking signal level, the distortion level generated by this clock can be significantly greater than the target / desired signal level, which means that this typical three-phase system may not pass the blocking test case required by the standard.

[0102] In such Figure 7 In the dual three-phase implementation shown, the conversion of the second harmonic to baseband can be minimized. Figure 7 In the arrangement of FIG. 1 , the single-ended signal from antenna 105 is converted to differential form by LNA blocks 721-1, 721-2 and fed to HRM 700 and then propagates through the signal path, similar to Figure 3 Like the transmitter. Figure 8B Shows Figure 8B The output obtained from the three-phase to IQ conversion block 743 is shown in FIG.

[0103] Figure 8B Shows Figure 7 The receiver is targeted at Fig. 8A The baseband frequency of the receiver channel extends from -Fc to Fc. Unwanted blockers close to the second harmonic can be converted to baseband within the target RX channel, which will reduce the signal-to-noise ratio; however, using a dual three-phase receiver architecture, such as Figure 8B As shown, the blocking transition will be minimized to have a lower level, thereby improving the signal-to-noise ratio.

[0104] Fig. 9 It is shown Figure 7Flowchart of an embodiment of the operation of a receiver in an embodiment of . At 901, an input signal is received. Figure 7 In the embodiment of the present invention, an input signal is received by antenna 105 and then enters segmented LNAs 721 - 1 and 721 - 2 , where differential outputs are provided to the p-side and n-side of HRM 700 .

[0105] At 903, the frequency synthesizer 730 generates an LO clock signal and the HRM 700 receives the LO clock signal. The LO clock signal includes three components of the first three-phase clock signal and three components of the shifted second three-phase clock signal. Figure 7 In an embodiment of the present invention, these are clock signals Clk0, Clk120 and Clk240 and shift signals Clk60, Clk180 and Clk300, all of which have a duty cycle of 1 / 3 (33%).

[0106] At 905, for each component in the first three-phase clock signal, the p-side input signal from LNA 721-1 is mixed with the clock signal to generate a corresponding three-phase output signal. Figure 7 In the embodiment, on the p-side, the output of LNA 721-1 enters mixers 701, 702 and 703, in which the output of LNA 721-1 is mixed with Clk0, Clk120 and Clk240 respectively to provide a first three-phase output signal of 0, 120 and 240 components.

[0107] At 907, for each component in the second three-phase clock signal, the p-side input signal from LNA 721-2 is mixed with the clock signal to generate a corresponding second three-phase output signal, the component of the second three-phase output signal being the inverse of the component of the first three-phase output signal of 905. Fig. 9 In the embodiment of the present invention, on the p-side, the output of LNA 721-2 enters mixers 704, 705 and 706, where the output of LNA 721-2 is mixed with Clk60, Clk300 and Clk180 respectively to provide a second three-phase output signal of 60, 300 and 180 components. The first three-phase output from 905 and the second three-phase output from 907 together generate a differential three-phase output. The differential three-phase output can then enter LPFs 747-1, 747-2 and 747-3, and then enter ADCs 745-1, 745-2 and 745-3, and a three-phase to IQ converter 745 to provide output data in an IQ format.

[0108] For Figure 7In the double-sided implementation, the n-side outputs of LNA 721-1 and 721-2 enter a first set of n-side mixers (711, 712, 713) to be mixed with a first three-phase clock signal and a second set of n-side mixers (714, 715, 716) to be mixed with a second three-phase clock signal, respectively. These generate a second inverted output signal and another copy of the first output signal, respectively, which can be similarly used to generate an IQ output.

[0109] As described above, for both the receiver implementation and the transmitter implementation, the described dual three-phase architecture allows the use of a lower VCO frequency to achieve similar harmonic performance as a conventional six-phase system. This reduces the maximum operating frequency requirement of the VCO to 1.5 times, rather than the 3 times VCO frequency requirement of a standard six-phase system.

[0110] The techniques described herein may be implemented using hardware, firmware, software, or a combination of these. The software or firmware used is stored on one or more processor-readable storage devices to Figures 3 to 9 One or more blocks of the computer program to perform the functions described herein. The processor readable storage device may include computer readable media, such as volatile and non-volatile media, removable and non-removable media. As an example and not limitation, the computer readable medium may include computer readable storage media and communication media. The computer readable storage medium may be implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other storage technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage device, cassette, magnetic tape, magnetic disk storage device or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by the components described above. One or more computer readable media do not include propagated, modulated or transient signals.

[0111] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transient data signal such as a carrier wave or other transmission mechanism, and includes any information delivery media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed in a manner that encodes the information in the signal. By way of example and not limitation, communication media include wired media such as a wired network or a direct wired connection and wireless media such as RF and other wireless media. Any combination of the above is also included within the scope of computer readable media.

[0112] In alternative embodiments, some or all of the software or firmware can be replaced by dedicated hardware logic components. For example, but not limited to, the hardware logic components of illustrative types that can be used include field programmable gate arrays (Field-programmable Gate Array, FPGA), application-specific integrated circuits (Application-specific Integrated Circuit, ASIC), application-specific standard products (Application-specific Standard Product, ASSP), system-on-a-chip (System-on-a-chip, SOC), complex programmable logic devices (Complex Programmable Logic Device, CPLD), special computers, etc. In one embodiment, the software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. One or more processors can communicate with one or more computer-readable media / storage devices, peripheral devices and / or communication interfaces.

[0113] It should be understood that this theme can be implemented in many different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this theme will be thorough and complete, and these embodiments fully convey the disclosure to those skilled in the art. In fact, this theme is intended to cover substitutions, modifications, and equivalents of these embodiments within the scope and spirit of the subject matter defined by the appended claims. In addition, in the following detailed description of this theme, many specific details are set forth to provide a thorough understanding of this theme. However, it will be clear to those of ordinary skill in the art that this theme can be practiced without such specific details.

[0114] Various aspects of the present disclosure are described herein with reference to the flowchart illustrations and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each block of the flowchart and / or block diagram and the combination of the blocks in the flowchart illustration and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of a computer or other programmable instruction execution device create a mechanism for implementing the function / action specified in a flowchart and / or block diagram block or multiple blocks.

[0115] The description of the present disclosure has been presented for the purpose of illustration and description, but the description of the present disclosure is not intended to be exhaustive or limited to the disclosure of the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. Various aspects of the disclosure herein are selected and described in order to best explain the principles and practical applications of the present disclosure, and to enable others of ordinary skill in the art to understand the present disclosure with various modifications suitable for the particular purpose contemplated.

[0116] For the purposes of this document, each process associated with the disclosed technology can be performed continuously and by one or more computing devices. Each step in the process can be performed by a computing device that is the same or different from the computing device used in other steps, and each step does not necessarily have to be performed by a single computing device.

[0117] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above may be disclosed as example forms of implementing the claims.

Claims

1. A transmitter, comprising: A three-phase signal source configured to provide three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals; A frequency synthesizer, the frequency synthesizer being configured to: generating a first three-phase clock signal having three clock signals, each of the three clock signals having a phase corresponding to one of the input signals of the three-phase input signal, and generating a second three-phase clock signal having three clock signals, each of the three clock signals having a phase corresponding to one of the inverted input signals of the three-phase input signal; as well as Harmonic rejection mixers, including: The first mixing part includes: a first set of three mixers, each mixer being configured to receive one of the clock signals of the first three-phase clock signal and to mix one of the clock signals of the first three-phase clock signal with one of the input signals of a corresponding phase; and a second group of three mixers, each mixer being configured to receive one of the clock signals of the second three-phase clock signal and to mix one of the clock signals of the second three-phase clock signal with one of the inverted input signals of a corresponding phase, Wherein, the harmonic rejection mixer is further configured as: forming a first intermediate signal by combining the outputs of the first three mixers, forming a second intermediate signal by combining the outputs of the second set of three mixers, and The first intermediate signal and the second intermediate signal are combined to form a first output signal of the harmonic rejection mixer.

2. The transmitter according to claim 1, further comprising: A first variable gain amplifier, wherein the first variable gain amplifier is configured to: receiving the first intermediate signal; as well as amplifying the first intermediate signal before combining the first intermediate signal and the second intermediate signal to form a first output signal of the harmonic rejection mixer; as well as A second variable gain amplifier, the second variable gain amplifier being configured to: receiving the second intermediate signal; and The second intermediate signal is amplified before the first intermediate signal and the second intermediate signal are combined to form a first output signal of the harmonic rejection mixer.

3. The transmitter of claim 1 , wherein the harmonic rejection mixer further comprises: The second mixing part includes: a third group of three mixers, each mixer being configured to receive one of the first three-phase clock signals and mix one of the first three-phase clock signals with an inverted input signal of one of the input signals of a corresponding phase; and a fourth group of three mixers, each mixer being configured to receive one of the clock signals of the second three-phase clock signal and mix one of the clock signals of the second three-phase clock signal with one of the inverted input signals of the corresponding phase as its inverted input signal, Wherein, the harmonic rejection mixer is configured as: forming a third intermediate signal by combining the outputs of the third set of three mixers, forming a fourth intermediate signal by combining the outputs of the fourth set of three mixers, and The third intermediate signal and the fourth intermediate signal are combined to form a second output signal of the harmonic rejection mixer.

4. The transmitter according to claim 3, further comprising: An inductive coupler, the inductive coupler comprising: a first coil configured to: receive a first output signal of the harmonic rejection mixer at a first terminal and receive a second output signal of the harmonic rejection mixer at a second terminal; and A second coil is inductively coupled to the first coil, the second coil having a first terminal configured to provide a single-ended output for the transmitter and a second terminal connected to ground.

5. The transmitter according to claim 4, further comprising: A power amplifier is configured to receive and amplify the single-ended output.

6. The transmitter according to claim 5, further comprising: An antenna is configured to receive and transmit the single-ended output.

7. A transmitter according to any one of claims 1 to 6, wherein: The three-phase signal source is configured to receive an input signal in an in-phase / quadrature format and generate therefrom the three input signals forming the three-phase input signal and an inverted input signal of each of the three input signals.

8. The transmitter according to any one of claims 1 to 6, wherein: The frequency synthesizer comprises: a voltage controlled oscillator configured to generate an oscillator signal; a first three-phase generator configured to generate the first three-phase clock signal from the oscillator signal; a delay circuit configured to receive and delay the oscillator signal; and A second three-phase generator is connected to the delay circuit and is configured to generate the second three-phase clock signal from the delayed oscillator signal.

9. The transmitter according to claim 8, wherein: The frequency synthesizer includes a phase-locked loop, and the phase-locked loop includes the voltage-controlled oscillator.

10. The transmitter according to claim 8, wherein: The voltage controlled oscillator is configured to generate the oscillator signal having a frequency that is 3 / 2 of a frequency of the three-phase clock signal.

11. The transmitter according to claim 10, wherein: The delay circuit introduces a 90° phase shift into the oscillator signal.

12. The transmitter according to claim 10, wherein: The frequency synthesizer is configured to generate the three-phase clock signal, wherein a duty cycle of each of the three clock signals is 1 / 3.

13. A method for sending a signal, comprising: receiving three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals; receiving a first three-phase clock signal having three clock signals and a second three-phase clock signal having three clock signals, each of the three clock signals of the first three-phase clock signal having a phase corresponding to one of the input signals of the three-phase input signal, and each of the three clock signals of the second three-phase clock signal having a phase corresponding to one of the inverted input signals of the three-phase input signal; as well as A first output signal is generated from three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals, and from the first three-phase clock signal and the second three-phase clock signal by the following operations: For each of the three clock signals of the first three-phase clock signal, mixing the clock signal with an input signal of a corresponding phase; For three clock signals of the first three-phase clock signal, combining the mixed clock signal and the input signal to form a first intermediate signal; For each of the three clock signals of the second three-phase clock signal, mixing the clock signal with an inverted input signal of a corresponding phase; For three clock signals of the second three-phase clock signal, combining the mixed clock signal and the inverted input signal to form a second intermediate signal; as well as The first intermediate signal and the second intermediate signal are combined to generate the first output signal.

14. The method according to claim 13, further comprising: The first intermediate signal and the second intermediate signal are respectively amplified before being combined to generate the first output signal.

15. The method according to claim 13, further comprising: A second output signal is generated from three input signals forming a three-phase input signal and an inverted input signal of each of the three input signals and from the first three-phase clock signal and the second three-phase clock signal by: For each of the three clock signals of the first three-phase clock signal, mixing the clock signal with an inverted input signal of a corresponding phase; For three clock signals of the first three-phase clock signal, combining the mixed clock signal and the inverted input signal to form a third intermediate signal; For each of the three clock signals of the second three-phase clock signal, mixing the clock signal with one of the inverted input signals of the corresponding phase which is an input signal of its inverted phase; For three clock signals of the second three-phase clock signal, combining the mixed clock signal and the input signal to form a fourth intermediate signal; as well as The third intermediate signal and the fourth intermediate signal are combined to generate the second output signal.

16. The method according to claim 15, further comprising: applying the first output signal and the second output signal to a first terminal and a second terminal of a first coil of an inductive coupler, respectively; receiving and amplifying an output from a second coil of the inductive coupler inductively coupled to the first coil; as well as Send the amplified output.

17. The method according to any one of claims 13 to 16, further comprising: Receive input signals in in-phase / quadrature format; as well as The three input signals forming a three-phase input signal and the inverted input signal of each of the three input signals are generated from the input signal.

18. The method according to any one of claims 13 to 16, further comprising: generating an oscillator signal by a voltage controlled oscillator; generating the first three-phase clock signal from the oscillator signal; delaying the oscillator signal; as well as The second three-phase clock signal is generated from a delayed oscillator signal.

19. The method according to claim 18, wherein: The voltage controlled oscillator is configured to generate the oscillator signal having a frequency that is 3 / 2 of a frequency of the three-phase clock signal.

20. The method according to claim 19, wherein: Delaying the oscillator signal includes introducing a 90° phase shift into the oscillator signal.

21. The method of claim 18, further comprising: generating the first three-phase clock signal, wherein the duty cycle of each of the three clock signals is 1 / 3; as well as The second three-phase clock signal is generated, wherein a duty cycle of each of the three clock signals is 1 / 3.

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