A floating-point FFT circuit design optimization method based on an approximate multiplier

Abstract

The application discloses a floating-point FFT circuit design optimization method based on an approximate multiplier, uses a precision-configurable approximate multiplier to replace an accurate multiplier, selects different approximation degrees for the approximate multiplier at different stages of an FFT pipeline, and controls the circuit in a top-down manner according to an FFT application level precision requirement, so that hardware benefits, performance benefits are maximized. The application combines the advantages of floating-point operation and approximate calculation, realizes less area overhead, higher clock frequency and lower energy consumption compared with an accurate FFT circuit under the condition that performance is ensured, and reaches excellent performance in the precision range and energy consumption compared with prior advanced approximate FFT technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FFT circuit design, and particularly relates to a floating-point FFT circuit design optimization method based on an approximate multiplier. BACKGROUND

[0002] Fast Fourier Transform (FFT) is a basic algorithm in digital communication and signal processing. Due to the criticality of FFT algorithm in many applications, its hardware accelerator is widely deployed even in resource-constrained systems. It is a challenging task to achieve high performance and high energy efficiency for FFT accelerator, and has attracted more and more attention from academia and industry. Recently, with the increasing popularity of human perception related tasks (such as audio / image processing, machine learning, etc.), it is noticed that the completely accurate FFT result is not always necessary. Therefore, people begin to explore the approximate design of FFT to achieve sufficient but not overly accurate calculation accuracy.

[0003] However, the existing approximate FFT design still has the following problems: 1. Current work mostly uses underlying arithmetic circuits (such as adders, multipliers) to replace the original accurate units, but does not explore the relationship between the accuracy of FFT operation and the error introduced by underlying hardware, thereby leading to invalid approximation or optimization. 2. Most of the existing approximate FFT designs either fix the approximation accuracy at the design stage or use fixed-point operations to sacrifice the dynamic range of operation, but considering the versatility of Internet of Things applications, the current design is difficult to support multi-purpose applications due to its low flexibility.

[0004] In order to ensure the design efficiency and excellent performance of the approximate FFT circuit, a floating-point FFT circuit design optimization method based on an approximate multiplier is proposed based on the above problems. SUMMARY

[0005] The present application aims at the deficiencies of the prior art, and proposes a floating-point FFT circuit design optimization method based on an approximate multiplier. By error modeling, the error introduced by underlying hardware is related to the accuracy of FFT operation. By using an optimization algorithm, the approximation degree of underlying hardware is flexibly adjusted according to the application accuracy requirement, so that the approximate FFT hardware has better performance and lower energy consumption.

[0006] The application aims to realize the following technical scheme: a floating-point FFT circuit design optimization method based on an approximate multiplier, using an accuracy-configurable approximate multiplier to replace an accurate multiplier, i.e., a traditional full-precision floating-point multiplier, selecting different approximation degrees for the approximate multiplier at different stages of the FFT pipeline, and controlling the circuit in a top-down manner according to the accuracy requirement of the FFT application level, thereby maximizing hardware benefits and performance benefits.

[0007] Step 1, error modeling: the relative error is used to numerically simulate the error introduced by the approximate multiplier. For a specific multiplier approximation level, the maximum relative error or a certain large relative error is selected to conservatively estimate the error introduced by the hardware operation at the approximation level. The numerically conservative estimate is used in the approximate FFT operation, thereby accelerating the precision analysis process to support approximation optimization.

[0008] Step 2, approximation optimization: under a certain accuracy constraint, a mixed-integer nonlinear optimization algorithm (Mixed-Integer Nonlinear Optimization Problem, MINLP) is used to select appropriate approximation levels for each pipeline stage of the floating-point FFT. The optimization goal is to minimize the sum of the approximation levels of all pipeline stages, and the constraint condition is that the FFT approximate calculation result meets the application accuracy requirement (generally measured by SNR or PSNR).

[0009] Step 3, hardware implementation: the basic architecture of the floating-point FFT circuit is a pipeline architecture, using an accuracy-configurable approximate multiplier to replace an accurate multiplier. The approximation degree of each pipeline stage depends on the approximation level of the approximate multiplier in the circuit at this stage, and the approximation levels of all approximate multipliers in the same pipeline stage are the same and are not adjusted during hardware operation. The FFT underlying hardware is adjusted according to the approximation level selected in the approximation optimization, thereby maximizing hardware benefits and performance benefits while meeting the accuracy requirement.

[0010] The application has the following beneficial effects: a floating-point FFT circuit design optimization method based on an approximate multiplier is provided, the error modeling links the error introduced by the underlying hardware to the FFT operation accuracy, and the optimization algorithm flexibly adjusts the approximation degree of the underlying hardware according to the application accuracy requirement, thereby better meeting the application requirements of existing limited hardware. The FFT hardware realized by using the design optimization method has a great improvement in area, delay, energy consumption, etc., compared with the traditional accurate FFT circuit; compared with the existing most advanced technology, the FFT hardware realized by using the design optimization method has a nearly 2-fold accuracy range improvement under the condition of ensuring low energy consumption. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1is a flow chart of the present application;

[0012] Figure 2 is a schematic diagram of the present application using relative error for error modeling, Figure 2 (a) shows how to obtain the relative error of a certain percentile in a statistical way, Figure 2 (b) lists the relative error values of different percentiles and approximate levels;

[0013] Figure 3 is a schematic diagram of the present application using relative error for error modeling,

[0014] Figure 4 is a schematic diagram of the present application using relative error for error modeling, Figure 4 (a) shows the PSNR results of precision estimation using error model when the approximate levels of each pipeline stage of the circuit are consistent, Figure 4 (b) shows the PSNR results of precision estimation using error model when the approximate levels of each pipeline stage of the circuit are inconsistent;

[0015] Figure 5 is a schematic diagram of the present application using relative error for error modeling,

[0016] Figure 6 is a schematic diagram of the present application using relative error for error modeling, DETAILED DESCRIPTION

[0017] The present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0018] As Figure 1 shown, the specific implementation steps of the floating-point FFT circuit design optimization method based on the approximate multiplier of the present application are as follows:

[0019] 1) Error modeling: Taking the approximate multiplier PAM proposed in Non-Patent Document 1 (Chen C, Qian W, Imani M, et al. PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier with Unbiasedness and Configurability [J]. IEEE Transactions on Computers, 2021.) as an example, this paper specifically explains how to perform error modeling. The important feature of the approximate multiplier PAM is that the result error of multiplication is closely related to its approximate level. The approximate error modeling method here can be easily extended to other approximate multiplier designs. The error modeling method includes 2 steps, which are error characteristic analysis and error model extraction.

[0020] 1.1) Error Characteristic Analysis:

[0021] According to the IEEE 754 standard, floating-point numbers can be represented as:

[0022]

[0023] where sign x , x, E x F represents floating-point number x The sign, mantissa, and exponent. According to non-patent literature 1, a PAM multiplier is used to multiply two floating-point numbers F... x and F y The difference between the result obtained by the PAM multiplier and the result of exact multiplication during multiplication—that is, the error introduced by the PAM multiplier—can be expressed as:

[0024]

[0025] Where n represents the approximation level chosen by PAM during the calculation; the higher the level, the smaller the error introduced. Where k x and k y For two parameters that vary based on x, y, and the approximate rank n:

[0026] k x = [0.5+floor(x×2)] n )]×2 -n

[0027] k y = [0.5+floor(y×2)] n )]×2 -n

[0028] Take the relative error rel_err n (F x ,F y To measure the error introduced at a certain approximation level:

[0029]

[0030] According to k x and k y The two parameters can be calculated in the following ways:

[0031]

[0032] 1.2) Error model extraction:

[0033] Let x and y be uniformly distributed in the range [1,2), then rel_err n Will as Figure 2(a) General normal distribution, and the value of the horizontal and vertical coordinates is related to n. In order to measure the relative error, the relative error limit in the worst case can be used However, this can be too pessimistic. Therefore, similar to statistical analysis or time series analysis, the relative error of a certain percentile is used to measure the approximation caused by the multiplier, denoted as Where σ is the ratio The percentage of smaller relative errors in a certain approximation level n. When σ and n are determined, It can be determined by statistics. When σ = 1 is determined, When σ is 0.9 and n is 2, Figure 2 (b) The value of Under different n and σ is given.

[0034] In the approximate FFT operation, the multiplication result that the approximate hardware will get can be estimated by

[0035]

[0036] Here, the fixed value is used instead of the error n which needs to be calculated complicatedly, so as to speed up the process of approximate FFT operation, and facilitate the analysis of the relationship between the error introduced by the underlying hardware and the accuracy of FFT operation, so as to support approximation optimization.

[0037] 2) Approximation optimization: according to the method proposed in Figure 1 The accuracy optimization process of FFT is to allocate appropriate approximation levels for each stage. The purpose is to maximize the possible approximation value to increase the benefit of approximate calculation, which is equivalent to minimizing the sum of approximation levels. This problem can be modeled as a mixed-integer nonlinear optimization problem (MINLP):

[0038] Minimize∑n stage

[0039] Subject to:PSNR bnd >PSNR spec

[0040] P(x|x∈Set m ,x≥PSNR bnd )≥Prob spec

[0041] n stage is integer, n​stage ∈[0,11]

[0042] where n stage is the approximation level of the approximate multiplier in a certain pipeline stage, which is an integer; PSNR spec is the precision requirement of the application. Set m is the PSNR set obtained by calculating the approximate FFT of m input sequences; PSNR bnd is the PSNR value at a certain percentile in the estimated PSNR set; Prob spec is the percentile that can be specified according to the application requirements, for example, when the PSNR of the approximate FFT is greater than the precision requirement of the application, Prob spec = 1 can be taken to optimize. The mixed integer nonlinear programming optimization problem can be solved using a MINLP solver.

[0043] Here, the PSNR is used to measure the precision requirement of the application:

[0044]

[0045] where N is the number of FFT points, APR(i) is the result of the approximate FFT, and EXA(i) is the result of the exact FFT. If the application has other ways to measure the FFT precision requirement, it can also be replaced.

[0046] 3) Hardware implementation: The basic architecture of the floating-point FFT circuit is a pipeline architecture, and the precision-configurable approximate multiplier is used to replace the exact multiplier. The approximation degree of each stage of the pipeline depends on the approximation level of the approximate multiplier in the circuit at this stage, and the approximation levels of all approximate multipliers in the same pipeline stage are the same and are not adjusted during hardware operation. According to the approximation level selected in the approximation optimization, the FFT underlying hardware is adjusted, thereby maximizing hardware benefits and performance benefits while meeting the precision requirement.

[0047] The functions and effects of the present application are further illustrated and demonstrated by the following simulation experiments:

[0048] 1. Simulation conditions

[0049] Figure 3 The experimental architecture is shown, including simulation and verification. An FFT precision simulation tool is established using Matlab, and then the RTL implementation of the optimized approximate FFT is completed, and functional verification and timing analysis are performed. Design Complier is used to synthesize and analyze the approximate FFT circuit design on the UMC 40nm library.

[0050] 2. Simulation results

[0051] 1) Verification of error model

[0052] Experiments were conducted to verify the accuracy of the proposed error modeling on a 256-point 8-stage FP FFT using the R2DIF algorithm. Two settings were used for the experiments. Experiment 1 traversed the approximation levels from 1 to 10 and assigned them to the first 6 stages of the pipelined FFT. Figure 4 (a) shows the relative error model using different σ and the PSNR corresponding to the model with the exact error estimate. The results are that all the lines have very small deviations and follow a consistent trend. Experiment 2 randomly assigned the approximation levels to each stage of the pipelined FFT and then performed the same comparison as the first experiment. Figure 4 (b) shows the relative error model using different σ and the PSNR corresponding to the model with the exact error estimate. The results are that all the lines have very small deviations and follow a consistent trend. Experiment 2 randomly assigned the approximation levels to each stage of the pipelined FFT and then performed the same comparison as the first experiment. Figure 4 (a) shows the relative error model using different σ and the PSNR corresponding to the model with the exact error estimate. The results are that all the lines have very small deviations and follow a consistent trend. Experiment 2 randomly assigned the approximation levels to each stage of the pipelined FFT and then performed the same comparison as the first experiment. Figure 5 The output statistics for both settings were further plotted. It can be seen that the difference increases with the increase of σ, indicating that higher σ contains more conservatism.

[0053] 2) Verification of approximation optimization

[0054] The proposed optimization procedure was verified with different application accuracy requirements using σ = 0.85, Prob spec = 1, and the results are presented in the table:

[0055] PSNR spec ]]> Best approximation design Approximation optimization result PSNR bnd ]]> Optimization run time 60 [2,2,2,3,3,3] [2,2,3,3,3,4] 62.3 1 m 13 s 70 [3,3,3,3,4,4] [3,3,3,4,4,5] 72.7 55s 80 [4,4,4,4,4,4] [4,4,4,4,5,5] 82.4 59s 90 [5,5,5,5,5,5] [5,5,5,5,5,6] 90.8 45s 100 [5,6,6,6,6,6] [5,6,6,6,6,6] 101 1 m 23 s

[0056] The second column lists the best approximation design through an exhaustive search that takes hours, while the 3rd-5th columns list the results given by the approximation optimization algorithm. The results show that for different application accuracy requirements, the proposed optimization procedure can be completed in about 1 minute, and the found solution is very close to the optimal combination.

[0057] 3) Approximate FFT hardware implementation and comparison

[0058] The following table gives the comparison between the approximate FFT and the exact FFT using the proposed design method:

[0059]

[0060]

[0061] The proposed designs were implemented using UMC 40nm, and the results were reported from the design compiler. In this table, the second row PSNR spec is the application level FFT accuracy requirement. The third row is the selected approximation levels for each stage of the pipelined FFT after approximation optimization. The fourth row PSNR actis the actual PSNR of the implemented FFT hardware. All optimized designs meet the PSNR requirement with a difference of less than 6 dB, which is only 6% of the PSNR requirement. The last five lines report the area, clock frequency, power, energy per FFT operation, and normalized area-delay product (ADP). The results show that the optimized FFTs run nearly 50% faster and save about 23% energy per operation. In addition, the proposed design can achieve up to 52% improvement in ADP to achieve higher energy efficiency than the exact FFT design.

[0062] The proposed approximate FFT is compared with the state-of-the-art approximate FFT design in Figure 6 from non-patent document 2 (Liu W, Liao Q, Qiao F, et al. Approximate designs for fast Fourier transform (FFT) with application to speech recognition [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12): 4727-4739.) It can be seen from the figure that the proposed approximate FFT has the advantages of wider accuracy range and higher energy efficiency under tighter PSNR constraints compared to the design of non-patent document 2. This shows that the proposed design has great hardware advantages.

[0063] The above embodiments are used to explain and illustrate the present application, but not to limit the present application. Any modifications and changes made to the present application within the spirit and protection scope of the claims fall within the protection scope of the present application.

Claims

1. A method for optimizing the design of floating-point FFT circuits based on approximate multipliers, characterized in that, The approximate multiplier with configurable precision is used to replace the accurate multiplier, different approximation degrees are selected for the approximate multiplier in different stages of the FFT pipeline, and the circuit is controlled in a top-down manner according to the accuracy requirement of the FFT application level, so as to maximize the hardware benefit and performance benefit; The method comprises the following steps: Step 1, error modeling: numerical simulation is performed on the introduced error of the approximate multiplier, and the simulation value is used for FFT operation to accelerate the accuracy analysis process, thereby supporting approximation optimization; Wherein, the introduced error of the approximate multiplier is numerically simulated by using relative error, for a certain multiplication approximation level, the maximum relative error or a certain user-set relative error is selected to conservatively estimate the introduced error, thereby simplifying the approximation FFT operation process; Step 2, approximation optimization: under a constraint condition, a mixed shaping nonlinear optimization algorithm is used to select appropriate approximation levels for each pipeline stage of the floating-point FFT, and the constraint condition is that the approximation calculation result of the FFT meets the application accuracy requirement; Step 3, hardware implementation: the bottom hardware of the FFT is adjusted according to the approximation level selected for each pipeline stage.

2. The method of claim 1, wherein the method is optimized for a floating-point FFT circuit design based on an approximate multiplier. The basic architecture of the FFT circuit is a pipeline architecture, and the approximation degree of each pipeline stage depends on the approximation level of the approximate multiplier in the circuit of the stage, the approximation levels of all approximate multipliers in the same pipeline stage are the same and do not change during hardware operation.

3. The method of claim 1, wherein the method further comprises: In step 2, the optimization target is "the sum of the approximation levels of all pipeline stages is as small as possible".

4. The method of claim 1, wherein the method further comprises: In step 3, the approximation levels of the approximate multipliers in each pipeline stage are adjusted according to the results of the approximation optimization.

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