Dual address command management using content addressable memory

Abstract

The present disclosure relates to dual address command management using content addressable memory. A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device performs operations including, in response to receiving a memory access command, determining that the memory access command is a dual address command including a source address and a destination address, generating a first content addressable memory (CAM) entry associated with a read command of the dual address command, where the first CAM entry references the source address, generating a second CAM entry associated with a write command of the dual address command, where the second CAM entry references the destination address, inserting the first CAM entry and the second CAM entry into a CAM, and issuing the read command associated with the first CAM entry to the memory device.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to dual-address commands using content-addressable memory (CAM) within a memory subsystem. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a system comprising: a memory device; and a processing means operably coupled to the memory device for performing operations including: in response to receiving a memory access command, determining that the memory access command is a dual-address command including a source address and a destination address; generating a first content-addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into a CAM; and issuing the read command associated with the first CAM entry to the memory device.

[0004] In another aspect, this disclosure relates to a method comprising: generating a first content-addressable memory (CAM) entry for a source address of a reference move command; generating a second CAM entry associated with a destination address of the reference move command; and inserting the first CAM entry and the second CAM entry into a CAM.

[0005] In another aspect, this disclosure relates to a non-transitory machine-readable storage medium for storing instructions, which, when executed by a processing device, cause the processing device to perform operations including: in response to receiving a memory access command, determining that the memory access command is a dual-address command including a source address and a destination address; generating a first content-addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into the CAM; and issuing the read command associated with the first CAM entry to a memory device. Attached Figure Description

[0006] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of an example system including a memory access command management (DCM) component according to some embodiments of the present disclosure.

[0009] Figure 3 A diagram illustrating an example of a queue of memory access commands according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of content addressable memory (CAM) metadata according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart illustrating an example method for implementing data consistency management according to some embodiments of the present disclosure.

[0012] Figure 6 This is a flowchart illustrating an example method for implementing data consistency management according to some embodiments of the present disclosure.

[0013] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0014] This disclosure relates to dual-address command management using content-addressable memory (CAM) in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logical states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0016] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in the form of column (hereinafter also referred to as bit lines) and row (hereinafter also referred to as word lines) arrays. A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate the address of each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and may include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form planes of a memory device to allow concurrent operation on each plane. A memory device may include circuitry that performs concurrent memory page accesses on two or more memory planes. For example, a memory device may include multiple access line driver circuits and power circuitry that can be shared by planes of the memory device to facilitate concurrent access to pages containing different page types on two or more memory planes. For ease of description, these circuits are often referred to as independent plane driver circuits. Depending on the memory architecture employed, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a segment of data (e.g., corresponding to one or more data addresses) can result in a read operation performed on two or more of the memory planes of the memory device.

[0017] Memory access commands request the memory device to perform a memory access operation. Memory access commands can typically be categorized into corresponding types, such as read commands, write commands, erase commands, move commands, etc. The memory subsystem controller can allocate the received memory access commands to one of multiple queues within the memory subsystem. Illustratively, the queue can be in the form of a linked list containing a head and a tail, where memory access commands are retrieved from the queue and executed in a first-in, first-out (FIFO) manner. Since memory access commands from only one queue can be executed simultaneously, the memory subsystem controller can use a sequencer to serve commands identified within the queue according to a scheduling scheme.

[0018] Memory access commands can specify an address that identifies a memory location (e.g., a management unit) on a memory device. For example, the address can be a physical block address (PBA). A media controller architecture (e.g., a 3D cross-point media controller architecture) can include a command management component and a set of communication channels (“channels”) that enable multi-channel communication between the media controller architecture and the memory device. The command management component can manage data integrity and command order based on the time of the entry (e.g., a FIFO command execution scheme). Each channel in the set of channels can implement a content-addressable memory (CAM) to receive commands for a specific memory location on the memory device and place the commands into a queue maintained on the CAM (e.g., for a FIFO command execution scheme, appending a new memory access command to the tail of the queue). Thus, each CAM can be used to ensure that memory access commands for a specific memory location are processed sequentially within the corresponding channel.

[0019] CAM is a common type of memory device used in some extremely high-speed search applications, such as identifier (ID) and pattern matching. Typically, a CAM is searched by comparing input search data with a table of stored data entries and returning the memory address of the data in the matching table. CAMs are frequently implemented in Dynamic Random Access Memory (DRAM) or Synchronous Random Access Memory (SRAM). However, both DRAM and SRAM have limited memory capacity, which limits the amount of data that can be stored and searched in conventional CAM implementations.

[0020] A move command is a memory access command that includes two addresses: a source address and a destination address. More precisely, a move command is used to move data from one address to another. For example, a move command can execute a read access command that instructs the memory device to perform a read access operation on the source address, and a write access command that instructs the memory device to write (program) data read from the source address to the destination address. Move commands can be used, for example, in wear-leveling operations to prevent a portion of the memory device from being overused and experiencing premature failure.

[0021] In some memory subsystems, the memory subsystem controller inserts separate commands into the CAM to process move commands. Specifically, the memory subsystem controller may insert a read command into the CAM to store the retrieved data in cache memory, and then insert a write command into the CAM to program the retrieved data onto the memory device. However, this process is relatively time-consuming, increasing the memory subsystem's system latency and reducing performance.

[0022] The aspects of this disclosure address the above and other shortcomings by providing a Content Addressable Memory (CAM) capable of executing move commands. In some embodiments, the memory subsystem may utilize a CAM architecture implemented in a NAND flash memory device to provide fast and high-capacity search capabilities. According to this architecture, the memory subsystem controller may employ one or more CAMs, wherein each CAM maintains a queue storing identifiers for memory access operations at a specific memory location (e.g., PBA) residing on the memory device. In some embodiments, the queue may be implemented by a linked list that identifies a sequence of memory access commands specifying a particular memory location. The queue may have a head command corresponding to the oldest memory access command received by the CAM for the particular memory location, and a tail command corresponding to the latest memory access command to be received by the CAM for the particular memory location. Each memory access command inserted into the CAM may be referred to as a CAM entry. Each CAM entry may contain metadata indicating different parameters and characteristics of the memory access command. In some embodiments, the metadata may include: a "command type" identifier indicating the command type of the CAM entry (e.g., a single-address command or a dual-address command); an "address" identifier identifying the physical block address (PBA) (and / or logical block address (LBA)) referenced by the memory access command; a "destination address" identifier indicating the destination address of the move command; a "destination header" identifier indicating that the CAM entry is the head of a linked list of destination addresses for the move command; a "move read" identifier indicating that the CAM entry is the read command portion of the move command; a "move write" identifier indicating that the CAM entry is the write command portion of the move command; and a "hold tag" identifier indicating which CAM entry in the read command portion of the move command is the write command portion of the move command. For example, a hold tag may be used in the metadata of the CAM entry in the read command portion of the move command to indicate that CAM entry 5 is the corresponding write portion of the move command.

[0023] When a CAM has free entries, the memory subsystem controller can select memory access commands (from the queue or cache) to insert into the CAM. To perform the insertion, the memory subsystem controller can first determine whether the memory access command is a single-address command (e.g., write, read, erase) or a dual-address command (e.g., move). If the memory access command is a dual-address command, the memory subsystem controller can generate two CAM entries: a CAM entry for the read command portion of the move command, and a CAM entry for the write command portion of the move command. The memory subsystem controller can further search the metadata of each valid CAM entry to determine the PBA and / or LBA referenced by each associated memory access command. In response to the memory subsystem controller determining that both the source address referenced by the read command portion of the move command and the destination address referenced by the write command portion of the move command match addresses referenced by two or more pending CAM entries, the memory subsystem controller can append the read command portion to the tail of the queue at the same address as the read command portion, and append the write command portion to the tail of the queue at the same address as the write command portion. The memory subsystem controller can further indicate the corresponding parameters of the two CAM entries via metadata (e.g., whether the CAM entry is the read command portion or the write command portion of a move command, which CAM entry is the write command portion of the move command, etc.). In response to determining that the source address referenced by the move command matches an address referenced by one or more of the CAM entries but not the destination address referenced by the move command, the memory subsystem controller can append the read command portion to the tail of the queue at the address that is the same as the read command portion, and insert the write command portion as the head memory access command. The memory subsystem controller can further indicate the corresponding parameters of the two CAM entries via metadata. In response to determining that the destination address referenced by the move command matches an address referenced by one or more of the CAM entries but not the source address referenced by the move command, the memory subsystem controller can append the write command portion to the tail of the queue at the address that is the same as the read command portion, and insert the read command portion as the head memory access command. The memory subsystem controller can further indicate the corresponding parameters of the two CAM entries via metadata. In response to a determination that the source and destination addresses referenced by a move command do not match either the address referenced by the CAM entry, the memory subsystem controller may insert each of the read and write command sections as a header memory access command. The memory subsystem controller may further indicate the corresponding parameters of the two CAM entries via metadata.

[0024] The advantages of this disclosure include, but are not limited to, improved performance in the memory subsystem. Specifically, this disclosure enables the memory subsystem to maintain memory access command ordering for both single-address and dual-address memory access commands. Therefore, this disclosure improves memory access command latency and Quality of Service (QoS), data transaction synchronization, and reduces hardware implementation complexity. Furthermore, implementing the functionality of this disclosure with fewer memory subsystem controller resources reduces cost and power consumption in the memory subsystem.

[0025] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0030] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2DN NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages that refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Memory subsystem 110 includes a data consistency management (DCM) component 113. In some embodiments, memory subsystem controller 115 includes at least a portion of DCM component 113. In some embodiments, DCM component 113 is part of host system 110, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of DCM component 113 and is configured to perform the functionality described herein.

[0042] In some embodiments, the DCM component 113 can enforce data consistency of the memory device by controlling the service level of incoming memory access commands to prevent desynchronization. To achieve this, the DCM component 113 can manage incoming memory access commands based on whether they are single-address commands (e.g., write commands, read commands, erase commands) or dual-address commands (e.g., move commands). If the incoming memory access command is a dual-address command, the DCM component 113 can insert two memory access commands (write command and read command) into the CAM and perform a set of operations to prevent the write command and / or read command from being processed asynchronously with other pending memory access commands. Reference will be made below. Figure 2 Further details about DCM component 113 are described below.

[0043] Figure 2 This is a block diagram of an example system 200 including a data consistency management (DCM) component 113 according to some embodiments of the present disclosure. The DCM component 113 may be included within a memory subsystem controller (e.g., memory subsystem controller 115). The DCM component 113 may be included in any suitable memory subsystem according to the embodiments described herein. For example, the DCM component 113 may be included in a 3DXP memory device (e.g., Figure 1 Within the memory subsystem of the memory device 130.

[0044] As shown, DCM component 113 may include command manager 220 and several CAMs 230-1 to 230-N. Command manager 220 may issue commands for processing by CAMs 230-1 to 230-N to handle data integrity and command ordering (e.g., FIFO command execution scheme). For example, memory access commands issued by command manager 220 are routed to one of CAMs 230-1 to 230-N based on the memory location specified by the memory access command. Each of CAMs 230-1 to 230-N may store multiple command entries identified by corresponding CAM entry values. Each of CAMs 230-1 to 230-N may maintain a queue of memory access commands issued by command manager 220, wherein each queue contains memory access commands corresponding to a specific memory location (e.g., PBA). In some embodiments, each queue of memory access commands contains a linked list of memory access commands ordered by time. Therefore, queues can be used to process memory access commands for a specific memory location in chronological order (e.g., FIFO order). An example of a linked list for memory access operations is referenced below. Figure 3 A description, and further details regarding the process that can be performed by DCM component 113 to implement data consistency management, will be referenced below. Figure 5 and 6Describe it.

[0045] Figure 3 FIG300 illustrates an example of a queue of memory access commands according to some embodiments of the present disclosure. FIG300 shows a first queue 310-A ​​corresponding to a first memory location (e.g., a physical block address (PBA)) residing on a memory device, a second queue 310-B corresponding to a second memory location residing on a memory device, and a third queue 310-C corresponding to a third memory location residing on a memory device. The first queue 310-A ​​contains four memory access commands, including a head memory access command 312-A and a tail memory access command 314-A. The second queue 310-B contains three memory access commands, including a head memory access command 312-B and a tail memory access command 314-B. The third queue 310-C contains memory access command 312-C, which may be both a head memory access command and a tail memory access command.

[0046] In some embodiments, each of queues 310-A ​​to 310-C is in the form of a linked list. Incoming memory access commands may be appended to the tail of the linked list (e.g., in FIFO order). For example, head memory access commands 312-A to 312-C may correspond to the oldest remaining memory access command in their respective queues 310-A ​​to 310-C, and tail memory access commands 314-A to 314-C may correspond to the oldest remaining memory access command in their respective queues 310-A ​​to 310-C. After one of the head memory access commands 312-A to 312-C is completed, the head memory access command is removed from its corresponding queue, and any next memory access command linked to the head memory access command becomes a new head memory access command (if any next memory access command linked to the head memory access command exists). If there is no next memory access command linked to the head memory access command (e.g., shown in queue 310-C relative to a single memory access command 312-C), then no additional memory access command is executed for the corresponding memory location before the new memory access command at the memory location.

[0047] Figure 4 Figure 400 illustrates instance metadata associated with each memory access command inserted into the CAM (e.g., inserted into each CAM entry) according to some embodiments of this disclosure. Figure 4The description includes an instance metadata table 405 containing a set of CAM fields 410 and corresponding values ​​420. Each CAM entry may contain a set of metadata identifying different parameters and / or characteristics associated with a memory access command. In some embodiments, the metadata may contain a CAM entry value. The CAM entry value may be used as a CAM entry identifier by the DCM component 113. In some embodiments, the metadata may contain a "valid" identifier to indicate whether the CAM entry is valid (e.g., whether the CAM entry has been processed by the memory device). For example, the DCM component 113 may use a binary value of 1 to indicate that the memory access command is valid and a binary value of 0 to indicate that the memory access command is invalid. In some embodiments, the metadata may contain a "command type" identifier to indicate the command type of the CAM entry (e.g., a single-address command or a dual-address command). In some embodiments, the metadata may contain a "header" identifier to indicate whether the CAM entry is a header memory access command. For example, the DCM component 113 may use a binary value of 1 to indicate that the memory access command is a header memory access command and a binary value of 0 to indicate that the memory access command is not a header memory access command. In some embodiments, the metadata may include a "tail" identifier to indicate whether a CAM entry is a tail memory access command. For example, DCM component 113 may use a binary value of 1 to indicate that a memory access command is a tail memory access command, and a binary value of 0 to indicate that a memory access command is not a tail memory access command. In some embodiments, the metadata may include an "address" identifier to identify the physical block address (PBA) (and / or logical block address (LBA)) referenced by the memory access command. A move command may be referred to as two separate CAM entries (e.g., a read command portion referencing a source address and a write command portion referencing a destination address). In some embodiments, the address identifier may be associated with the source address referenced by the read command portion of the move command, and the address identifier may be associated with the destination address referenced by the write command portion of the move command. In some embodiments, the metadata may include a "next" identifier to indicate which CAM entry is a subsequent entry in the corresponding linked list. For example, the queue may contain two memory access commands, including a head memory access command as CAM entry 2 and a tail memory access command as CAM entry 5. DCM component 113 can set the next indicator of the metadata of CAM entry 2 to recognize CAM entry 5 as a subsequent memory access command of the linked list.

[0048] In some embodiments, the metadata may include a "destination header" identifier indicating that the CAM entry is the head of a linked list of destination addresses for a move command. In some embodiments, the metadata may include a "destination address" identifier indicating the destination address of a move command. In some embodiments, the metadata may include a "move read" identifier indicating that the CAM entry is the read command portion of a move command. In some embodiments, the metadata may include a "move write" identifier indicating that the CAM entry is the write command portion of a move command. In some embodiments, the metadata may include a "hold tag" identifier indicating which CAM entry is the write command portion of the move command within the read command portion. For example, a hold tag may indicate in the CAM entry metadata of the read command portion that CAM entry 6 is the corresponding write portion.

[0049] Figure 5 This is a flowchart of an example method 500 for implementing data consistency management according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 and 2 The DCM component 113 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0050] At operation 502, the processing logic may select a memory access command to insert into the CAM (e.g., CAM 230-1 to 230-N). For example, in response to the CAM having free entries, the processing logic may select a memory access command from a queue or cache based on at least one of the following: the priority of the memory access command (e.g., a host start command or a controller start command), the location received in the queue or cache (e.g., FIFO, Last-In-First-Out (LIFO), etc.), or any other method. The memory access command may specify a memory location residing on a memory device. The memory location may be associated with any suitable memory device. In some embodiments, the memory location is a PBA.

[0051] At operation 504, the processing logic determines whether the memory access command is a single-address command (e.g., a write command, a read command, an erase command) or a dual-address command (e.g., a move command). In response to the memory access command being a single-address command, the processing logic proceeds to operation 506. In response to the memory access command being a dual-address command, the processing logic proceeds to operation 514.

[0052] At operation 506, the processing logic determines the address referenced by the CAM entry in the CAM. In some embodiments, the processing logic may search metadata associated with each CAM entry to determine the PBA (and / or LBA) referenced by each memory access command. In some embodiments, the processing logic may search only valid CAM entries (e.g., "valid" identifiers containing a binary value set to 1).

[0053] At operation 508, the processing logic determines whether any of the CAM entries matches the address referenced by the memory access command. For example, the processing logic may determine whether the PBA referenced by the memory access command is the same as the PBA referenced by any of the CAM entries. In response to the processing logic determining that none of the CAM entries references the same address as the memory access command, the processing logic proceeds to operation 510. In response to the processing logic determining that one or more of the CAM entries reference the same address as the memory access command, the processing logic proceeds to operation 512.

[0054] At operation 510, the processing logic generates a new linked list and inserts the memory access command into the CAM. For example, the processing logic can set the header identifier and destination header identifier (of the metadata associated with the CAM entry for the inserted memory access command) to the value 1 to indicate that the memory access command is a header memory access command. The processing logic can then issue the memory access command.

[0055] At operation 512, the processing logic may insert a memory access command as a tail memory access command of the linked list associated with the matching address. For example, the processing logic may set the header identifier to a binary value of 0 and the destination header identifier to a binary value of 1.

[0056] At operation 514, the processing logic determines the address referenced by the CAM entry in the CAM. In some embodiments, the processing logic may search metadata associated with each memory access command inserted into the CAM to determine the PBA (and / or LBA) referenced by each memory access command. In some embodiments, the processing logic may search only valid CAM entries.

[0057] At operation 516, the processing logic determines whether the source address and destination address referenced by a dual-address command (e.g., a move command) are both the same as addresses referenced by two or more entries in the CAM. In response to determining that the source address and destination address referenced by the memory access command are both the same as addresses referenced by two or more entries in the CAM, the processing logic proceeds to operation 518 and inserts the move command at the tail of the linked list associated with the matching address. For example, the processing logic may insert the read command portion of the move command as a tail memory access command into the linked list referencing the source address of the move command, and insert the write command portion of the move command as a tail memory access command into the linked list referencing the destination address of the move command. The processing logic may set the header identifier to a binary value of 0 for both portions of the move command and set the destination header identifier to a binary value of 0.

[0058] In response to the determination that the source and destination addresses referenced by the move command are different from the addresses referenced by two or more of the entries in the CAM entry (e.g., mismatch), the processing logic proceeds to operation 520.

[0059] At operation 520, the processing logic determines whether the source address referenced by the move command matches the address referenced by one or more CAM entries. In response to determining that the source address referenced by the move command matches the address referenced by one or more CAM entries (and the destination address of the move command does not match the address referenced by one or more CAM entries), the processing logic proceeds to operation 522 and inserts the read command portion of the move command as a tail memory access command into the linked list of the source address of the reference move command, and inserts the write command portion of the move command as a head memory access command. For the read command portion of the move command, the processing logic may set the header identifier to a binary value of 0 and the destination header identifier to a binary value of 1. The processing logic may then insert the write command portion of the move command into the CAM as another CAM entry, and set the hold tag identifier to a binary value of 1 to indicate that the CAM entry associated with the write command portion of the move command is linked to the CAM entry associated with the read command portion of the move command.

[0060] In response to the determination that the source address referenced by the move command does not match the address referenced by one or more of the CAM entries, the processing logic proceeds to operation 524.

[0061] At operation 524, the processing logic determines whether the destination address referenced by the move command matches the address referenced by one or more CAM entries. In response to determining that the destination address referenced by the move command matches the address referenced by one or more CAM entries (and the source address of the move command does not match the address referenced by one or more CAM entries), the processing logic proceeds to operation 526 and inserts the write command portion of the move command as a tail memory access command into the linked list of destination addresses of memory access commands, and inserts the read command portion of the move command as a head memory access command. For the read command portion of the move command, the processing logic may set the header identifier to a binary value of 1 and the destination header identifier to a binary value of 0. The processing logic may then insert the write command portion of the move command into the CAM as another CAM entry, and set the hold tag identifier to a binary value of 1 to indicate that the CAM entry associated with the write command portion of the move command is linked to the CAM entry associated with the read command portion of the move command. The processing logic can further set the tail identifier to 1 for the write portion of the move command, set the tail identifier to 0 in the previous CAM entry of the linked list, and set the next identifier in the previous CAM entry of the linked list to the CAM entry ID of the write command portion of the move command.

[0062] In response to the determination that the source and destination addresses referenced by the move command do not match the addresses referenced by one or more CAM entries in the CAM, the processing logic proceeds to operation 528. At operation 528, the processing logic generates a new linked list and inserts the move command into the CAM. Specifically, the processing logic inserts the read command portion of the move command as one CAM entry and the write command portion as another CAM entry. For the read command portion of the move command, the processing logic may set the header identifier and destination header identifier to a value of 1 to indicate that the memory access command is a header memory access command. The processing logic may then issue the memory access command. For the write command portion of the move command, the processing logic may set the hold tag identifier to a binary value of 1 to indicate that the CAM entry associated with the write command portion of the move command is linked to the CAM entry associated with the read command portion of the move command.

[0063] Figure 6 This is a flowchart of an example method 600 for implementing data consistency management according to some embodiments of the present disclosure. Method 600 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1 and 2The DCM component 113 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] At operation 602, in response to receiving an indication that the memory device has completed a memory access command, the processing logic determines the CAM entry value associated with the completed memory access command. For example, the processing logic may receive a programmed indication of read data associated with a read access command or write data associated with a write access command. The processing logic may use metadata, data structures, identifiers, etc., to determine the CAM entry value.

[0065] At operation 604, the processing logic invalidates the CAM entry (e.g., sets the valid identifier to the binary value 0) and instructs the CAM entry to freely receive another memory access command.

[0066] At operation 606, in response to the tail identifier indicating the existence of a subsequent CAM entry in the corresponding linked list, the processing logic sets a header identifier for the subsequent CAM entry to indicate that the subsequent CAM entry is a header memory access command (e.g., setting the header identifier to a binary value of 1). In some embodiments, in response to the subsequent CAM entry being indicated as a header memory access command and a destination header memory access command, the memory subsystem controller may issue the subsequent CAM entry.

[0067] At operation 608, the processing logic determines whether the CAM entry involves the single-address command or read command portion of a move command. If the CAM entry is related to a single-address command, method 600 ends. If the CAM entry is related to the read command portion of a move command, the processing logic proceeds to operation 610.

[0068] At operation 610, the processing logic identifies and issues the CAM entry associated with the write command section. For example, the processing logic can use a retain tag identifier to identify the CAM entry associated with the write command section. The processing logic can then issue the write command to the memory device.

[0069] At operation 612, in response to receiving an indication that the memory device has completed a write command, the processing logic invalidates the CAM entry associated with the write command portion (e.g., sets the valid identifier to a binary value of 0) and instructs the CAM entry to freely receive another memory access command. The processing logic may further perform operation 606 in response to a tail identifier indicating the existence of a subsequent CAM entry in the corresponding linked list.

[0070] Figure 7 An example machine illustrating computer system 700 is described, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of DCM component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0071] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions that will take a specified action by said machine. Furthermore, although a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0072] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0073] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0074] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more sets of instructions 726 or software embodying any or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0075] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1 The DCM component 113 contains functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0076] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. The algorithms described herein generally refer to a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical control over a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0077] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0078] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Structures for various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0080] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, and the like.

[0081] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the invention without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: Memory devices; and A processing device, operatively coupled to the memory device, for performing operations including: In response to receiving a memory access command, the memory access command is determined to be a dual-address command including a source address and a destination address; Generate a first content-addressable memory (CAM) entry associated with the read command of the dual-address command, wherein the first CAM entry references the source address; A second CAM entry is generated that is associated with the write command of the dual-address command, wherein the second CAM entry references the destination address; Insert the first CAM entry and the second CAM entry into the CAM; and The read command associated with the first CAM entry is issued to the memory device.

2. The system of claim 1, wherein the processing device further performs operations including: In response to determining that the third CAM entry references the source address, the first CAM entry is appended to the tail of the corresponding linked list.

3. The system of claim 1, wherein the processing device further performs operations including: In response to determining that the third CAM entry refers to the destination address, the second CAM entry is appended to the tail of the corresponding linked list.

4. The system of claim 1, wherein the first CAM entry includes an indicator that identifies the second CAM entry.

5. The system of claim 4, wherein the processing device further performs operations including: Receive an indication that the read command associated with the first CAM entry has been completed; The second CAM entry is identified using the indicator; and The write command associated with the second CAM entry is issued to the memory device.

6. The system of claim 1, wherein the processing device further performs operations including: Receive an indication that the read command associated with the first CAM entry has been completed; and Invalidate the first CAM entry.

7. The system of claim 1, wherein the processing device further performs operations including: In response to determining that a CAM entry does not reference the source address or the destination address, a new linked list associated with the first CAM entry is generated.

8. A method comprising: A first content-addressable memory (CAM) entry is generated to the source address of the reference move command, and the first CAM entry is associated with a read command of the move command; A second CAM entry is generated that is associated with the destination address of the referenced move command, and the second CAM entry is associated with the write command of the move command; Insert the first CAM entry and the second CAM entry into the CAM; and The read command associated with the first CAM entry is issued to the memory device.

9. The method of claim 8, further comprising: In response to determining that the third CAM entry references the source address, the first CAM entry is appended to the tail of the corresponding linked list.

10. The method of claim 8, further comprising: In response to determining that the third CAM entry refers to the destination address, the second CAM entry is appended to the tail of the corresponding linked list.

11. The method of claim 8, wherein the first CAM entry includes an indicator that identifies the second CAM entry.

12. The method of claim 11, further comprising: Receive an indication that the read command associated with the first CAM entry has been completed; The second CAM entry is identified using the indicator; and A write command associated with the second CAM entry is issued to the memory device.

13. The method of claim 8, further comprising: Receive an indication that the read command associated with the first CAM entry has been completed; and Invalidate the first CAM entry.

14. The method of claim 8, further comprising: In response to determining that a CAM entry does not reference the source address or the destination address, a new linked list associated with the first CAM entry is generated.

15. A non-transitory machine-readable storage medium storing instructions, said instructions, when executed by a processing device, causing the processing device to perform operations including: In response to receiving a memory access command, the memory access command is determined to be a dual-address command including a source address and a destination address; Generate a first content-addressable memory (CAM) entry associated with the read command of the dual-address command, wherein the first CAM entry references the source address; A second CAM entry is generated that is associated with the write command of the dual-address command, wherein the second CAM entry references the destination address; Insert the first CAM entry and the second CAM entry into the CAM; and The read command associated with the first CAM entry is issued to the memory device.

16. The non-transitory machine-readable storage medium of claim 15, wherein the processing means further performs operations including: In response to determining that the third CAM entry references the source address, the first CAM entry is appended to the tail of the corresponding linked list.

17. The non-transitory machine-readable storage medium of claim 15, wherein the processing means further performs operations including: In response to determining that the third CAM entry refers to the destination address, the second CAM entry is appended to the tail of the corresponding linked list.

18. The non-transitory machine-readable storage medium of claim 15, wherein the first CAM entry includes an indicator that identifies the second CAM entry.

19. The non-transitory machine-readable storage medium of claim 18, wherein the processing means further performs operations including: Receive an indication that the read command associated with the first CAM entry has been completed; The second CAM entry is identified using the indicator; and The write command associated with the second CAM entry is issued to the memory device.

20. The non-transitory machine-readable storage medium of claim 15, wherein the processing device is to further perform operations comprising: generating a new linked list associated with the first CAM entry in response to determining that the CAM entry does not reference the source address or the destination address.

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