Joint single-level cell verification in memory devices

Abstract

The present disclosure relates to joint single-level cell verification in a memory device. Control logic in a memory device identifies a set of memory cells in a block of a memory array, where the set of memory cells includes two or more memory cells programmed during a program phase of a program operation and associated with a selected word line of the memory array. The control logic further causes a program verify voltage to be applied to the selected word line during a program verify phase of the program operation; and performs a parallel sense operation on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to joint single-level cell (SLC) verification in memory devices of memory subsystems. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to one aspect of this disclosure, a memory device is provided. The memory device includes: a memory array; and control logic operably coupled to the memory array to perform operations including: identifying a set of memory cells in a block of the memory array, wherein the set of memory cells includes two or more memory cells programmed during a programming phase of a programming operation and associated with a selected word line of the memory array; causing a programming verification voltage to be applied to the selected word line during a programming verification phase of the programming operation; and performing a parallel sensing operation on the set of memory cells to determine whether each memory cell in the set of memory cells is programmed to at least the programming verification voltage during the programming phase of the programming operation.

[0004] According to another aspect of this disclosure, a method is provided. The method includes: identifying a set of memory cells in a block of a memory array, wherein the set of memory cells includes two or more memory cells that are programmed during a programming phase of a programming operation and associated with a selected word line of the memory array; causing a programming verification voltage to be applied to the selected word line during a programming verification phase of the programming operation; and performing a parallel sensing operation on the set of memory cells to determine whether each memory cell in the set of memory cells is programmed to at least the programming verification voltage during the programming phase of the programming operation.

[0005] According to another aspect of this disclosure, a memory device is provided. The memory device includes: a memory array; and control logic operably coupled to the memory array to perform operations including: initiating a programming operation on the memory array, the programming operation including a programming phase and a programming verification phase; and causing, during the programming phase, to apply a dual pulse having a programming voltage level to a selected word line of the memory array to program a pair of memory cells associated with the selected word line; and causing, during the programming verification phase, to apply a single pulse having a programming verification voltage level to the selected word line of the memory array to verify in parallel that the pair of memory cells are programmed to at least the programming verification voltage level during the programming phase of the programming operation. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of this disclosure may be used for reference. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3A This is a schematic diagram of a portion of a memory cell array implementing Joint Single-Level Cell (SLC) verification according to some embodiments of the present disclosure.

[0011] Figure 3B This is a signal diagram illustrating various signals applied to a memory array during joint single-level cell (SLC) verification according to some embodiments of this disclosure.

[0012] Figure 4 This is a flowchart of an example method for joint single-level cell (SLC) verification in a memory device according to some embodiments of the memory subsystem of the present disclosure.

[0013] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0014] This disclosure relates to joint single-level cell (SLC) verification in a memory device within a memory subsystem. The memory subsystem can be a storage device, a memory module, or a combination of both. Examples of storage devices and memory modules are described below with reference to Figure 1. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0015] A memory subsystem may contain high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. For example, NAND flash memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane consists of a set of physical blocks. Each block contains a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0016] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device to allow parallel operation on each plane.

[0017] During programming operations on non-volatile memory devices, certain phases may be encountered, including programming and programming verification. For example, a high programming voltage may be applied to a selected word line of a block of the memory device during the programming phase, followed by a programming verification phase in which a verification voltage is applied to the selected word line. Some programming operations may be, for example, dual programming operations in which two sub-blocks are programmed in one operation. In such dual programming operations, two sub-blocks may be programmed before the programming verification phase (i.e., two separate programming pulses may be applied). Depending on the implementation, some memory devices may utilize dual verification operations or seamless verification operations during the subsequent programming verification phase. In a dual verification operation, the programming verification voltage is applied to the selected word line in two separate pulses, during each of the two separate pulses, by individually activating the corresponding select gate device that connects the sub-block to the common bit line to sense the current in the corresponding sub-block (i.e., the current through the memory string forming the sub-block). Therefore, there is a delay associated with the two separate pulses (and the corresponding sensing operation), including additional time related to the programming verification voltage ramping up and ramping down twice. In seamless verification operations, the programming verification voltage is applied to the selected word line only once, and the current in both sub-blocks is sensed continuously (i.e., by activating one select gate device first and then the other). Therefore, a delay still exists under the two separate sensing operations, although this is slightly reduced by making the programming verification voltage ramp and sag only once. However, the total delay still increases the length of the programming operation, which may be particularly noticeable in high-priority, time-sensitive operations such as single-level cell (SLC) programming operations.

[0018] This disclosure addresses the above and other shortcomings by implementing joint single-level cell (SLC) verification in a memory device within a memory subsystem. In a joint SLC verification operation, the control logic in the memory device can simultaneously (i.e., at least partially overlap in time) verify that memory cells in two separate sub-blocks have been successfully programmed using data from two separate pages with a single sensing operation. When multiple sub-blocks are programmed in a single programming operation, the control logic can enable the memory strings corresponding to the two sub-blocks in parallel (e.g., simultaneously) during subsequent programming verification phases. Since the word lines in the block (including both the selected word line being programmed and the unselected word line) are common to both sub-blocks, no changes are needed when biasing the word lines. Because the memory strings forming the two sub-blocks can independently draw current from the common bit lines, the joint verification operation cannot be used to disable cells that have passed programming verification (i.e., have reached the target programming voltage level). Therefore, as the programming operation progresses, the width of the programming distribution will track the natural programming changes of the cells. Thus, joint SLC verification can be used to make a pass or fail determination for an associated programming operation. During joint SLC verification, in one embodiment, only cell pairs where both cells are programmed (i.e., from sub-block pairs) are sensed. Because the cells are sensed in pairs, the total number of bits being verified is halved compared to a double verification or seamless verification operation, and the result indicates that both cells have been programmed to a voltage level higher than the programming verification level. To determine the number of bytes that failed programming verification, the control logic can count individual failed bits as failed bytes. Therefore, when the number of bytes that failed programming verification meets a threshold criterion (e.g., below a specific threshold level), the control logic can determine that the programming verification was successful and can proceed to the next programming operation.

[0019] The advantages of this method include, but are not limited to, improved memory device performance. The joint SLC verification operation described herein allows the programming of multiple SLC pages to be verified in parallel (e.g., simultaneously) within a single verification operation. This results in fewer verification operations being performed (e.g., half the number of verification operations) for the same amount of data being programmed into the memory device. Consequently, the latency associated with the entire programming operation is reduced, which improves SLC programming performance.

[0020] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing means (e.g., a processor).

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1A The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller for media management within the same memory device package (e.g., memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0036] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 handles interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. In some embodiments, memory subsystem controller 115 includes at least a portion of memory interface 113. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, memory interface component 113 is part of host system 110, an application, or an operating system.

[0037] In one embodiment, memory device 130 includes a local media controller 135 and a memory array 104. As described herein, the local media controller 135 can perform programming operations on memory cells of memory array 104. The programming operation may include, for example, a programming phase and a programming verification phase. During the programming phase, a programming voltage is applied to a selected word line of memory array 104 to program a specific charge level representing a desired value to a selected memory cell on the word line. During the programming verification phase, a read voltage is applied to the selected word line to read the charge level stored at the selected memory cell to confirm that the desired value has been properly programmed. In one embodiment, the local media controller 135 may utilize a joint single-level cell (SLC) verification operation to verify, in parallel (i.e., at least partially overlapping in time), the successful programming of memory cells in two separate sub-blocks of a block of memory block array 104 using data from two separate pages with a single sensing operation. In one embodiment, the local media controller 135 may identify a set of memory cells in a block of memory array 104, said set of memory cells including two or more memory cells programmed during the programming phase of the programming operation and associated with a selected word line of memory array 104. The local media controller 135 may further cause a programming verification voltage to be applied to a selected word line during the programming verification phase of the programming operation and to perform a parallel sensing operation on the memory cell set to determine whether each memory cell in the memory cell set has been programmed to at least the programming verification voltage during the programming phase. This process may be repeated for multiple memory cell sets in a block of memory array 104, and the local media controller 135 may track (e.g., using a counter) the number of memory cell pairs that have failed to be programmed to at least the programming verification voltage. If the number of memory cell sets that have failed to be programmed meets a threshold criterion (e.g., less than a threshold number), then the local media controller 135 may determine that the block has passed the programming verification phase. If the number of memory cell sets that have failed to be programmed does not meet the threshold criterion (e.g., greater than or equal to a threshold number), then the local media controller 135 may determine that the block has failed the programming verification phase. Further details regarding the operation of the local media controller 135 are described below.

[0038] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1AA simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0039] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the image) can be programmed to one of at least two target data states.

[0040] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 160, row decoding circuitry 108, and column decoding circuitry 109 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0041] A controller (e.g., a local media controller 135 within memory device 130) responds to a command to control access to memory cell array 104 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 109 to control them in response to an address. In one embodiment, the local media controller 135 may perform a joint single-level cell (SLC) verification operation to verify, in parallel (i.e., at least partially overlapping in time), the successful programming of memory cells in two separate sub-blocks of a block of memory block array 104 using data from two separate pages via a single sensing operation.

[0042] The local media controller 135 also communicates with cache register 172. Cache register 172 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 172 to data register 170 for transmission to the memory cell array 104; new data can then be latched from I / O control circuitry 160 into cache register 172. During read operations, data can be transferred from cache register 172 to I / O control circuitry 160 for output to memory subsystem controller 115; new data can then be transferred from data register 170 to cache register 172. Cache register 172 and / or data register 170 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may additionally include sensing devices ( Figure 1B (Not shown in the diagram), it is used to sense the data status of the memory cells, for example, by sensing the status of the data lines connected to the memory cells of the memory cell array 104. The status register 122 can communicate with the I / O control circuitry system 160 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0043] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0044] For example, commands can be received at I / O control circuitry system 160 via I / O pins [7:0] of input / output (I / O) bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry system 160 via I / O pins [7:0] of input / output (I / O) bus 134 and then written to address register 114. Data can be received at I / O control circuitry system 160 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 172. The data can then be written to data register 170 for programming memory cell array 104.

[0045] In this embodiment, cache register 172 may be omitted, and data may be written directly to data register 170. Data may also be output on input / output (I / O) pins [7:0] for 8-bit devices or on input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0046] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0047] Figure 2 As can be used as a reference according to the embodiments Figure 1B A schematic diagram of a portion of a memory cell array 104 (e.g., a NAND memory array) in a memory of the described type. The memory array 104 includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to data cables not in... Figure 2 The global access lines (e.g., global word lines) shown in the diagram. In some embodiments, the memory array 104 may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0048] The memory array 104 can be arranged in rows (each row corresponds to word lines 202) and columns (each column corresponds to bit lines 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cell 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain transistor). Select transistors 2100 to 210 M They can be connected together to select line 214, such as the source select line (SGS), and select transistors 2120 to 212. M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, each selected gate being configured in series to receive the same or independent control signals.

[0049] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0050] The drain of each select gate 212 can be connected to bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to memory cell 208 in the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0051] Figure 2 The memory array 104 can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 104 in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0052] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236, such as... Figure 2 As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0053] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may often be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 often contains every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202 NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0054] Although Figure 2 Bit lines 2043-2045 are not explicitly depicted in the figure, but it is evident from the figure that bit lines 204 of the memory cell array 104 can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell. This is in conjunction with the discussion of NAND flash memory. Figure 2 Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0055] Figure 3A This is a schematic diagram of a portion of a memory cell array implementing Joint Single-Level Cell (SLC) verification according to some embodiments of the present disclosure. A portion of the memory cell array (e.g., memory array 104) may be, for example, block 300. In one embodiment, block 300 includes strings of memory cells that can be divided into sub-blocks (e.g., sub-blocks 3050-3053). In other embodiments, it may include a different number of sub-blocks.

[0056] Specifically, in at least some embodiments, block 300 includes bit line 304, wherein each sub-block is coupled to bit line 304. First sub-block 3050 may include a first drain-select (SGD) transistor 3120, a first source-select (SGS) transistor 3100, and a first memory cell string 3060 coupled therebetween. Second sub-block 3051 may include a second SGD transistor 3121, a second SGS transistor 3101, and a second memory cell string 3061 coupled therebetween. Third sub-block 3052 may include a third SGD transistor 3122, a third SGS transistor 3102, and a third memory cell string 3062 coupled therebetween. Fourth sub-block 3053 may include a fourth SGD transistor 3123, a fourth SGS transistor 3103, and a fourth memory cell string 3063 coupled therebetween. By way of example, the first memory cell string 3060 includes a plurality of memory cells 3080, ..., 308 N Each SGS transistor can be connected to a common source (SRC), such as a source voltage line, to provide voltage to multiple memory cells 3080, ..., 3080. N The source. In some embodiments, the source voltage line includes a source plate that provides the source voltage. In at least some embodiments, a plurality of word lines (WL) are coupled to the gate of the memory cell of each memory cell string 3060, ..., 3063.

[0057] In these embodiments, a first drain-select gate line (SGD0) can be connected to the gate of a first SGD transistor 3120, a second drain-select gate line (SGD1) can be connected to the gate of a second SGD transistor 3121, a third drain-select gate line (SGD2) can be connected to the gate of a third SGD transistor 3122, and a fourth drain-select gate line (SGD3) can be connected to the gate of a fourth SGD transistor 3123. Additionally, a first source-select gate line (SGS0) can be connected to the gate of a first SGS transistor 3100, a second source-select gate line (SGS1) can be connected to the gate of a second SGS transistor 3101, a third source-select gate line (SGS2) can be connected to the gate of a third SGS transistor 3102, and a fourth source-select gate line (SGS3) can be connected to the gate of a fourth SGS transistor 3103.

[0058] In one embodiment, the local media controller 135 may perform a joint single-level cell (SLC) verification operation to verify, in parallel (i.e., at least partially overlapping in time), the successful programming of memory cells in two separate sub-blocks of block 300 using data from two separate pages with a single sensing operation. In one embodiment, the local media controller 135 may identify a set of memory cells in block 300, such as memory cells 308 programmed during the programming phase of a programming operation.x and 314. Memory unit 308 x 314 is associated with the selected word line WLx and each is associated with a different sub-block and memory string. For example, memory cell 308... x The memory cell 314 is a portion of the memory string 3060 forming sub-block 3050, and the memory cell 314 is a portion of the memory string 3061 forming sub-block 3051. In one embodiment, the memory cell set contains two memory cells; however, in other embodiments, the memory cell set may contain additional memory cells. In one embodiment, the memory cells in the memory cell set are portions of adjacent sub-blocks within block 300; however, in other embodiments, the memory cells in the memory cell set may not be adjacent.

[0059] In one embodiment, to perform a joint SLC verification operation, the local media controller 135 may cause a programming verification voltage to be applied to a selected word line, such as WLx, during the programming verification phase of the programming operation. The local media controller 135 may additionally perform a parallel sensing operation on the set of memory cells to determine whether each memory cell in the set of memory cells has been programmed to at least the programming verification voltage during the programming phase. Figure 3B As described, the local media controller 135 can cause a single pulse with a programming verification voltage level 350 to be applied to a selected word line and activate corresponding select gate devices in parallel (e.g., simultaneously), such as the first SGD transistor 3120 and the second SGD transistor 3121. For example, signals 352 on the first drain select gate line (SGD0) and the second drain select gate line (SGD1) can be driven high in parallel. During these parallel sensing operations, the local media controller 135 can determine whether current from the shared bit line 304 flows through a memory cell (e.g., memory cell 308) that contains the memory cell set. x Each of the corresponding memory strings (3060 and 3061) is an example. If the memory cells in the memory cell set are programmed to at least the programming verification voltage during the programming phase of the programming operation, then the current from the shared bit line 304 does not flow through the corresponding memory string, indicating that the memory cell set has passed the programming verification phase.

[0060] This process can be repeated for multiple sets of memory cells in block 300, and the local media controller 135 can track (e.g., using a counter) the number of memory cell sets that have failed to be programmed to at least the programming verification voltage. If the number of memory cell sets that have failed to be programmed meets a threshold criterion (e.g., less than a threshold number), then the local media controller 135 can determine that block 300 has passed the programming verification phase. If the number of memory cell sets that have failed to be programmed does not meet the threshold criterion (e.g., greater than or equal to the threshold number), then the local media controller 135 can determine that block 300 has failed the programming verification phase.

[0061] Figure 4 This is a flowchart of an example method for joint single-level cell (SLC) verification in a memory device according to some embodiments of the memory subsystem of this disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1A and Figure 1B The local media controller 135 executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0062] At operation 405, the memory cell is programmed. For example, processing logic (e.g., local media controller 135) may perform the programming phase of the programming operation. In one embodiment, the processing logic may cause a dual pulse with a programming voltage level to be applied to a selected word line of a block of the memory array, such as word line WL of block 300 of memory array 104 of memory device 130. x ,like Figure 3A As shown in the diagram. This type of dual pulse can be used to program a set of memory cells associated with a selected word line, such as memory cell 308, using corresponding bits from two separate data pages. x And 314. In other embodiments, a different number of memory cells or a different set of memory cells may be programmed during the programming phase.

[0063] At operation 410, the programmable memory cell is verified. For example, the processing logic may initiate a programming verification phase of the programming operation. In one embodiment, the programming verification phase is initiated in response to the completion of the programming phase. As described in more detail below, during the programming verification phase, a read voltage is applied to a selected word line, such as WL.x This allows reading the charge level stored in a selected memory cell to confirm the appropriate programming of the desired value.

[0064] At operation 415, the set of memory cells is identified. For example, the processing logic may identify the set of memory cells in block 300, such as memory cell 308 that is programmed during the programming phase of the programming operation. x and 314. Memory unit 308 x 314 is associated with the selected word line WLx and each is associated with a different sub-block and memory string. For example, memory cell 308... x It is a portion of the memory string 3060 forming sub-block 3050 and memory cell 314 is a portion of the memory string 3061 forming sub-block 3051. In one embodiment, all memory cells in the memory cell set are memory cells that are programmed during programming operations (i.e., storing a specific charge level representing a desired value, compared to those memory cells that are not programmed to any particular voltage level).

[0065] At operation 420, a voltage is applied to the memory array. For example, the processing logic could cause a programming verification voltage to be applied to a selected word line, such as WL, during the programming verification phase of the programming operation. x In one embodiment, such as Figure 3B As described herein, the local media controller 135 may cause a single pulse having a programming verification voltage level 350 to be applied to a selected word line. In one embodiment, the programming verification voltage level has an amount lower than the programming voltage level.

[0066] At operation 425, a sensing operation is performed. For example, the processing logic may perform a parallel sensing operation on the set of memory cells to determine whether each memory cell in the set of memory cells has been programmed to at least a programming verification voltage during the programming phase of a programming operation. In one embodiment, when the programming verification voltage is applied to a selected word line, the local media controller 135 may activate, in parallel (e.g., simultaneously), the corresponding select gate means, such as the first SGD transistor 3120 and the second SGD transistor 3121, for memory cells in the identified set of memory cells. For example, signals 352 on the first drain select gate line (SGD0) and the second drain select gate line (SGD1) may be driven high in parallel.

[0067] At operation 430, a determination is made. For example, the processing logic may determine whether the memory cell set has been programmed. During the parallel sensing operation, the local media controller 135 may determine whether current from shared bit line 304 flows through each corresponding memory string, such as memory strings 3060 and 3061. If the memory cells in the memory cell set are programmed to at least the programming verification voltage during the programming phase of the programming operation, then current from shared bit line 304 does not flow through the corresponding memory string, indicating that the memory cell set has passed the programming verification phase. Conversely, if the memory cells in the memory cell set are not programmed to at least the programming verification voltage during the programming phase of the programming operation, then current from shared bit line 304 does flow through the corresponding memory string, indicating that the memory cell set has not passed the programming verification phase.

[0068] If the set of memory cells is not programmed, then at operation 435, a counter is incremented. For example, the processing logic may maintain a counter, such as a count-not-passed-byte (CFBYTE) counter. In one embodiment, the counter is incremented in each case where it is determined that all memory cells in a given set of memory cells are not sufficiently programmed (i.e., not programmed to at least the programming verification voltage). Therefore, the value of the counter tracks the number of memory cells in the set that have failed to be programmed to at least the programming verification voltage.

[0069] Once it is determined at operation 430 that the memory cell set has been programmed, or a counter is incremented at operation 435, processing can continue to operation 430. At operation 440, a determination is made. For example, the processing logic may determine whether there is an additional memory cell set to be verified. As described above, a memory cell set may comprise two or more memory cells from all memory cells in a block that were programmed during the programming phase of the programming operation. In one embodiment, each of these memory cells is assigned to a memory cell set that can be verified using joint SLC verification, as described herein. In one embodiment, if there is a specific group of cells to be verified, then the group may be divided into sets, with different joint verification operations performed on each set. For example, in the case of SLC, if four sub-blocks are programmed together, then all four sub-blocks may be combined for a single verification operation, or two separate joint verification operations may be performed on each of the two sub-blocks. Other embodiments may utilize different verification levels for SLC memory or other memory types, such as TLC, QLC, etc. Therefore, if there is an additional set of memory cells to be verified, the process can return to operation 415, and operations 415-435 can be repeated. If there is no additional set of memory cells to be verified (i.e., if all memory cells have been verified), the process can continue to operation 445.

[0070] At operation 445, a determination is made. For example, the processing logic can determine whether the counter meets the threshold criterion.

[0071] If the number of unprogrammable memory cell sets meets the threshold criterion (e.g., is less than the threshold number), then at operation 450, the processing logic can determine that block 300 has passed the programming verification phase. Subsequently, a new programming operation can be initiated.

[0072] If the number of unprogrammed memory cells does not meet the threshold criterion (e.g., greater than or equal to the threshold number), then at operation 455, the processing logic can determine that block 300 has failed the programming verification stage. Subsequently, an additional programming stage and a programming verification stage from the previous programming operation can be performed to ensure that the memory cells are properly programmed to their target voltage level.

[0073] Figure 5 An example machine illustrating computer system 500 is described, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., host system 120 of FIG1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of FIG1), or may be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to local media controller 135 of FIG1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0074] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0075] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0076] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed herein. Computer system 500 may additionally include a network interface device 508 for communication on network 520.

[0077] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more instruction sets 526 or software embodying any or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to memory subsystem 110 of FIG. 1.

[0078] In one embodiment, instruction 526 includes instructions for implementing functionality corresponding to the local media controller 135 of FIG1. ​​Although machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0080] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0081] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0083] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device, comprising: a memory array; and control logic, operably coupled with the memory array, to perform operations including: identifying a set of memory cells in a block of the memory array, wherein the set of memory cells includes two or more memory cells programmed during a program phase of a program operation and associated with a selected word line of the memory array; causing a program verify voltage to be applied to the selected word line during a program verify phase of the program operation; performing a parallel sense operation on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation; and in response to determining that each memory cell in the set of memory cells was not programmed to at least the program verify voltage during the program phase of the program operation, incrementing a value of a counter, wherein the value of the counter indicates whether the block of the memory array has passed the program verify phase of the program operation.

2. The memory device of claim 1, wherein the control logic is to further perform operations including: performing the program phase of the program operation; and in response to completion of the program phase of the program operation, initiating the program verify phase of the program operation.

3. The memory device of claim 1, wherein the two or more memory cells in the set of memory cells are each associated with adjacent sub-blocks of the block of the memory array.

4. The memory device of claim 1, wherein the two or more memory cells in the set of memory cells are each associated with different respective memory strings of the memory array.

5. The memory device of claim 4, wherein performing the parallel sense operation includes: parallel activating respective select gate devices coupled between each respective memory string of the memory array and a shared bit line; and sensing whether a current from the shared bit line flows through each respective memory string.

6. The memory device of claim 5, wherein the current from the shared bit line does not flow through each respective memory string if each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

7. The memory device of claim 1, wherein the control logic is to further perform operations including: determining whether one or more additional sets of memory cells programmed during the program phase of the program operation are present in the block of the memory array.

8. The memory device of claim 7, wherein the control logic is to further perform operations including: in response to determining that no additional sets of memory cells programmed during the program phase of the program operation are present in the block of the memory array, determining whether the value of the counter satisfies a threshold criterion; and ​ determining that the block of the memory array has passed the program verify phase of the program operation in response to determining that the value of the counter satisfies a threshold criterion.

9. A method comprising: identifying a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected word line of the memory array; causing a program verify voltage to be applied to the selected word line during a program verify phase of the program operation; performing a parallel sense operation on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation; and incrementing a value of a counter in response to determining that each memory cell in the set of memory cells was not programmed to at least the program verify voltage during the program phase of the program operation, wherein the value of the counter indicates whether the block of the memory array has passed the program verify phase of the program operation.

10. The method of claim 9, further comprising: performing the program phase of the program operation; and initiating the program verify phase of the program operation in response to the program phase of the program operation completing.

11. The method of claim 9, wherein the two or more memory cells in the set of memory cells are each associated with adjacent sub-blocks of the block of the memory array.

12. The method of claim 9, wherein the two or more memory cells in the set of memory cells are each associated with different respective memory strings of the memory array.

13. The method of claim 12, wherein performing the parallel sense operation comprises: parallel activating respective select gate devices coupled between each respective memory string of the memory array and a shared bit line; and sensing whether current from the shared bit line flows through each respective memory string.

14. The method of claim 13, wherein the current from the shared bit line does not flow through each respective memory string if each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

15. The method of claim 9, further comprising: determining whether one or more additional sets of memory cells programmed during the program phase of the program operation are present in the block of the memory array.

16. The method of claim 15, further comprising: determining whether the value of the counter satisfies a threshold criterion in response to determining that no additional sets of memory cells programmed during the program phase of the program operation are present in the block of the memory array; and determining that the block of the memory array has passed the program verify phase of the program operation in response to determining that the value of the counter satisfies a threshold criterion.

17. A memory device comprising: a memory array; and control logic, operably coupled with the memory array, to perform operations including: initiating a program operation on the memory array, the program operation comprising a program phase and a program verify phase; and causing a double pulse having a program voltage level to be applied to a selected word line of the memory array during the program phase to program a pair of memory cells associated with the selected word line; causing a single pulse having a program verify voltage level to be applied to the selected word line of the memory array during the program verify phase to verify in parallel that the pair of memory cells were programmed to at least the program verify voltage level during the program phase of the program operation; and in response to determining that the pair of memory cells were not programmed to at least the program verify voltage during the program phase of the program operation, incrementing a value of a counter, wherein the value of the counter indicates whether a block of the memory array has passed the program verify phase of the program operation.

18. The memory device of claim 17, wherein the pair of memory cells are each associated with a different sub-block of the block of the memory array, and wherein the control logic is to further perform operations including: activating respective select gate devices associated with each different sub-block in parallel during the program verify phase; and determining whether respective strings of memory associated with each different sub-block are conducting.

19. The memory device of claim 18, wherein the control logic is to further perform operations including: in response to determining that the respective strings of memory associated with each different sub-block are conducting, incrementing the value of a counter; and determining whether there are one or more additional pairs of memory cells programmed during the program phase of the program operation in the block of the memory array.

20. The memory device of claim 19, wherein the control logic is to further perform operations including: in response to determining that there are no additional sets of memory cells programmed during the program phase of the program operation in the block of the memory array, determining whether the value of the counter satisfies a threshold criterion; and in response to determining that the value of the counter satisfies a threshold criterion, determining that the block of the memory array has passed the program verify phase of the program operation.

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