Semiconductor structure and manufacturing method thereof, and memory

Abstract

The embodiments of the present application relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: two layers of photolithography layers arranged in sequence, each of which includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer, the first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; at least one blocking layer, the blocking layer is located between the first functional pattern and the second functional pattern, and in the stacking direction of the photolithography layers, the vertical distance between the first functional pattern and the second functional pattern is greater than the vertical spacing between the first overlay mark and the second overlay mark. The embodiments of the present application are conducive to improving the electrical performance of the semiconductor structure and the memory.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular to a semiconductor structure and a manufacturing method thereof, and a memory. Background Art

[0002] The photolithography process is a process of transferring the mask pattern to the wafer through a series of steps such as alignment and exposure. In the process of semiconductor structure manufacturing, multiple photolithography processes are usually required to achieve overlay. However, due to various factors in the photolithography process that cannot reach the ideal state, the pattern left on the wafer after exposure and development cannot be completely aligned with the existing pattern on the wafer. Therefore, it is necessary to accurately measure the offset between the pattern left on the wafer after exposure and development and the existing pattern on the wafer, that is, the overlay error, so that the overlay error can be effectively compensated and corrected in the subsequent process, so that the final semiconductor structure has the expected effect. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, and a memory, which are at least beneficial to improving the electrical performance of the semiconductor structure and the memory.

[0004] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a semiconductor structure, which may include at least: two layers of photolithography layers arranged in sequence, each of the photolithography layers including a functional pattern and an overlay mark, the photolithography layers including a first photolithography layer and a second photolithography layer, the first photolithography layer including a first functional pattern and a first overlay mark, the second photolithography layer including a second functional pattern and a second overlay mark; at least one blocking layer, the blocking layer being located between the first functional pattern and the second functional pattern, and in the stacking direction of the photolithography layers, a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical spacing between the first overlay mark and the second overlay mark.

[0005] In addition, the semiconductor structure includes a functional area and a cutting path, the cutting path is located between adjacent functional areas, and the functional pattern and the blocking layer are arranged in the functional area.

[0006] In addition, the integrated structure including the blocking layer is further located at least one of within the first photolithography layer, within the second photolithography layer, below the first photolithography layer, or above the second photolithography layer.

[0007] In addition, the functional pattern and the overlay mark are composed of raised structures arranged in an array; the semiconductor structure also includes: a filling part, the filling part is filled between adjacent raised structures, and the blocking layer and the filling part are an integral structure.

[0008] In addition, the protruding structures include lines or bumps.

[0009] In addition, the functional pattern and the overlay mark are composed of hole structures arranged in an array; the semiconductor structure also includes: a filling part, the filling layer is filled in the hole structure, and the blocking layer and the filling part are an integrated structure.

[0010] In addition, the cavity structure includes gaps or holes.

[0011] In addition, the material of the barrier layer includes a conductive material.

[0012] Additionally, the conductive material includes tungsten.

[0013] In addition, the functional pattern includes a periodic grating structure arranged along a first direction, and the overlay mark includes at least another periodic grating structure arranged along the first direction.

[0014] In addition, the overlay mark further includes a periodic grating structure arranged along a second direction, and the second direction is perpendicular to the first direction.

[0015] According to some embodiments of the present application, on the other hand, embodiments of the present application further provide a memory comprising any of the semiconductor structures described above.

[0016] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a method for manufacturing a semiconductor structure, which method for manufacturing a semiconductor structure may at least include: forming two photolithography layers and at least one blocking layer, each of the photolithography layers including a functional pattern and an overlay mark, the photolithography layers including a first photolithography layer and a second photolithography layer, the first photolithography layer including a first functional pattern and a first overlay mark, the second photolithography layer including a second functional pattern and a second overlay mark; at least one blocking layer, the blocking layer being located between the first functional pattern and the second functional pattern, and in the stacking direction of the photolithography layers, the vertical distance between the first functional pattern and the second functional pattern is greater than the vertical spacing between the first overlay mark and the second overlay mark.

[0017] In addition, the semiconductor structure includes functional areas and cutting paths, and the cutting paths are located between adjacent functional areas; the process steps for forming the blocking layer and the second photolithography layer include: after forming the first photolithography layer, covering the cutting paths and exposing the functional areas; forming the blocking layer, which is located in the functional areas and on the first functional pattern; forming the second photolithography layer, which covers the top surface of the blocking layer and the top surface of the cutting paths of the first photolithography layer.

[0018] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0019] In the above technical scheme, in the stacking direction of the photolithography layer, the vertical spacing between the first overlay mark and the second overlay mark is smaller than the vertical spacing between the first functional pattern and the second functional pattern. This is helpful to avoid the film layer between the first overlay mark and the second overlay mark from transmitting weak light to the first photolithography layer, and to avoid the first diffraction signal formed by reflection from the first overlay mark from being weak, thereby ensuring that the first diffraction signal corresponding to the first overlay mark and the second diffraction signal corresponding to the second overlay mark have more obvious asymmetry in light intensity distribution after overlapping, thereby avoiding the light intensity distribution of the overlapping signal from being affected by external light or the light intensity distribution tending to be symmetrical, thereby accurately measuring the overlay error of different photolithography layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0021] Figures 1 to 3 A schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The detection of overlay error is generally divided into after development inspection (ADI) and after etching inspection (AEI). After development inspection refers to the measurement of critical dimension (CD) after development, which is generally used to detect the performance indicators of exposure machine and developer. After exposure and development are completed, the ADI machine conducts a qualitative inspection on the generated graphics to determine whether the graphics are normal. Since it cannot be measured by transmitted light, ADI is generally measured by electron beam or scanning electron microscope. After etching inspection refers to the CD measurement after etching. Before and after the removal of photoresist in the etching process, the product is fully inspected or sampled.

[0023] The overlay error can generally be measured by image recognition-based measurement technology (Image Based Overlay, IBO), scanning electron microscope (Scanning Electron microscope, SEM) and new diffraction measurement technology (In Die Metrology, IDM). IDM collects zero-order diffraction light from different lithography layers and determines the overlay error of different marking layers based on the asymmetry of the intensity distribution of the zero-order diffraction light. Ideally, if there is an offset between different lithography layers (assuming the first lithography layer and the second lithography layer), the intensity distribution of the zero-order diffraction light finally collected has obvious asymmetry, and the zero-order diffraction light is composed of a first diffraction signal corresponding to the first lithography layer and a second diffraction signal corresponding to the second lithography layer.

[0024] The present application provides a semiconductor structure, which is arranged in the stacking direction of the lithography layer, and the vertical spacing between different overlay marks is greater than the overlay marks of the corresponding functional patterns. This is beneficial to reduce the obstruction of the film layers between the different overlay marks to the transmitted light and the reflected light, and ensure that the searchlight transmitted to the bottom lithography layer has a larger light intensity after reflection and diffraction, so that the intensity distribution of the zero-order diffraction light finally collected has obvious asymmetry, avoiding the light intensity distribution of the zero-order diffraction light finally collected being the same or similar to the light intensity distribution of the diffraction signal corresponding to the top lithography layer due to the weak light intensity of the diffraction signal corresponding to the bottom lithography layer, thereby ensuring the accuracy of the measurement result.

[0025] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0026] Figures 1 to 3 A schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present application.

[0027] refer to Figure 1 to Figure 2The semiconductor structure includes: two layers of photolithography layers arranged in sequence, each photolithography layer includes a functional pattern and an overlay mark, the photolithography layer includes a first photolithography layer 10 and a second photolithography layer 20, the first photolithography layer 10 includes a first functional pattern 112 and a first overlay mark 111, and the second photolithography layer 20 includes a second functional pattern 212 and a second overlay mark 211; at least one barrier layer 312a, the barrier layer 312a is located between the first functional pattern 112 and the second functional pattern 212, and in the stacking direction of the photolithography layers, the vertical distance between the first functional pattern 112 and the second functional pattern 212 is greater than the vertical spacing between the first overlay mark 111 and the second overlay mark 211.

[0028] It is known that, in common cases, the object of any process step is the entire photolithography layer, that is, the film structure of different regions of the same photolithography layer is the same, or in other words, the film structure of at least two regions is the same, and when a blocking layer 312a is provided between the first functional pattern 112 and the second functional pattern 212, a corresponding blocking layer is generally provided between the first overlay mark 111 and the second overlay mark 211. When the overlay error of the first overlay mark 111 and the second overlay mark 211 is measured using the IDM technology, the blocking layer between the first overlay mark 111 and the second overlay mark 211 will weaken the light transmitted to the first photolithography layer 10 and the light reflected from the first photolithography layer 10, thereby causing the light intensity of the first diffraction signal corresponding to the first photolithography layer 10 to be weak.

[0029] When calculating the overlay error using the first diffraction signal corresponding to the first lithography layer 10 and the second diffraction signal corresponding to the second lithography layer 20, since the light intensity of the first diffraction signal is relatively weak, the light intensity asymmetry of the zero-order diffraction light finally collected is relatively weak. When calculating the overlay error using the light intensity difference, since the actual light intensity difference corresponding to the same offset is less than the preset light intensity difference, the calculated overlay error may be less than the actual overlay error. In addition, since the light intensity of the first diffraction signal is relatively weak, the interference of external light on the zero-order diffraction light is more obvious, which easily leads to the calculated overlay error being greater than the actual overlay error. By controlling the vertical distance between the first overlay mark 111 and the second overlay mark 211 to be less than the vertical distance between the first functional pattern 112 and the second functional pattern 212, thinning or even removing the blocking layer between the first overlay mark 111 and the second overlay mark 211, it is beneficial to suppress the blocking and weakening of the light by the intermediate film layer, and ensure that the zero-order diffraction light finally measured has a relatively obvious light intensity distribution asymmetry in the presence of the offset, thereby achieving accurate measurement of the overlay error.

[0030] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0031] In some embodiments, the semiconductor structure includes a functional area and a cutting path, the cutting path is located between adjacent functional areas, and the functional pattern and the blocking layer 312a are arranged in the functional area; in addition, in some embodiments, the overlay mark is located in the cutting path. It can be understood that the functional area and the cutting path are used to divide different areas of the semiconductor structure or chip in the plane extension direction. In the stacking direction of the photolithography layer, different photolithography layers have corresponding functional areas and cutting paths. For example, the first photolithography layer 10 has a first cutting path 11 and a first functional area 12, the first overlay mark 111 is located in the first cutting path 11, and the first functional pattern 112 is located in the first functional area 12. Correspondingly, the second photolithography layer 20 has a second cutting path 21 and a second functional area 22, the second overlay mark 211 is located in the second cutting path 21, and the second functional pattern 212 is located in the second functional area 22.

[0032] In which, in the stacking direction of the photolithography layer, the projections of the first cutting street 11 and the second cutting street 21 overlap, and the projections of the first functional area 12 and the second functional area 22 overlap; in addition, the first cutting street 11 and the first functional area 12 may or may not be in the same plane, and correspondingly, the second cutting street 21 and the second functional area 22 may or may not be in the same plane.

[0033] In some embodiments, the integrated structure including the blocking layer 312a is further located at least one of within the first photolithography layer 10, within the second photolithography layer 20, below the first photolithography layer 10, or above the second photolithography layer 20. Below the first photolithography layer 10 refers to a side of the first photolithography layer 10 facing away from the second photolithography layer 20, and above the second photolithography layer 20 refers to a side of the second photolithography layer 20 facing away from the first photolithography layer 10.

[0034] In some embodiments, the functional pattern and the overlay mark are composed of convex structures arranged in an array; the semiconductor structure further comprises: a filling portion, the filling portion is filled between adjacent convex structures, and the blocking layer and the filling portion are an integral structure. Figure 2 The semiconductor structure includes a first filling portion 312b located in the functional area and a second filling portion 311 located in the cutting path, the first filling portion 312b is filled between adjacent first functional patterns 112, the second filling portion 311 is filled between adjacent first engraved marks 111, and the blocking layer 312a covers the surface of the first filling portion 312b and the first functional pattern 112, and the first filling portion 312b and the blocking layer 312a are an integrated structure.

[0035] In some embodiments, the process steps for forming the first filling part 312b, the second filling part 311 and the blocking layer 312a include: after forming the first functional pattern 112 and the first overlay mark 111, performing a deposition process to simultaneously form the first filling part 312b and the second filling part 311; after forming the second filling part 311, covering the cutting road and exposing the functional area, and continuing to deposit to form the blocking layer 312a. It can be understood that in this process step, the first filling part 312b, the second filling part 311 and the blocking layer 312a are formed using the same process step, the first filling part 312b and the second filling part 311 are an integrated structure, and the first filling part 312b and the blocking layer 312a are an integrated structure.

[0036] In another embodiment, different deposition processes are used to deposit materials in the functional area and the cutting road, respectively. For example, the functional area is first covered and the cutting road is exposed, and a first deposition process is used to deposit and form the second filling part 311, and then the cutting road is covered and the functional area is exposed, and a second deposition process is used to deposit and form the first filling part 312b and the blocking layer 312a.

[0037] In some embodiments, the blocking layer 312a is only disposed between the first functional pattern 112 and the second functional pattern 212; in other embodiments, the blocking layer is also disposed between the first overlay mark and the second overlay mark, and the thickness of the blocking layer disposed between the overlay marks is less than the thickness of the blocking layer disposed between the functional patterns. In addition, the blocking layer 312a can be either a single-layer film layer or a laminated structure. The blocking layer 312a refers to a film layer that blocks and weakens light, and does not refer to a film layer specifically used to block light or block other media or ions. In other words, this article does not limit the material of the blocking layer 312a. It is generally believed that all film layers will block the propagation of light.

[0038] In some embodiments, the raised structure includes a line or a bump. A line is a raised structure extending in one direction, with a large aspect ratio, and a bump is a protruding structure, with a small aspect ratio. The shape of the line or the bump is not limited herein, as long as it can form a corresponding diffraction signal. For example, the bump can be in the shape of a square, a rectangle, a parallelogram, etc.

[0039] In some embodiments, the functional pattern and the overlay mark are composed of a hole structure arranged in an array; the semiconductor structure also includes: a filling part, the filling part is filled in the hole structure, and the barrier layer and the filling part are an integral structure. In other words, the functional pattern and the overlay mark can be not only a solid structure such as a convex structure, but also a hollow structure such as a hole structure. The hole structure includes a gap or a hole. The gap corresponds to a line and extends in one direction. The hole corresponds to a bump and is convex or concave relative to the surrounding area. In addition, if the functional pattern and the overlay mark are hollow structures, other materials may not be filled in the hollow structure.

[0040] In addition, the material of the blocking layer 312a can be a dielectric material or a conductive material. The dielectric material includes silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, etc. The conductive material includes doped conductive material (such as doped polysilicon), metal material (such as tungsten, copper, silver and gold) and metal compound (such as titanium nitride and indium tin oxide). In the actual production process, in order to avoid a large top surface height difference between the functional area and the cutting road, it is necessary to limit the thinning degree of the blocking layer 312a. In this context, the film layer composed of a material with stronger light blocking performance can be thinned, thereby improving the asymmetry of the intensity distribution of the zero-order diffraction light finally collected, and realizing accurate measurement of the overlay error.

[0041] In some embodiments, the functional pattern and the corresponding overlay mark are both periodic grating structures, and the grating arrangement directions of the functional pattern and the corresponding overlay mark are the same; in another embodiment, the functional pattern and the corresponding overlay mark are both periodic grating structures, but each photolithography layer has multiple groups of overlay marks, and there are at least two different grating arrangement directions in the multiple groups of overlay marks, and the two different grating arrangement directions can be perpendicular to each other, and the grating arrangement direction of the functional pattern is the same as the grating arrangement direction of one group of overlay marks; in yet another embodiment, the functional pattern and the corresponding overlay mark are both periodic grating structures, and the grating arrangement directions of the functional pattern and the corresponding overlay mark are different, and the grating arrangement direction of the functional pattern is perpendicular to or oblique to the grating arrangement direction of the overlay mark.

[0042] The following will be described in detail with reference to specific embodiments. Figure 3In the functional area of ​​the semiconductor structure, the first functional pattern 112 includes a buried word line 112a and an isolation layer 112b for isolating the buried word line 112a, the isolation layer 112b is located above the buried word line 112a, the blocking layer 312a is a conductive film for forming a bit line conductive film, part of the conductive film is located between adjacent isolation layers 112b, part of the conductive film is located on the isolation layer 112b, part of the conductive film located between adjacent isolation layers 112b serves as a first filling portion 312b, and part of the conductive film located on the isolation layer 112b serves as a blocking layer 312a, the second functional pattern 212 is a developing layer, the developing layer is a mask structure left after exposure and development, and the conductive film is etched through the mask structure to obtain a plurality of discrete bit line conductive layers; accordingly, in the cutting path of the semiconductor structure, only part of the conductive film located between adjacent first set engraving marks 111 is provided as a second filling portion 311. That is to say, by removing or not forming the conductive film on the first overlay mark 111, it is helpful to avoid that this part of the conductive film blocks the incident light and the first diffraction signal formed by reflection and diffraction, thereby ensuring that the first diffraction signal has a larger light intensity, and further ensuring that the zero-order diffraction light composed of the first diffraction signal and the second diffraction signal has a more obvious asymmetry in light intensity distribution, and accurately obtaining the overlay error of the first functional pattern 112 and the second functional pattern 212 based on the first overlay mark 111 and the second overlay mark 211.

[0043] In some embodiments, whether it is an overlay mark or a functional pattern, whether it is a filling layer filled in a hollow overlay mark or a filling layer filled between solid overlay marks, it can be a stacked structure. Assuming that the stacking direction of the photolithography layer is a vertical direction, the stacked structure here can be stacked in the vertical direction or in the horizontal direction, or can store the above two stacking relationships at the same time. It can be understood that the horizontal direction is perpendicular to the vertical direction.

[0044] In the embodiment of the present application, in the stacking direction of the photolithography layer, the vertical spacing between the first overlay mark and the second overlay mark is smaller than the vertical spacing between the first functional pattern and the second functional pattern. This is helpful to avoid the film layer between the first overlay mark and the second overlay mark from transmitting weak light to the first photolithography layer, and to avoid the first diffraction signal formed by reflection from the first overlay mark from being weak, thereby ensuring that the first diffraction signal corresponding to the first overlay mark and the second diffraction signal corresponding to the second overlay mark have a more obvious asymmetry in light intensity distribution after overlapping, thereby avoiding the light intensity distribution of the overlapping signal from being affected by external light or the light intensity distribution tending to be symmetrical, thereby accurately measuring the overlay errors of different photolithography layers.

[0045] Accordingly, the embodiment of the present application also provides a memory, including any of the semiconductor structures described above. The memory prepared based on the semiconductor structure can better correct or even eliminate the overlay error of the functional area, ensure that different functional patterns in the functional area have high alignment accuracy, so that different functional components in the functional area have corresponding preset electrical characteristics, and make the memory have preset electrical performance and the electrical performance of different memories is relatively stable.

[0046] Accordingly, the present application also provides a method for manufacturing a semiconductor structure, which is used to manufacture any of the above semiconductor structures. Figure 1 and Figure 2 The method for manufacturing a semiconductor structure may at least include: forming two layers of photolithography layers arranged in sequence, each photolithography layer includes a functional pattern and an overlay mark, the photolithography layer includes a first photolithography layer 10 and a second photolithography layer 20, the first photolithography layer 10 includes a first functional pattern 112 and a first overlay mark 111, and the second photolithography layer 20 includes a second functional pattern 212 and a second overlay mark 211; at least one barrier layer 312a, the barrier layer 312a is located between the first functional pattern 112 and the second functional pattern 212, and in the stacking direction of the photolithography layers, the vertical distance between the first functional pattern 112 and the second functional pattern 212 is greater than the vertical spacing between the first overlay mark 111 and the second overlay mark 211.

[0047] In some embodiments, the semiconductor structure includes a functional area and a cutting path, and the cutting path is located between adjacent functional areas; the process steps of forming a blocking layer and a second photolithography layer 20 include: after forming the first photolithography layer 10, covering the cutting path and exposing the functional area; forming a blocking layer 312a, the blocking layer 312a is located in the functional area and on the first functional pattern 112; forming a second photolithography layer 20, the second photolithography layer 20 covers the top surface of the blocking layer 312a and covers the top surface of the cutting path of the first photolithography layer 10.

[0048] It is understandable that the above-mentioned covering of the cutting road can refer to a selective deposition process to form the blocking layer 312a only in the functional area; it can also refer to first forming a sacrificial layer on the top surface of the cutting road of the first photolithography layer 10, then performing a maskless deposition process, and finally removing the sacrificial layer and the blocking medium on the sacrificial layer, and only retaining the blocking layer 312a on the top surface of the functional area of ​​the first photolithography layer 10. The use of a mask deposition process or a sacrificial layer covering process to form the blocking layer 312a is conducive to avoiding damage to the first overlay mark 111 caused by etching the blocking material, ensuring that the first overlay mark 111 has good integrity and ensuring that the first diffraction signal formed based on the first overlay mark 111 can better reflect the position signal of the first functional pattern 112, thereby ensuring that the overlay error obtained based on the first overlay mark 111 and the second overlay mark 211 can be used to correct the position of the second functional pattern 212.

[0049] In other embodiments, a blocking film may be first formed by a maskless deposition process, and then the blocking film on the cutting path of the first photolithography layer may be removed by etching, leaving the blocking film on the functional area of ​​the first photolithography layer as a blocking layer.

[0050] In the embodiment of the present application, in the stacking direction of the photolithography layer, the vertical spacing between the first overlay mark and the second overlay mark is smaller than the vertical spacing between the first functional pattern and the second functional pattern. This is helpful to avoid the film layer between the first overlay mark and the second overlay mark from transmitting weak light to the first photolithography layer, and to avoid the first diffraction signal formed by reflection from the first overlay mark from being weak, thereby ensuring that the first diffraction signal corresponding to the first overlay mark and the second diffraction signal corresponding to the second overlay mark have a more obvious asymmetry in light intensity distribution after overlapping, thereby avoiding the light intensity distribution of the overlapping signal from being affected by external light or the light intensity distribution tending to be symmetrical, thereby accurately measuring the overlay errors of different photolithography layers.

[0051] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, It is characterized in that include: Two photolithography layers are arranged in sequence, each of the photolithography layers comprises a functional pattern and an overlay mark, the photolithography layers comprise a first photolithography layer and a second photolithography layer, the first photolithography layer comprises a first functional pattern and a first overlay mark, and the second photolithography layer comprises a second functional pattern and a second overlay mark; At least one blocking layer, the blocking layer is located between the first functional pattern and the second functional pattern, and in the stacking direction of the photolithography layer, the vertical distance between the first functional pattern and the second functional pattern is greater than the vertical spacing between the first overlay mark and the second overlay mark.

2. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure includes a functional area and a cutting path, wherein the cutting path is located between adjacent functional areas, and the functional pattern and the blocking layer are arranged in the functional area.

3. The semiconductor structure according to claim 2, It is characterized in that The overlay mark is located within the dicing street.

4. The semiconductor structure according to claim 1, It is characterized in that The integrated structure including the blocking layer is also located at least one of within the first photolithography layer, within the second photolithography layer, below the first photolithography layer, or above the second photolithography layer.

5. The semiconductor structure according to claim 4, It is characterized in that The functional pattern and the overlay mark are composed of raised structures arranged in an array; the semiconductor structure further comprises: a filling portion, the filling portion is filled between adjacent raised structures, and the blocking layer and the filling portion are an integral structure.

6. The semiconductor structure according to claim 5, It is characterized in that The protruding structures include lines or bumps.

7. The semiconductor structure according to claim 4, It is characterized in that The functional pattern and the overlay mark are composed of hole structures arranged in an array; the semiconductor structure also includes: a filling part, the filling part is filled in the hole structure, and the blocking layer and the filling part are an integrated structure.

8. The semiconductor structure according to claim 7, It is characterized in that The cavity structure includes gaps or holes.

9. The semiconductor structure according to claim 1, It is characterized in that The material of the blocking layer includes a conductive material.

10. The semiconductor structure according to claim 9, It is characterized in that The conductive material includes tungsten.

11. The semiconductor structure according to claim 1, It is characterized in that The functional pattern includes a periodic grating structure arranged along a first direction, and the overlay mark includes at least another periodic grating structure arranged along the first direction.

12. The semiconductor structure according to claim 11, It is characterized in that The overlay mark further includes a periodic grating structure arranged along a second direction, wherein the second direction is perpendicular to the first direction.

13. A memory, It is characterized in that A semiconductor structure comprising any one of claims 1 to 12.

14. A method for manufacturing a semiconductor structure, It is characterized in that include: Forming two photolithography layers and at least one blocking layer, each of the photolithography layers comprises a functional pattern and an overlay mark, the photolithography layers comprise a first photolithography layer and a second photolithography layer, the first photolithography layer comprises a first functional pattern and a first overlay mark, and the second photolithography layer comprises a second functional pattern and a second overlay mark; At least one blocking layer, the blocking layer is located between the first functional pattern and the second functional pattern, and in the stacking direction of the photolithography layer, the vertical distance between the first functional pattern and the second functional pattern is greater than the vertical spacing between the first overlay mark and the second overlay mark.

15. The method for manufacturing a semiconductor structure according to claim 14, It is characterized in that The semiconductor structure comprises a functional area and a cutting path, wherein the cutting path is located between adjacent functional areas; The process steps of forming the blocking layer and the second photolithography layer include: After forming the first photolithography layer, covering the cutting road and exposing the functional area; forming the blocking layer, wherein the blocking layer is located in the functional area and on the first functional pattern; The second photoresist layer is formed, and the second photoresist layer covers a top surface of the stop layer and a top surface of the cutting line of the first photoresist layer.

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