Wafer physical analysis area determination method, device and electronic equipment

Abstract

The embodiment of the application discloses a wafer physical analysis area determination method and device and electronic equipment, relates to the wafer test technical field, and is invented to improve the success rate of physical failure analysis. The wafer physical analysis area determination method comprises the following steps: dividing the wafer surface according to a specified size to obtain a plurality of areas; determining first-type defects and second-type defects in each area; calculating the failure severity of the first-type defects and the failure severity of the second-type defects in each area; the first-type defects are defects obtained by first-type testing of the wafer, and the second-type defects are defects obtained by second-type testing of the wafer; determining a target area on the wafer according to the failure severity of the first-type defects and the failure severity of the second-type defects; the target area is used for physical analysis of defects of the wafer. The application is suitable for testing and analyzing chips on the wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer testing, and in particular to a wafer physical analysis area determination method and device and electronic equipment. BACKGROUND

[0002] A wafer refers to a silicon wafer used for manufacturing silicon semiconductor integrated circuits, and various circuits and electronic component structures are processed and manufactured on the wafer to make the wafer into an integrated circuit product with specific electrical functions.

[0003] Integrated circuits can fail during research, production and use. Through wafer failure analysis, the causes of the failure can be found at an early stage of product development, which plays a very important role in improving product quality and reducing costs.

[0004] In the process of implementing the present application, the inventors have found that different electrical failure analysis methods are often used to analyze the failure of the wafer in the prior art, and the output results obtained by different electrical failure analysis methods are used independently, which is not conducive to improving the success rate of physical failure analysis. SUMMARY

[0005] Therefore, the embodiments of the present application provide a wafer physical analysis area determination method and device and electronic equipment, which are conducive to improving the success rate of physical failure analysis.

[0006] In a first aspect, the embodiments of the present application provide a wafer physical analysis area determination method, a wafer having circuits and electronic components manufactured thereon, the method comprising: dividing the surface of the wafer according to a specified size to obtain a plurality of regions; determining first-type defects and second-type defects in each region; calculating the failure severity of the first-type defects and the failure severity of the second-type defects in each region; the first-type defects are defects obtained by a first-type test on the wafer, and the second-type defects are defects obtained by a second-type test on the wafer; determining a target region on the wafer according to the failure severity of the first-type defects and the failure severity of the second-type defects; and the target region is used for physical analysis of defects on the wafer.

[0007] According to a specific implementation of the embodiments of the present application, the determination of the first-type defects and the second-type defects in each region comprises: matching the positions of each defect in the first-type defects and the second-type defects on the wafer with each region on the wafer to determine the first-type defects and the second-type defects in each region.

[0008] According to a specific implementation of the embodiment of the present application, the regions include a first region; wherein the calculating the failure severity of the first type of defects and the failure severity of the second type of defects in each region comprises: determining a failure severity coefficient of the first type of defects in the first region based on the proportion of the number of the first type of defects in the first region to the total number of the first type of defects in each region; and determining a failure severity coefficient of the second type of defects in the first region based on the proportion of the number of the second type of defects in the first region to the total number of the second type of defects in each region.

[0009] According to a specific implementation of the embodiment of the present application, the determining the target region on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects comprises: calculating a matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region; and determining a region whose matching degree exceeds a predetermined matching degree threshold as the target region; or, calculating a matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region; sorting regions according to the failure severity of the first type of defects or the failure severity of the second type of defects, and extracting a first predetermined number of regions at the top of the sorting as the target region.

[0010] According to a specific implementation of the embodiment of the present application, the calculating a matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region comprises: calculating a matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in each region according to the following formula: P = 1 - |S1-S2| / S1; wherein S1 is the failure severity coefficient of the first type of defects in the region; and S2 is the failure severity coefficient of the second type of defects in the region.

[0011] or,

[0012] calculating a matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in each region according to the following formula: P = M - |SL1-SL2|; wherein M is a failure severity coefficient level, M is a natural number greater than 1; SL1 is a failure severity level of the first type of defects in a region; and SL2 is a failure severity level of the second type of defects in the region.

[0013] According to a specific implementation of the embodiment of the present application, after determining the first type of defects and the second type of defects in each region, before determining the failure severity, the method further comprises: determining whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold; if the defect boundary density in the first boundary range is greater than the preset boundary density threshold, adjusting the region so that the defect boundary density in the first boundary range is less than or equal to the preset boundary density threshold.

[0014] According to a specific implementation of the embodiment of the present application, the determination of whether the defect boundary density in the first boundary range is greater than the preset boundary density threshold comprises: when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold; or,

[0015] when the number of failure points in the first boundary range is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold; or,

[0016] when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, and is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold.

[0017] According to a specific implementation of the embodiment of the present application, the adjustment of the region comprises: translating the region towards a specified direction; and / or, enlarging or reducing the region.

[0018] According to a specific implementation of the embodiment of the present application, after determining the target region on the wafer, the method further comprises: determining whether the defect boundary density of the target region is greater than a preset boundary density threshold; if the defect boundary density of the target region is greater than the preset boundary density threshold, adjusting the target region so that the defect boundary density of the target region is less than or equal to the preset boundary density threshold.

[0019] According to a specific implementation of the embodiment of the present application, the first type of test is a failure link scanning diagnosis analysis, and the second type of test is a memory cell failure bitmap analysis.

[0020] In a second aspect, an embodiment of the present application provides a wafer physical analysis area determination apparatus, wherein a circuit and an electronic component are fabricated on the wafer, and the apparatus comprises: an area division module configured to divide a wafer surface according to a specified size to obtain a plurality of areas; a mapping module configured to determine a first type of defect and a second type of defect in each area; a failure degree determination module configured to calculate a failure severity of the first type of defect and a failure severity of the second type of defect in each area; the first type of defect is a defect obtained by performing a first type of test on the wafer, and the second type of defect is a defect obtained by performing a second type of test on the wafer; and a target area determination module configured to determine a target area on the wafer according to the failure severity of the first type of defect and the failure severity of the second type of defect; the target area is used for physical analysis of defects on the wafer.

[0021] According to a specific implementation of an embodiment of the present application, the mapping module is specifically configured to: match the position of each defect in the first type of defect and the second type of defect on the wafer with the position of each area on the wafer to determine the first type of defect and the second type of defect in each area.

[0022] According to a specific implementation of an embodiment of the present application, the areas include a first area; and the failure degree determination module is specifically configured to: determine a failure severity coefficient of the first type of defect in the first area based on the proportion of the number of the first type of defect in the first area in the total number of the first type of defect in each area; and determine a failure severity coefficient of the second type of defect in the first area based on the proportion of the number of the second type of defect in the first area in the total number of the second type of defect in each area.

[0023] According to a specific implementation of an embodiment of the present application, the target area determination module is specifically configured to: calculate a matching degree of the failure severity of the first type of defect and the failure severity of the second type of defect in each area; and determine a region with a matching degree exceeding a predetermined matching degree threshold as a target area.

[0024] Alternatively, the target area determination module is specifically configured to: calculate a matching degree of the failure severity of the first type of defect and the failure severity of the second type of defect in each area; sort each area according to the failure severity of the first type of defect or the failure severity of the second type of defect to extract a first predetermined number of areas in the front of the sorting; and sort the first predetermined number of areas according to the matching degree to extract a second predetermined number of areas in the front of the sorting as target areas.

[0025] According to a specific implementation of the embodiment of the present application, the target region determining module is specifically configured to: calculate the matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in each region according to the following formula: P = 1 - |S1-S2| / S1; wherein S1 is the failure severity coefficient of the first type of defects in the region; and S2 is the failure severity coefficient of the second type of defects in the region.

[0026] Alternatively, the matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in each region is calculated according to the following formula: P = M - |SL1-SL2|; wherein M is a failure severity coefficient level, M is a natural number greater than 1; SL1 is the failure severity level of the first type of defects in a region; and SL2 is the failure severity level of the second type of defects in the region.

[0027] According to a specific implementation of the embodiment of the present application, the wafer physical analysis region determining apparatus further comprises a first adjusting module configured to: before determining the failure severity of the first type of defects and the second type of defects in each region, determine whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold; and if the defect boundary density in the first boundary range is greater than the preset boundary density threshold, adjust the region so that the defect boundary density in the first boundary range is less than or equal to the preset boundary density threshold.

[0028] According to a specific implementation of the embodiment of the present application, the first adjusting module specifically determines whether the defect boundary density in the first boundary range is greater than the preset boundary density threshold according to the following manner: when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold; or,

[0029] when the number of failure points in the first boundary range is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold; or,

[0030] when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, and is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold.

[0031] According to a specific implementation of the embodiment of the present application, the first adjusting module adjusts the region according to the following manner: translating the region towards a specified direction; and / or, enlarging or reducing the region.

[0032] According to a specific implementation of the embodiment of the present application, the wafer physical analysis region determining apparatus further comprises a second adjusting module, configured to determine whether the defect boundary density of the target region is greater than a preset boundary density threshold after determining the target region on the wafer.

[0033] If the defect boundary density of the target region is greater than the preset boundary density threshold, the target region is adjusted so that the defect boundary density of the target region is less than or equal to the preset boundary density threshold.

[0034] In a third aspect, the embodiment of the present application further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the housing, the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; the processor is configured to run programs corresponding to the executable program codes by reading the executable program codes stored in the memory, and execute the wafer physical analysis region determining method according to any of the foregoing implementation manners.

[0035] In a fourth aspect, the embodiment of the present application further provides a computer readable storage medium, which stores one or more programs executable by one or more processors to implement the wafer physical analysis region determining method according to any of the foregoing implementation manners.

[0036] The wafer physical analysis region determining method, apparatus and electronic device provided by the embodiment of the present application can obtain a plurality of regions by dividing the surface of the wafer according to a specified size; calculate the failure severity of the first type of defects and the failure severity of the second type of defects in each region, wherein the first type of defects are defects obtained by a first type of test, and the second type of defects are defects obtained by a second type of test; and then determine a target region on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects, i.e., by combining the output results obtained by different test methods to determine the target region for physical failure analysis, which is conducive to accurately determining the failure region on the wafer, thereby improving the success rate of physical failure analysis. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim to explain some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0038] Figure 1 Flow chart of the first embodiment of the wafer physical analysis area determination method of the present application;

[0039] Figure 2 Local schematic diagram obtained after the wafer surface is divided;

[0040] Figure 3 An exemplary defect distribution diagram is shown;

[0041] Figure 4a Flow chart of an embodiment of determining a target area on a wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects;

[0042] Figure 4b Flow chart of another embodiment of determining a target area on a wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects;

[0043] Figure 4c Flow chart of still another embodiment of determining a target area on a wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects;

[0044] Figure 5 Failure severity level division schematic diagram in an embodiment;

[0045] Figure 6 Flow chart of the second embodiment of the wafer physical analysis area determination method of the present application;

[0046] Figure 7a Schematic diagram in an embodiment in which failure points are concentrated in the boundary range;

[0047] Figure 7b Schematic diagram obtained after the regions shown are moved laterally; Figure 7a Schematic diagram obtained after the regions shown are enlarged;

[0048] Figure 7c Schematic diagram obtained after the regions shown are moved laterally; Figure 7a Schematic diagram obtained after the regions shown are enlarged;

[0049] Figure 8 Flow chart of the third embodiment of the wafer physical analysis area determination device of the present application;

[0050] Figure 9The first embodiment of the wafer physical analysis area determination device is shown in the schematic block diagram;

[0051] Figure 10 The second embodiment of the wafer physical analysis area determination device is shown in the schematic block diagram;

[0052] Figure 11 The third embodiment of the wafer physical analysis area determination device is shown in the schematic block diagram;

[0053] Figure 12 The structure schematic diagram of the electronic device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0054] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0055] When performing failure analysis on a wafer, potential failure is often found through electrical failure analysis first. After obtaining the coordinates of the failure point position through electrical failure analysis, the area where the failure point is located is checked and verified through physical failure analysis means. The electrical failure analysis is a means of analyzing potential defects or failure points in a circuit by using electricity and without damaging the circuit, and can provide positioning support. The physical failure analysis refers to a destructive failure analysis means, which mainly analyzes the wafer in terms of physics and materials. When checking and verifying the target area through physical failure analysis, the wafer can be ground by mechanical or chemical methods to obtain the relevant position plane or section picture, which is used for physical failure judgment.

[0056] SCAN diagnosis and BITMAP analysis are two important electrical failure analysis means. Through SCAN diagnosis, the position of potential failure points and the corresponding circuit layout can be obtained. Specifically, a large number of registers reserved in the design are used to form an effective link. By inputting different types of test patterns during testing, the potential link problems are analyzed by comparing the results, and the coordinates of the defect points in the wafer and other information are given. The object of BITMAP analysis is various high-density storage unit devices, which are tested by test algorithms and logic. According to the pass or failure, the storage unit array position is marked to form the corresponding BITMAP diagram.

[0057] SCAN diagnosis and BITMAP analysis are two important electrical failure analysis means, but the output results of SCAN diagnosis and the output results of BITMAP analysis are used independently, which is not conducive to improving the success rate of physical failure analysis.

[0058] Based on this, the embodiment of the present application provides a wafer physical analysis area determination method, device and electronic equipment, which combines the output results obtained by different electrical analysis means to determine the target area for physical failure analysis, is conducive to accurately determining the failure area on the wafer, thereby facilitating the improvement of the success rate of physical failure analysis.

[0059] Figure 1 The flow chart of the first embodiment of the wafer physical analysis area determination method of the present application. Referring to Figure 1 The wafer physical analysis area determination method of the embodiment includes steps S10-S16.

[0060] S10, divide the wafer surface according to a specified size to obtain a plurality of regions.

[0061] Before physical analysis of wafer defects, the target area for physical analysis of defects (or failure) needs to be determined. For this purpose, the wafer surface can be divided according to a specified size to obtain a plurality of regions, and then the plurality of regions are analyzed one by one to determine the target area for physical analysis of wafer defects.

[0062] The size of the divided region can be determined according to the specific needs. For example, the wafer surface can be divided according to several times the area of a single storage region collected by BITMAP analysis.

[0063] In one example, the wafer surface can be divided according to an area 2 times the single storage region collected by BITMAP analysis. In another example, the wafer surface can be divided according to an area 3 times the single storage region collected by BITMAP analysis.

[0064] Figure 2 A partial schematic view of the wafer surface after division. Figure 2 The divided regions shown in the figure are rectangular regions. In other embodiments, each region obtained after division can also be a square or other shaped region.

[0065] S12, determine the first type of defects and the second type of defects in each region.

[0066] There are many means for failure analysis of wafers, such as SCAN diagnostic analysis, BITMAP analysis, micro-light microscope EMMI, laser beam induced impedance value change test OBIRCH, etc. Different types of failure analysis means can obtain different types of defects.

[0067] The first type of defect refers to defects obtained from the wafer after undergoing the first type of test, and the second type of defect refers to defects obtained from the wafer after undergoing the second type of test. A first-type defect database can be pre-established for the wafer through the first type of test, and a second-type defect database can be established through the second type of test. Then, the first-type defect and the second-type defect can be obtained from the first-type defect database and the second-type defect database, respectively.

[0068] In one example, the first type of test is SCAN diagnostics, and the second type of test is BITMAP analysis. Correspondingly, the first type of defect is a netpath defect, and the second type of defect is a memory cell failure bitmap, i.e., a BITMAP. The first type of defect can be obtained from a database of suspected netpaths pre-obtained through SCAN diagnostics, and the second type of defect can be obtained from a database of failure bits pre-obtained through BITMAP analysis.

[0069] After dividing the wafer surface into multiple regions according to a specified size, the first and second types of defects obtained can be combined to determine the first and second types of defects in each region. In other words, each defect in the first and second types of defects can be mapped to the corresponding region.

[0070] Specifically, the positions (e.g., coordinates) of each defect in the first and second categories on the wafer can be matched with the positions of each region on the wafer to determine the first and second categories of defects in each region.

[0071] In some embodiments, the area corresponding to a defect can be determined by traversing and querying to determine whether the center coordinates of a defect fall within the area enclosed by the boundary of a region.

[0072] The following examples, using the netpath defect as the first type of defect and the Fail Bit defect as the second type, illustrate the regions corresponding to a defect. It should be understood that the defects corresponding to a region, in addition to the aforementioned first and / or second types of defects, may also correspond to (or include) other types of defects, such as third, fourth, and even fifth types of defects.

[0073] Extract the center point coordinates of a NetPath defect as (x1, y1). Then, iterate through the center point coordinates (x1, y1) of the NetPath defect and check them against the boundary coordinates of each region. Assume the coordinates of the lower left corner of the i-th region are (x1, y1). Li ,y Li The coordinates of the upper right corner are (x Ri ,y Ri If the condition is met: x Li <x1<x Ri , and yLi <y1 < y Ri Then, it can be determined that the ith region is the region corresponding to the netpath defect.

[0074] The center point coordinates of a fail bit defect are extracted as (x2, y2). The center point coordinates (x2, y2) of the fail bit defect are checked with the boundary coordinates of each region. Assuming that the coordinates of the lower left corner of the kth region are (x Lk , y Lk ) and the coordinates of the upper right corner are (x Rk , y Rk ), if the conditions x Lk < x2 < x Rk and y Lk < y2 < y Rk are satisfied, it can be determined that the kth region is the region corresponding to the fail bit defect.

[0075] It should be understood that the center point coordinates of the netpath defect and the center point coordinates of the fail bit defect are in the same coordinate system as the coordinates of the lower left corner and the upper right corner of each region.

[0076] As for the region corresponding to the fail bit defect, in addition to the above-mentioned traversal method, in some embodiments, the region corresponding to the fail bit defect can also be determined by querying the pre-collected test log of the automated test equipment (ATE log). In the test log, the coordinates of each fail bit defect and the corresponding region (for the sake of distinction, the region can be referred to as the in-log region) are usually recorded. Accordingly, the region corresponding to the fail bit defect in the log (i.e., the in-log region) can be obtained by querying the test log.

[0077] The size of the in-log region corresponding to the fail bit defect can be inconsistent with the size of the region obtained by dividing the wafer surface in step S10. The size of the in-log region corresponding to the fail bit defect can be smaller than the size of the region obtained by dividing the wafer surface in step S10. According to the coordinate position of the in-log region corresponding to the fail bit defect and the coordinate position of the region obtained by dividing the wafer surface in step S10, the region obtained by dividing the wafer surface in step S10 corresponding to the fail bit defect can be determined.

[0078] S14, calculating the failure severity of the first type of defect and the failure severity of the second type of defect in each region.

[0079] After determining the first type of defects and the second type of defects in each region, the failure severity of the first type of defects and the failure severity of the second type of defects in each region can be determined respectively based on the number of the first type of defects and the number of the second type of defects in each region.

[0080] In the embodiment, the regions include a first region. In some embodiments, the calculating the failure severity of the first type of defects and the failure severity of the second type of defects in each region can include: determining a failure severity coefficient of the first type of defects in the first region based on the proportion of the number of the first type of defects in the first region to the total number of the first type of defects in all regions. For example, there are n regions after division, the number of the first type of defects in the first region is P1, and the total number of the first type of defects in all regions is p1+p2+p3+…+pn. Then, the failure severity coefficient S1 of the first type of defects in the first region is

[0081] P1 / (p1+p2+p3+…+pn). The greater the failure severity coefficient is, the more serious the failure degree is.

[0082] Similarly, the failure severity coefficient of the second type of defects in the first region can be determined based on the proportion of the number of the second type of defects in the first region to the total number of the second type of defects in all regions. For example, the number of the second type of defects in the first region is N1, and the total number of the first type of defects in all regions is N1+N2+N3+…+Nn. Then, the failure severity coefficient S2 of the second type of defects in the first region is N1 / (N1+N2+N3+…+Nn).

[0083] If the second type of defects is fail bit defects, the failure severity coefficient of the second type of defects in each region can also be determined according to the number of each type of failing pattern in each region. Specifically, the failure severity coefficient of the second type of defects can be determined according to the proportion of the number of each type of failing pattern in the first region to the sum of the number of each type of failing pattern in all regions.

[0084] For example, there are n regions after division, the number of each type of failing pattern in the first region is C1, and the total number of each type of failing pattern in the n regions is C1+C2+C3+…+Cn. Then, the failure severity coefficient S2 of the second type of defects in the first region is C1 / (C1+C2+C3+…+Cn). The type of the failing pattern can include single bit fail, double bit fail, WL fail (word line direction failure), BL fail (bit line direction failure), Cluster Fail (cluster failure), etc.

[0085] Figure 3An exemplary defect distribution map is shown for illustration purposes only. Figure 3 The three regions B1, B2 and B3 shown are used to illustrate how to determine the failure severity coefficients of different types of defects in each region. In the example shown, Figure 3 The cross-shaped blocks in each region represent the first type of defects, and the rectangular blocks represent the second type of defects.

[0086] For region B1, the failure severity coefficient S1 of the first type of defects is 3 / (3+4+5) = 0.25, and the failure severity coefficient S2 of the second type of defects is 4 / (4+6+4) = 0.29. Similarly, the failure severity coefficients S1 and S2 of the first type of defects and the second type of defects in regions B2 and B3 can be calculated respectively.

[0087] In the above embodiment, the failure severity of a certain type of defects in a region (e.g., the first region) can be determined based on the proportion of the total number of the type of defects in the region. The present application is not limited thereto, and in some other embodiments, the failure severity of a certain type of defects in a region can also be determined based on whether the number of the type of defects in the region is greater than a predetermined defect quantity threshold. For example, if the predetermined defect quantity threshold is 5, and the actual number of a certain type of defects in a region is 7, then the failure severity of the type of defects in the region can be determined as severe.

[0088] S16, determining a target region on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects.

[0089] After determining the failure severity of the first type of defects and the failure severity of the second type of defects in each region, a target region for physical analysis of defects of the wafer can be determined according to the failure severity of the first type of defects and the failure severity of the second type of defects.

[0090] The wafer physical analysis region determination method provided by the embodiments of the present application divides the wafer surface according to a specified size to obtain a plurality of regions, calculates the failure severity of the first type of defects and the failure severity of the second type of defects in each region, wherein the first type of defects are defects obtained by a first type of test, and the second type of defects are defects obtained by a second type of test, and then determines a target region on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects, i.e., by combining the output results obtained by different test methods to determine a target region for physical failure analysis, which is conducive to accurately determining the failure region on the wafer, thereby improving the success rate of physical failure analysis.

[0091] Referring toFigure 4a In an embodiment, the target region is determined on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects (step S16), which can include:

[0092] S161a, calculating the matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region.

[0093] Generally speaking, the more consistent the failure severity of the first type of defects and the failure severity of the second type of defects in a region, the higher the matching degree of the two, and the more accurate the physical failure analysis will be when the region is determined as the target region.

[0094] In an example, the matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region can be calculated according to the following formula one:

[0095] P = 1 - |S1-S2| / S1; (Formula one)

[0096] Wherein, P is the matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in a region; S1 is the failure severity coefficient of the first type of defects in the region; S2 is the failure severity coefficient of the second type of defects in the region.

[0097] The calculation of S1 and S2 is the same as the calculation method of S1 and S2 in the foregoing embodiment, which will not be described here.

[0098] In formula one, S2 can also be used as the denominator to calculate P.

[0099] In another example, the matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region can be calculated according to the following formula two:

[0100] P = M - |SL1-SL2|; (Formula two)

[0101] Wherein, P is the matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in a region; M is the failure severity coefficient level, and M is a natural number greater than 1; SL1 is the failure severity level of the first type of defects in the region; SL2 is the failure severity level of the second type of defects in the region.

[0102] According to the size of M value, the failure severity coefficients of the first type of defects (including the maximum value and the minimum value) and the failure severity coefficients of the second type of defects (including the maximum value and the minimum value) in all regions can be divided into several levels respectively.

[0103] Reference Figure 5In one example, M is 10, the failure severity coefficients SL1 of the first type of defects (including the maximum value and the minimum value) and the failure severity coefficients SL2 of the second type of defects (including the maximum value and the minimum value) in all regions can be divided into 10 levels respectively.

[0104] In one region (e.g., the first region), if the failure severity coefficient SL1 of the first type of defects is in the 8th level, i.e., SL1 = 8, and the failure severity coefficient SL2 of the second type of defects is in the 7th level, i.e., SL2 = 7, then the matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in the region is P = 10 - |8 - 7| = 9.

[0105] The greater the matching degree result value is, the more consistent the failure severity of the first type of defects and the failure severity of the second type of defects in the same region are.

[0106] S162a, sorting each region according to the failure severity of the first type of defects, and extracting a first predetermined number of regions in the front of the sorting.

[0107] In the above example, each region can be sorted according to the failure severity coefficient of the first type of defects, and a first predetermined number of regions in the front of the sorting can be extracted. The first predetermined number can be a certain percentage or a specific value. In one example, 20% of the regions in the front of the sorting can be extracted. In another example, 8 regions in the front of the sorting can be extracted.

[0108] S163a, sorting the first predetermined number of regions according to the matching degree, and extracting a second predetermined number of regions in the front of the sorting as target regions.

[0109] After sorting each region according to the failure severity of the first type of defects and extracting a first predetermined number of regions in the front of the sorting, the first predetermined number of regions can be sorted according to the matching degree, and a second predetermined number of regions in the front of the sorting can be extracted as target regions.

[0110] In one example, after sorting each region according to the failure severity of the first type of defects and extracting 8 regions in the front of the sorting, the 8 regions can be sorted according to the matching degree, and 4 regions in the front of the sorting can be extracted as target regions.

[0111] Referring to Figure 4b In another embodiment, determining target regions on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects (step S16) can include:

[0112] S161b, calculating a matching degree of the first failure severity and the second failure severity in each region;

[0113] S162b, sorting the regions according to the second failure severity, and extracting a first predetermined number of regions with a high sorting result as target regions;

[0114] S163b, sorting the first predetermined number of regions according to the matching degree, and extracting a second predetermined number of regions with a high sorting result as target regions.

[0115] The embodiment is basically the same as the previous embodiment, except that in the previous embodiment, the regions are sorted according to the failure severity of the first type of defects first, and then sorted according to the matching degree; in the present embodiment, the regions are sorted according to the failure severity of the second type of defects first, and then sorted according to the matching degree.

[0116] Referring to Figure 4c In yet another embodiment, the target regions can also be determined directly according to the failure severity of the first type of defects and the failure severity of the second type of defects. Specifically, determining the target regions on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects (step S16) can include:

[0117] S161c, calculating a matching degree of the first failure severity and the second failure severity in each region;

[0118] S162c, determining a region with a matching degree exceeding a predetermined matching degree threshold as a target region.

[0119] In one example, if the predetermined matching degree threshold is 0.7, and the matching degree in a region is calculated to be 0.8 according to the above Formula One, the region can be determined as a target region.

[0120] In another example, if the predetermined matching degree threshold is 6, and the matching degree in a region is calculated to be 9 according to the above Formula Two, the region can be determined as a target region.

[0121] Figure 6 A flowchart of a second embodiment of the wafer physical analysis region determination method of the present application. Referring to Figure 6 The wafer physical analysis region determination method of the present embodiment is basically the same as the wafer physical analysis region determination method of the first embodiment of the present application, except that Figure 1The wafer physical analysis region determination method is basically the same, the difference is that, in the embodiment, after determining the first type of defects and the second type of defects in each region (step S12), before determining the failure severity of each type of defects (step S14), the method further comprises steps S13a-S13b.

[0122] S13a, judge whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold.

[0123] In order to avoid the failure points located in the boundary range of the region after the region division, affecting the analysis quality of the failure points and the circuit part, it is necessary to avoid the failure points from being too concentrated in the boundary range. If the failure points are too concentrated in the boundary range, the divided region needs to be adjusted.

[0124] The concentration degree of the failure points in the boundary range can be referred to as the defect boundary density. Whether the divided region needs to be adjusted can be determined by judging whether the defect boundary density is greater than a preset boundary density threshold.

[0125] In some embodiments, the boundary range can be a specified width (such as 1 / 4 of the region width) range on both sides of the boundary line of the adjacent two regions. For example, the first boundary range is a specified width range on both sides of the boundary of the first region and the second region. The specified width on both sides of the boundary line can be 1 / 4 of the region width, as shown in Figure 7a , the range of width D shown in the figure is the boundary range.

[0126] In one example, judging whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold (step S13a) comprises: when the number of failure points in the first boundary range exceeds a preset percentage (such as 30%) of the number of failure points in the first region or the second region on both sides of the boundary, it can be determined that the divided region needs to be adjusted. Preferably, when the number of failure points in the first boundary range exceeds a preset percentage (such as 30%) of the number of failure points in the region with more failure points on both sides of the boundary, it can be determined that the divided region needs to be adjusted.

[0127] In another example, judging whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold (step S13a) comprises: when the number of failure points in the first boundary range is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold. The average number of failure points in each region = the total number of failure points in each region / the sum of the number of regions.

[0128] In another example, determining whether the defect boundary density in the first boundary range is greater than the preset boundary density threshold (step S13a) includes: when the number of failure points in the first boundary range exceeds a preset percentage (e.g., 30%) of the number of failure points in the first region or the second region on both sides of the boundary, and is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold.

[0129] In other embodiments, the boundary range can also be a region defined by a specified width (e.g., 1 / 4 of the width of the region) near the side of the boundary line in a single region.

[0130] In one example, when the number of failure points in the boundary range in a region exceeds a preset percentage (e.g., 30%) of the number of failure points in the region, it can be determined that the divided region needs to be adjusted.

[0131] In another example, when the number of failure points in the boundary range in a region is greater than the average number of failure points in each region, it can be determined that the divided region needs to be adjusted.

[0132] Through the above determination, if the defect boundary density in the first boundary range is greater than the preset boundary density threshold, step S13b is performed.

[0133] S13b, adjusting the region so that the defect boundary density in the first boundary range is less than or equal to the preset boundary density threshold.

[0134] The adjustment of the region can include the following two ways:

[0135] (1) translating the region in a specified direction

[0136] At least one region can be translated in a specified direction by a predetermined step size (e.g., 10% of the width). Figure 7b For example, the regions shown in FIG. 1 can be moved horizontally to obtain the schematic diagram shown in FIG. 2. Figure 7a

[0137] (2) enlarging or reducing the region

[0138] At least one region can be enlarged or reduced by a predetermined percentage (e.g., 5% of the size of the region). Figure 7c For example, the regions shown in FIG. 1 can be enlarged to obtain the schematic diagram shown in FIG. 3. Figure 7a

[0139] The above two adjustment methods can be used alone or in combination.

[0140] ​​After each adjustment, a defect boundary density check is performed again, that is, the defect boundary density within the first boundary range is re-evaluated to see if it is greater than the preset boundary density threshold. If it is still greater than the preset boundary density threshold, the adjustment continues until the defect boundary density check passes.

[0141] The number of translations can be set to an upper limit, such as 5, 10, or 15 times.

[0142] The number of times the scale can be enlarged or reduced can also be set to an upper limit, for example, the upper limit of the number of times the scale can be set to a predetermined percentage of the wafer area after the single area is enlarged.

[0143] Figure 8 This is a flowchart illustrating a third embodiment of the wafer physical analysis region determination apparatus of the present invention. See also... Figure 8 The wafer physical analysis region determination device of this embodiment and Figure 1 The wafer physical analysis region determination device is basically the same as described above. The difference is that, in this embodiment, after determining the target region on the wafer (step S16), the method further includes steps S18-S20.

[0144] S18. Determine whether the defect boundary density of the target area is greater than the preset boundary density threshold.

[0145] To avoid failure points located at the boundaries of a defined target area, which could affect the analysis quality of the failure points and circuit components, it is possible to determine whether the defect boundary density of the target area exceeds a preset boundary density threshold. If the defect boundary density of the target area exceeds the preset boundary density threshold, step S20 can be executed.

[0146] S20. Adjust the target area so that the defect boundary density of the target area is less than or equal to a preset boundary density threshold.

[0147] In this embodiment, the determination of the defect boundary density in the target area and the method of adjusting the target area are similar to... Figure 6 The methods for determining the defect boundary density and adjusting the region in the embodiments shown are basically the same, and will not be repeated here.

[0148] In this embodiment, after determining the target area for physical failure analysis, it is then determined whether the defect boundary density of the target area is greater than a preset boundary density threshold. If it is greater, the target area is adjusted. This makes the adjusted area more targeted and improves the efficiency and success rate of material failure analysis.

[0149] Figure 9 This is a schematic block diagram of a first embodiment of the wafer physical analysis region determination device of the present invention. Circuits and electronic components are fabricated on the wafer, see below. Figure 9The wafer physical analysis area determination device 90 comprises an area division module 91, a mapping module 92, a failure degree determination module 93, and a target area determination module 94. The area division module 91 is configured to divide a wafer surface according to a specified size to obtain a plurality of areas. The mapping module 92 is configured to determine first-type defects and second-type defects in each area. The failure degree determination module 93 is configured to calculate failure severity of the first-type defects and failure severity of the second-type defects in each area. The first-type defects are defects obtained by performing a first-type test on the wafer, and the second-type defects are defects obtained by performing a second-type test on the wafer. The target area determination module 94 is configured to determine a target area on the wafer according to the failure severity of the first-type defects and the failure severity of the second-type defects. The target area is used for physical analysis of defects of the wafer.

[0150] The wafer physical analysis area determination device of the embodiment can be used to perform the wafer physical analysis area determination method shown in the embodiment, and has basically the same functions and technical effects, which will not be described herein again. Figure 1 The wafer physical analysis area determination method shown in the embodiment has basically the same functions and technical effects as the wafer physical analysis area determination device, which will not be described herein again.

[0151] In an embodiment, the mapping module 92 is specifically configured to match positions of each of the first-type defects and the second-type defects on the wafer with each of the areas on the wafer to determine the first-type defects and the second-type defects in each area. The determination of the first-type defects and the second-type defects in each area can refer to the related description in the foregoing method embodiments, which will not be described herein again.

[0152] In an embodiment, the areas comprise a first area. The failure degree determination module 93 is specifically configured to determine a failure severity coefficient of the first-type defects in the first area based on a proportion of a number of the first-type defects in the first area in a total number of the first-type defects in each area, and determine a failure severity coefficient of the second-type defects in the first area based on a proportion of a number of the second-type defects in the first area in a total number of the second-type defects in each area. The determination of the failure severity coefficient of the first-type defects and the failure severity coefficient of the second-type defects can refer to the related description in the foregoing method embodiments, which will not be described herein again.

[0153] In one embodiment, the target region determination module 94 is specifically configured to: calculate the matching degree between the failure severity of the first type of defect and the failure severity of the second type of defect in each region; determine the region whose matching degree exceeds a predetermined matching degree threshold as the target region; or, calculate the matching degree between the failure severity of the first type of defect and the failure severity of the second type of defect in each region; sort each region according to the failure severity of the first type of defect or the failure severity of the second type of defect, and extract a first predetermined number of regions that rank highly; sort the first predetermined number of regions according to the matching degree, and extract a second predetermined number of regions that rank highly as the target region.

[0154] In one embodiment, the target area determination module 94 can be specifically used to: calculate the matching degree P of the failure severity of the first type of defect and the failure severity of the second type of defect in each area according to the following formula: P = 1 - |S1 – S2| / S1; where S1 is the failure severity coefficient of the first type of defect in the area; and S2 is the failure severity coefficient of the second type of defect in the area.

[0155] In another embodiment, the target area determination module 94 can be specifically used to: calculate the matching degree P of the failure severity of the first type of defect and the failure severity of the second type of defect in each area according to the following formula: P = M - |SL1 – SL2|; where M is the failure severity coefficient level, M is a natural number greater than 1; SL1 is the failure severity level of the first type of defect in a region; SL2 is the failure severity level of the second type of defect in the region.

[0156] The specific method for determining the target area based on the matching degree of the failure severity of the first type of defect and the failure severity of the second type of defect in each area can be found in the relevant description in the aforementioned method implementation, and will not be repeated here.

[0157] Figure 10 This is a schematic block diagram of a second embodiment of the wafer physical analysis region determination device of the present invention. (See attached diagram) Figure 10 This implementation method is the same as Figure 9 The implementation methods shown are basically the same, except that this implementation method also includes a first adjustment module 95, which is used to: determine whether the defect boundary density within the first boundary range is greater than a preset boundary density threshold after determining the first type of defect and the second type of defect in each region and before determining the severity of the failure; if the defect boundary density within the first boundary range is greater than the preset boundary density threshold, then the region is adjusted so that the defect boundary density within the first boundary range is less than or equal to the preset boundary density threshold.

[0158] The wafer physical analysis region determination device of the embodiment can be used to execute Figure 6 The wafer physical analysis region determination method shown in the embodiment has basically the same functions and technical effects as the wafer physical analysis region determination device, and thus will not be described here.

[0159] In an embodiment, the first adjusting module specifically determines whether the defect boundary density in the first boundary range is greater than the preset boundary density threshold value according to the following manner: when the number of failure points in the first boundary range exceeds the preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, it is determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold value; or,

[0160] when the number of failure points in the first boundary range is greater than the average number of failure points in each region, it is determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold value; or,

[0161] when the number of failure points in the first boundary range exceeds the preset percentage of the number of failure points in the first region or the second region on both sides of the boundary and is greater than the average number of failure points in each region, it is determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold value.

[0162] The detailed process of determining the defect boundary density and determining whether it is greater than the preset boundary density threshold value can be referred to the related description in the foregoing method embodiments, and thus will not be described here.

[0163] In an embodiment, the first adjusting module specifically adjusts the region according to the following manner: translating the region in a specified direction; and / or enlarging or reducing the region. The specific process of adjusting the region according to the above manner can be referred to the related description in the foregoing method embodiments, and thus will not be described here.

[0164] Figure 11 The third embodiment of the wafer physical analysis region determination device of the present application is shown in the schematic block diagram, which can be referred to Figure 11 The third embodiment of the wafer physical analysis region determination device of the present application is shown in the schematic block diagram, which can be referred to Figure 9 The third embodiment of the wafer physical analysis region determination device of the present application is shown in the schematic block diagram, which can be referred to Figure 8The wafer physical analysis area determination method shown has basically the same functions and technical effects as the implementation, and thus will not be described here.

[0165] Figure 12 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 1, which can include a housing 61, a processor 62, a memory 63, a circuit board 64, and a power supply circuit 65. The circuit board 64 is disposed inside a space enclosed by the housing 61, and the processor 62 and the memory 63 are disposed on the circuit board 64. The power supply circuit 65 is configured to supply power to each circuit or device of the electronic device. The memory 63 is configured to store executable program codes. The processor 62 is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory 63, and is configured to execute any wafer physical analysis area determination method provided by the foregoing embodiments, and thus can also achieve the corresponding beneficial technical effects, which have been described in detail above and thus will not be described here. Figure 12 The electronic device can exist in various forms, including but not limited to desktop computers, servers, and the like. The server is a device configured to provide computing services. The server is similar in architecture to a general-purpose computer, but has higher requirements in terms of processing capability, stability, reliability, security, scalability, and manageability, because it needs to provide high-reliability services.

[0166] The present application also provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any wafer physical analysis area determination method provided by the foregoing embodiments, and thus can also achieve the corresponding technical effects, which have been described in detail above and thus will not be described here.

[0167] The wafer physical analysis area determination method, device, and electronic device provided by the embodiments of the present application can obtain a plurality of regions by dividing the wafer surface according to a specified size, calculate the failure severity of the first type of defects and the failure severity of the second type of defects in each region, the first type of defects being defects obtained by a first type of test on the wafer, and the second type of defects being defects obtained by a second type of test on the wafer, and then determine a target region on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects, that is, by combining the output results obtained by different test methods to determine the target region for physical failure analysis, which is conducive to accurately determining the failure region on the wafer, and thus is conducive to improving the success rate of physical failure analysis.

[0168]

[0169] ​It is to be noted that, in the present document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0170] Each of the above-described embodiments is described in a related manner, and the same or similar parts among the embodiments can be referred to each other. Each of the embodiments focuses on a difference from other embodiments.

[0171] In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0172] For the convenience of description, the above device is described in various units / modules respectively according to functions. Of course, in the implementation of the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0173] Those skilled in the art can understand that all or part of the processes in the above-described embodiments can be completed by a computer program instructing related hardware. The program can be stored in a computer readable storage medium, and when executed, can include the processes of the above-described embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0174] The above description is merely specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily conceived by those skilled in the art, and should be covered by the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

Claims

1. A method for determining a physical analysis area of a wafer on which circuits and electronic components are fabricated, comprising the steps of: The method comprises: ​ dividing a wafer surface according to a specified size to obtain a plurality of regions; determining first-type defects and second-type defects in each region; calculating failure severity of the first-type defects and failure severity of the second-type defects in each region; the first-type defects are defects obtained by testing the wafer in a first type, and the second-type defects are defects obtained by testing the wafer in a second type; determining a target region on the wafer according to the failure severity of the first-type defects and the failure severity of the second-type defects; the target region is used for physical analysis of defects of the wafer; wherein the determining of the target region on the wafer according to the failure severity of the first-type defects and the failure severity of the second-type defects comprises: calculating a matching degree of the failure severity of the first-type defects and the failure severity of the second-type defects in each region; and determining a region with a matching degree exceeding a predetermined matching degree threshold as the target region; or, calculating a matching degree of the failure severity of the first-type defects and the failure severity of the second-type defects in each region; sorting regions according to the failure severity of the first-type defects or the failure severity of the second-type defects to extract a first predetermined number of regions in the front of the sorting as the target region. sorting the first predetermined number of regions according to the matching degree to extract a second predetermined number of regions in the front of the sorting as the target region.

2. The wafer physical analysis area determination method of claim 1, wherein The determining of the first-type defects and the second-type defects in each region comprises: positionally matching positions of each defect in the first-type defects and the second-type defects on the wafer with each region on the wafer to determine the first-type defects and the second-type defects in each region.

3. The wafer physical analysis area determination method of claim 1, wherein The regions comprise a first region; wherein the calculating of the failure severity of the first-type defects and the failure severity of the second-type defects in each region comprises: determining a failure severity coefficient of the first-type defects in the first region based on a proportion of a number of the first-type defects in the first region in a total number of the first-type defects in each region; determining a failure severity coefficient of the second-type defects in the first region based on a proportion of a number of the second-type defects in the first region in a total number of the second-type defects in each region.

4. The wafer physical analysis area determination method of claim 1, wherein, The calculating of the matching degree of the failure severity of the first-type defects and the failure severity of the second-type defects in each region comprises: calculating the matching degree P of the failure severity of the first-type defects and the failure severity of the second-type defects in each region according to the following formula: P = 1 - |S1 - S2| / S1; wherein S1 is the failure severity coefficient of the first-type defects in the region; and S2 is the failure severity coefficient of the second-type defects in the region; or, calculating the matching degree P of the failure severity of the first-type defects and the failure severity of the second-type defects in each region according to the following formula: P = M - |SL1 - SL2|; wherein M is a matching degree of the failure severity of the first-type defects and the failure severity of the second-type defects in each region; SL1 is the failure severity coefficient of the first-type defects in the region; and SL2 is the failure severity coefficient of the second-type defects in the region. Wherein, M is a failure severity coefficient level, M is a natural number greater than 1; SL1 is a failure severity level of the first type of defects in a region; SL2 is a failure severity level of the second type of defects in the region.

5. The wafer physical analysis area determination method of claim 1, wherein, After determining the first type of defects and the second type of defects in each region, the method further comprises: determining whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold value; if the defect boundary density in the first boundary range is greater than the preset boundary density threshold value, adjusting the region so that the defect boundary density in the first boundary range is less than or equal to the preset boundary density threshold value.

6. The wafer physical analysis area determination method of claim 5, wherein, The determination of whether the defect boundary density in the first boundary range is greater than the preset boundary density threshold value comprises: when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold value; or, when the number of failure points in the first boundary range is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold value; or, when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, and is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold value.

7. The wafer physical analysis area determination method of claim 5, wherein, The adjustment of the region comprises: translating the region towards a specified direction; and / or, enlarging or reducing the region.

8. The wafer physical analysis area determination method of claim 1, wherein, After determining the target region on the wafer, the method further comprises: determining whether the defect boundary density of the target region is greater than a preset boundary density threshold value; if the defect boundary density of the target region is greater than the preset boundary density threshold value, adjusting the target region so that the defect boundary density of the target region is less than or equal to the preset boundary density threshold value.

9. The wafer physical analysis area determination method of claim 1, wherein, The first type of test is a failure link scanning diagnosis analysis, and the second type of test is a storage unit failure bitmap analysis.

10. A wafer physical analysis area determination apparatus, on which a circuit and an electronic component are fabricated, characterized by comprising: a wafer physical analysis area determination program for determining a wafer physical analysis area on the wafer. The device comprises a region division module, a mapping module, a failure degree determination module and a target region determination module; wherein, the region division module is used to divide the wafer surface according to a specified size to obtain a plurality of regions; the mapping module is used to determine the first type of defects and the second type of defects in each region; the failure degree determination module is used to calculate the failure severity of the first type of defects and the failure severity of the second type of defects in each region; the first type of defects are defects obtained by the first type of test on the wafer, and the second type of defects are defects obtained by the second type of test on the wafer; the target region determination module is used to determine a target region on the wafer according to the failure severity of the first type of defects and the failure severity of the second type of defects; the target region is used for physical analysis of defects on the wafer; wherein the target region determination module is specifically used for: The matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region is calculated; and the region whose matching degree exceeds a predetermined matching degree threshold is determined as the target region. Alternatively, The matching degree of the failure severity of the first type of defects and the failure severity of the second type of defects in each region is calculated; the regions are sorted according to the failure severity of the first type of defects or the failure severity of the second type of defects, and the first predetermined number of regions at the top of the sorting are extracted; and the first predetermined number of regions are sorted according to the matching degree, and the second predetermined number of regions at the top of the sorting are extracted as the target region.

11. The wafer physical analysis area determination apparatus according to claim 10, wherein The mapping module is specifically configured to: match the positions of each defect in the first type of defects and the second type of defects on the wafer with each region on the wafer to determine the first type of defects and the second type of defects in each region.

12. The wafer physical analysis area determination apparatus according to claim 10, wherein The regions include a first region; and the failure degree determination module is specifically configured to: determine a failure severity coefficient of the first type of defects in the first region based on the proportion of the number of the first type of defects in the first region in the total number of the first type of defects in each region; determine a failure severity coefficient of the second type of defects in the first region based on the proportion of the number of the second type of defects in the first region in the total number of the second type of defects in each region.

13. The wafer physical analysis area determination apparatus according to claim 10, wherein The target region determination module is specifically configured to: calculate the matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in each region according to the following formula: P = 1 - |S1 - S2| / S1; wherein S1 is the failure severity coefficient of the first type of defects in the region; and S2 is the failure severity coefficient of the second type of defects in the region. Alternatively, calculate the matching degree P of the failure severity of the first type of defects and the failure severity of the second type of defects in each region according to the following formula: P = M - |SL1 - SL2|; wherein M is a failure severity coefficient level, M is a natural number greater than 1; SL1 is the failure severity level of the first type of defects in a region; and SL2 is the failure severity level of the second type of defects in the region.

14. The wafer physical analysis area determination apparatus according to claim 10, wherein Further comprising a first adjustment module configured to: determine whether the defect boundary density in the first boundary range is greater than a preset boundary density threshold before determining the first type of defects and the second type of defects in each region and determining the failure severity; if the defect boundary density in the first boundary range is greater than the preset boundary density threshold, adjust the region so that the defect boundary density in the first boundary range is less than or equal to the preset boundary density threshold.

15. The wafer physical analysis area determination apparatus according to claim 14, wherein The first adjustment module specifically determines whether the defect boundary density in the first boundary range is greater than the preset boundary density threshold according to the following manner: when the number of failure points in the first boundary range exceeds a preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold; or When the number of failure points in the first boundary range is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold; or When the number of failure points in the first boundary range exceeds the preset percentage of the number of failure points in the first region or the second region on both sides of the boundary, and is greater than the average number of failure points in each region, it can be determined that the defect boundary density in the first boundary range is greater than the preset boundary density threshold.

16. The wafer physical analysis area determination apparatus according to claim 14, wherein The first adjusting module specifically adjusts the region in the following manner: Translate the region towards a specified direction; and / or, Enlarge or reduce the region.

17. The wafer physical analysis area determination apparatus of claim 10, wherein Further comprising a second adjusting module for determining whether the defect boundary density of the target region is greater than the preset boundary density threshold after determining the target region on the wafer; If the defect boundary density of the target region is greater than the preset boundary density threshold, the target region is adjusted so that the defect boundary density of the target region is less than or equal to the preset boundary density threshold.

18. An electronic device, comprising: The electronic device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged inside the space surrounded by the shell, the processor and the memory are arranged on the circuit board; the power circuit is used to power each circuit or device of the electronic device; the memory is used to store executable program codes; the processor runs the program corresponding to the executable program codes by reading the executable program codes stored in the memory, and is used to execute the wafer physical analysis region determination method of any one of the preceding claims 1-9.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium stores one or more programs, which can be executed by one or more processors to implement the wafer physical analysis region determination method of any one of the preceding claims 1-9.

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