Gate driving circuit and display panel

Abstract

Embodiments of the present application provide a gate drive circuit and a display panel; the gate drive circuit is provided with a second anti-leakage unit in at least one gate drive unit, and the second anti-leakage unit is connected with at least one of a pull-down unit, a first pull-down maintenance unit and a global reset unit, so that when the threshold voltage of a transistor in the pull-down unit, the first pull-down maintenance unit and the global reset unit is negatively biased, the second anti-leakage unit can close at least one transistor in the pull-down unit, the first pull-down maintenance unit and the global reset unit when the first node is at a high potential, so that the closed transistor cannot leak, thereby reducing the leakage current of the first node, and the display panel can display normally.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] With the development of display technology, the existing display device has higher requirements for narrow frame, therefore, the existing display device will adopt GOA (Gate Driver On Array, array substrate row driving technology) technology to replace the gate driving chip to reduce the frame. However, in the working process of the gate driving circuit, due to the influence of the process, the threshold voltage of the transistor will be offset, specifically, the threshold voltage of the transistor in the gate driving circuit will be negatively biased, resulting in Q point leakage in the gate driving circuit, and further resulting in that the gate driving circuit cannot normally output the switching signal and the level transmission signal of the pixel, and the display panel cannot normally display.

[0003] Therefore, the existing gate driving circuit has the technical problem that the negative bias of the threshold voltage of the transistor causes the display panel to be unable to normally display. SUMMARY

[0004] Embodiments of the present application provide a gate driving circuit and a display panel to alleviate the technical problem that the existing gate driving circuit has the negative bias of the threshold voltage of the transistor causing the display panel to be unable to normally display.

[0005] Embodiments of the present application provide a gate driving circuit, which includes a plurality of gate driving units connected in cascade, and the gate driving unit includes:

[0006] a pull-up control unit connected with the first node, configured to pull up the potential of the first node;

[0007] a pull-up unit connected with the first node, configured to pull up the potential of the first level transmission signal end and the output signal end;

[0008] a pull-down unit connected with the first node, configured to pull down the potential of the first node;

[0009] a first pull-down maintaining unit connected with the first node, configured to maintain the low potential of the first node;

[0010] a first anti-leakage unit connected with the first node, an output end of the first anti-leakage unit being connected with the pull-down unit and the first pull-down maintaining unit, configured to prevent the pull-down unit and the first pull-down maintaining unit from leaking;

[0011] a global reset unit connected with the first node, configured to pull down the potential of the first node;

[0012] an inverter connected to the second node for inverting the potential of the first node and the second node;

[0013] The at least one gate driving unit further comprises a second anti-leakage unit connected to at least one of the pull-down unit, the first pull-down maintaining unit and the global reset unit, the second anti-leakage unit being configured to turn off at least one transistor of the pull-down unit, the first pull-down maintaining unit and the global reset unit when the potential of the first node is at a high potential.

[0014] In some embodiments, the second anti-leakage unit comprises a second level signal terminal and an anti-leakage transistor, a gate of the anti-leakage transistor being connected to the second level signal terminal, a first electrode of the anti-leakage transistor being connected to the first low potential signal terminal, and a second electrode of the anti-leakage transistor being connected to a second gate of at least one transistor of the pull-down unit, the first pull-down maintaining unit and the global reset unit.

[0015] In some embodiments, the second electrode of the anti-leakage transistor is connected to the second gate of at least one transistor of the pull-down unit.

[0016] In some embodiments, the pull-down unit comprises a first transistor, a second transistor and a third level signal terminal, a first gate of the first transistor and a first gate of the second transistor being connected to the third level signal terminal, a first electrode of the first transistor being connected to the first node, a second electrode of the first transistor and a second electrode of the second transistor being connected to an output terminal of the first anti-leakage unit, a first electrode of the second transistor being connected to the first low potential signal terminal, and the second electrode of the anti-leakage transistor being connected to a second gate of at least one of the first transistor and the second transistor.

[0017] In some embodiments, the second electrode of the anti-leakage transistor is connected to the second gate of at least one transistor of the first pull-down maintaining unit.

[0018] In some embodiments, the first pull-down maintaining unit comprises a third transistor and a fourth transistor, a first gate of the third transistor and a first gate of the fourth transistor being connected to the second node, a first electrode of the third transistor being connected to the first node, a second electrode of the third transistor and a first electrode of the fourth transistor being connected to the output terminal of the first anti-leakage unit, a second electrode of the fourth transistor being connected to the first low potential signal terminal, and the second electrode of the anti-leakage transistor being connected to a second gate of at least one of the third transistor and the fourth transistor.

[0019] In some embodiments, the first pull-down maintaining unit further comprises a fifth transistor and a sixth transistor, a first gate of the fifth transistor and a first gate of the sixth transistor are connected with the third node, a first electrode of the fifth transistor is connected with the first node, a second electrode of the fifth transistor and a first electrode of the sixth transistor are connected with an output terminal of the first leakage prevention unit, a second electrode of the sixth transistor is connected with the first low potential signal terminal, and a second electrode of the leakage prevention transistor is connected to a second gate of at least one of the fifth transistor and the sixth transistor.

[0020] In some embodiments, a second electrode of the leakage prevention transistor is connected with a second gate of at least one transistor in the global reset unit.

[0021] In some embodiments, the global reset unit comprises a seventh transistor, an eighth transistor and a global reset signal terminal, a first gate of the seventh transistor and a first gate of the eighth transistor are connected with the global reset signal terminal, a first electrode of the seventh transistor is connected with the first node, a second electrode of the seventh transistor and a first electrode of the eighth transistor are connected with the output terminal of the first leakage prevention unit, a second electrode of the eighth transistor is connected with the output signal terminal, and a second electrode of the leakage prevention transistor is connected to a second gate of at least one of the seventh transistor and the eighth transistor.

[0022] In some embodiments, a second electrode of the leakage prevention transistor is connected with a second gate of at least one transistor in the pull-down unit, a second electrode of the leakage prevention transistor is connected with a second gate of at least one transistor in the first pull-down maintaining unit, and a second electrode of the leakage prevention transistor is connected with a second gate of at least one transistor in the global reset unit.

[0023] In some embodiments, the leakage prevention transistor comprises a first leakage prevention transistor, a second leakage prevention transistor and a third leakage prevention transistor, a gate of the first leakage prevention transistor, a gate of the second leakage prevention transistor and a gate of the third leakage prevention transistor are connected with the second stage signal terminal, a first electrode of the first leakage prevention transistor, a first electrode of the second leakage prevention transistor and a first electrode of the third leakage prevention transistor are connected with the first low potential signal terminal, a second electrode of the first leakage prevention transistor is connected with a second gate of at least one transistor in the pull-down unit, a second electrode of the second leakage prevention transistor is connected with a second gate of at least one transistor in the first pull-down maintaining unit, and a second electrode of the third leakage prevention transistor is connected with a second gate of at least one transistor in the global reset unit.

[0024] Meanwhile, this application provides a display panel that includes a gate driving circuit as described in any of the above embodiments.

[0025] Beneficial Effects: This application provides a gate driving circuit and a display panel. The gate driving circuit includes multiple cascaded gate driving units. Each gate driving unit includes a pull-up control unit, a pull-up unit, a pull-down unit, a first pull-down sustaining unit, a first leakage protection unit, a global reset unit, and an inverter. The pull-up control unit is connected to a first node and is used to pull up the potential of the first node. The pull-up unit is connected to the first node and is used to pull up the potential of the first stage signal transmission terminal and output signal terminal. The pull-down unit is connected to the first node and is used to pull down the potential of the first node. The first pull-down sustaining unit is connected to the first node and is used to maintain the low potential of the first node. The first leakage protection unit is connected to... The first node is connected, the output of the first leakage protection unit is connected to the pull-down unit and the first pull-down sustaining unit to prevent leakage from the pull-down unit and the first pull-down sustaining unit, the global reset unit is connected to the first node to pull the potential of the first node low, and the inverter is connected to the second node to reverse the potential of the first node and the second node. At least one gate drive unit further includes a second leakage protection unit, which is connected to at least one of the pull-down unit, the first pull-down sustaining unit and the global reset unit. The second leakage protection unit is used to turn off at least one transistor of the pull-down unit, the first pull-down sustaining unit and the global reset unit when the potential of the first node is high. This application adds a second leakage protection unit to at least one gate driving unit, and connects the second leakage protection unit to at least one of the pull-down unit, the first pull-down sustaining unit, and the global reset unit. When the threshold voltage of the transistors in the pull-down unit, the first pull-down sustaining unit, and the global reset unit is negatively biased, the second leakage protection unit can turn off at least one of the transistors in the pull-down unit, the first pull-down sustaining unit, and the global reset unit when the first node is at a high potential. This prevents the turned-off transistor from leaking current, thereby reducing the leakage current of the first node and enabling the display panel to display normally. Attached Figure Description

[0026] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0027] Figure 1 This is a first circuit diagram of a gate drive circuit provided in an embodiment of this application.

[0028] Figure 2 for Figure 1 Timing diagram of the gate drive circuit.

[0029] Figure 3 This is a second circuit diagram of the gate drive circuit provided in an embodiment of this application.

[0030] Figure 4 A third circuit diagram of a gate drive circuit is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0032] The embodiments of the present application provide a gate drive circuit and a display panel, to alleviate the technical problem that the threshold voltage of a transistor is negatively biased in the existing gate drive circuit, resulting in that the display panel cannot be normally displayed.

[0033] As shown in Figure 1 , Figure 2 The embodiments of the present application provide a gate drive circuit, which includes a plurality of gate drive units 10 connected in cascade, and the gate drive unit 10 includes:

[0034] A pull-up control unit 11 is connected with a first node Q[n], and is configured to pull up the potential of the first node Q[n];

[0035] A pull-up unit 12 is connected with the first node Q[n], and is configured to pull up the potential of a first stage transmission signal end Cout[n] and an output signal end WR[n];

[0036] A pull-down unit 13 is connected with the first node Q[n], and is configured to pull down the potential of the first node;

[0037] A first pull-down maintaining unit 14 is connected with the first node Q[n], and is configured to maintain the low potential of the first node Q[n];

[0038] A first anti-leakage unit 15 is connected with the first node Q[n], and an output end N[n] of the first anti-leakage unit 15 is connected with the pull-down unit 13 and the first pull-down maintaining unit 14, and the first anti-leakage unit 15 is configured to prevent the pull-down unit 13 and the first pull-down maintaining unit 14 from leaking electricity;

[0039] A global reset unit 16 is connected with the first node Q[n], and is configured to pull down the potential of the first node Q[n];

[0040] An inverter 17 is connected with a second node QB[n], and is configured to invert the potential of the first node Q[n] and the second node QB[n];

[0041] At least one of the gate drive units 10 further comprises a second leakage prevention unit 18 connected to at least one of the pull-down unit 13, the first pull-down maintaining unit 14 and the global reset unit 16, the second leakage prevention unit 18 is used to turn off at least one transistor (for example, the first transistor T41 in the pull-down unit 13) in the pull-down unit 13, the first pull-down maintaining unit 14 and the global reset unit 16 when the potential of the first node Q[n] is at a high potential. Figure 1 At least one of the gate drive units 10 further comprises a second leakage prevention unit 18 connected to at least one of the pull-down unit 13, the first pull-down maintaining unit 14 and the global reset unit 16, the second leakage prevention unit 18 is used to turn off at least one transistor (for example, the first transistor T41 in the pull-down unit 13) in the pull-down unit 13, the first pull-down maintaining unit 14 and the global reset unit 16 when the potential of the first node Q[n] is at a high potential.

[0042] The embodiments of the present application provide a gate drive circuit, by adding a second leakage prevention unit in at least one gate drive unit, the second leakage prevention unit is connected to at least one of the pull-down unit, the first pull-down maintaining unit and the global reset unit, so that when the threshold voltage of the transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit is negative, the second leakage prevention unit can turn off at least one transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit when the first node is at a high potential, so that the turned-off transistor cannot leak electricity, thereby reducing the leakage current of the first node, and enabling the display panel to display normally.

[0043] The embodiments of the present application provide a gate drive circuit, by adding a second leakage prevention unit in at least one gate drive unit, the second leakage prevention unit is connected to at least one of the pull-down unit, the first pull-down maintaining unit and the global reset unit, so that when the threshold voltage of the transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit is negative, the second leakage prevention unit can turn off at least one transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit when the first node is at a high potential, so that the turned-off transistor cannot leak electricity, thereby reducing the leakage current of the first node, and enabling the display panel to display normally.

[0044] The embodiments of the present application provide a gate drive circuit, by adding a second leakage prevention unit in at least one gate drive unit, the second leakage prevention unit is connected to at least one of the pull-down unit, the first pull-down maintaining unit and the global reset unit, so that when the threshold voltage of the transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit is negative, the second leakage prevention unit can turn off at least one transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit when the first node is at a high potential, so that the turned-off transistor cannot leak electricity, thereby reducing the leakage current of the first node, and enabling the display panel to display normally.

[0045] It should be noted that, Figure 1 The point marked by a black dot in the figure represents that the two lines cross at the point and are conductive at the point, but Figure 1 All the conductive points are not marked in the figure, and the actual connection is described in the following embodiments.

[0046] It should be noted that, Figure 1 N[n] in the figure comprises a plurality of connection terminals, but in actuality, the plurality of connection terminals of N[n] are a point, in order to facilitate the display and description, N[n] is divided into a plurality of connection terminals, and in actuality, the plurality of connection terminals are the same point.

[0047] It should be noted that, Figure 1 A plurality of signal terminals in the figure adopt the same reference numerals, for example, the second-stage transmission signal terminal Cout-PU comprises a plurality of signal terminals with the same reference numerals, but in actuality, the signal terminals with the same reference numerals are the same signal terminal, Figure 1 In order to facilitate the display and description of the connection of each element in the circuit, each connection

[0048] terminal is separately shown in the figure, in actuality, the signal terminals with the same reference numerals are the same signal terminal, for example, Figure 1 All the Cout-PU in the figure are the second-stage transmission signal terminals, and similarly, the signal terminals with the same reference numerals are the same signal terminal.

[0049] For the stage that the potential of the first node is pulled up in the gate drive unit provided with the first anti-creeping unit, the transistor in the first anti-creeping unit has not been turned on, which will cause the problem of creeping of the transistor connected with the first node. In an embodiment, as shown in Figure 1 The second anti-creeping unit 18 includes

[0050] The second stage signal terminal Cout-PU and the anti-creeping transistor Tn, the gate of the anti-creeping transistor Tn is connected with the second stage signal terminal Cout-PU, the first electrode of the anti-creeping transistor Tn is connected with the first low potential signal terminal VGL1, and the second electrode of the anti-creeping transistor Tn is connected with the second gate of the transistor in at least one of the pull-down unit 13, the first pull-down maintaining unit 14 and the global reset unit 16. By setting the anti-creeping transistor and designing the transistor in the pull-down unit, the first pull-down maintaining unit and the global reset unit, the first electrode of the anti-creeping transistor is connected with the first low potential signal terminal, and the second electrode of the anti-creeping transistor is connected with the second gate of the transistor in at least one of the pull-down unit, the first pull-down maintaining unit and the global reset unit, so that when the high potential is input to the first node, the transistor in at least one of the pull-down unit, the first pull-down maintaining unit and the global reset unit is closed, thereby avoiding the problem of creeping of the first node when the transistor in the first anti-creeping unit is not turned on.

[0051] It should be noted that each unit in the embodiments of the present application will include a signal terminal, for example, the second anti-creeping unit 18 includes the second stage signal terminal Cout-PU, but it can be understood that each signal terminal will exist in multiple units, each signal terminal can be regarded as a component of each unit, or each signal terminal can be regarded as an independent element which does not belong to the component of each unit, the embodiments of the present application will limit whether each signal terminal belongs to each unit for the convenience of description, but in practice, each signal terminal is not limited to belong to a specific unit.

[0052] Specifically, taking Figure 1 as an example, from Figure 1It can be seen that when the second anti-creeping unit is not set, the second-stage transmission signal terminal Cout-PU outputs a high potential, pulls up the potential of the first node Q[n], the third-stage transmission signal terminal Cout-PD is a low potential, and the transistor in the pull-down unit is in a closed state. However, due to the threshold voltage negative bias of the transistor, the voltage difference between the gate voltage Vg and the source voltage Vs is greater than the threshold voltage, at this time, the transistor in the first anti-creeping unit 15 has not opened, the first anti-creeping unit 15 cannot prevent the creeping, the anti-creeping unit is invalid, and the first node Q[n] creeps. By setting the second anti-creeping unit, the second anti-creeping unit controls the anti-creeping transistor Tn by using the second-stage transmission signal terminal Cout-PU. When the potential of the first node Q[n] is pulled up, the anti-creeping transistor Tn can be opened and input a low potential to close the transistor in the pull-down unit, so as to prevent the creeping. After the potential of the first node Q[n] is pulled up, the output end N[n] of the first anti-creeping unit outputs a high potential. Even if there is a threshold voltage negative bias, the voltage difference between the gate voltage Vg and the source voltage Vs can still be ensured to be less than the threshold voltage, so as to prevent the pull-down unit from being abnormally opened to cause the first node Q[n] to creep.

[0053] The above embodiment takes the pull-down unit in the embodiment of the present application as an example to prevent the creeping, and it can be understood that the principle of preventing the creeping is the same for other circuit units connected with the second anti-creeping unit, which will not be described herein.

[0054] In view of the problem that the transistor in the pull-down unit creeps before the first anti-creeping unit works. In an embodiment, the second electrode of the anti-creeping transistor is connected with the second gate of at least one transistor in the pull-down unit. By connecting the second electrode of the anti-creeping transistor with the second gate of at least one transistor in the pull-down unit, when the potential of the first node is pulled up, the anti-creeping transistor inputs a low potential to the gate of at least one transistor in the pull-down unit, so as to close at least one transistor in the pull-down unit, so as to reduce the current of the first node, avoid the invalidation of the anti-creeping unit, make the gate drive circuit normally output a signal, and make the display panel normally display.

[0055] In an embodiment, the first transistor includes a first gate and a second gate. When the first transistor is set, two gates can be arranged on both sides of the active pattern of the first transistor, and the two gates are connected to different signal terminals respectively to obtain a first transistor with a double-gate structure.

[0056] In an embodiment, the second transistor includes a first gate and a second gate. When the second transistor is set, two gates can be arranged on both sides of the active pattern of the second transistor, and the two gates are connected to different signal terminals respectively to obtain a second transistor with a double-gate structure.

[0057] Specifically, for the transistor of double gate structure, taking the N-type transistor as an example, the potential of any one of the two gates can be high, that is, the transistor can be controlled to be turned on, and when the potential of the two gates is low, the transistor can be controlled to be turned off, which will not be described in the following embodiments. In an embodiment, as shown in Figure 1 The pull-down unit 13 includes a first transistor T41, a second transistor T42 and a third level transmission signal end Cout-PD. The first gate of the first transistor T41 and the first gate of the second transistor T42 are connected with the third level transmission signal end Cout-PD. The first electrode of the first transistor T41 is connected with the first node Q[n]. The second electrode of the first transistor T41 and the second electrode of the second transistor T42 are connected with the output end N[n] of the first leakage prevention unit 15. The first electrode of the second transistor T42 is connected with the first low potential signal end VGL1. The second electrode of the leakage prevention transistor Tn is connected to the second gate of at least one of the first transistor T41 and the second transistor T42. By connecting the second electrode of the leakage prevention transistor with the second gate of the first transistor and the second gate of at least one of the second transistors, the problem of leakage of the first node caused by negative bias of the threshold voltage of the first transistor and / or the second transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0058] Specifically, the second electrode of the leakage prevention transistor is connected with the second gate of the first transistor. By connecting the second electrode of the leakage prevention transistor with the second gate of the first transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the first transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0059] Specifically, the second electrode of the leakage prevention transistor is connected with the second gate of the second transistor. By connecting the second electrode of the leakage prevention transistor with the second gate of the second transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the second transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0060] Specifically, as shown in Figure 1As shown, the second electrode of the leakage prevention transistor Tn is connected to the second gate of the first transistor T41, and the second electrode of the leakage prevention transistor Tn is connected to the second gate of the second transistor T42. By connecting the second electrode of the leakage prevention transistor to the second gate of the first transistor and the second gate of the second transistor, the problem of leakage of the first node caused by negative threshold voltage bias of the first transistor and the second transistor is avoided, the leakage prevention unit is prevented from failing, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0061] In view of the problem of leakage of the transistor in the first pull-down maintenance unit before the first leakage prevention unit works. In an embodiment, the second electrode of the leakage prevention transistor is connected to the second gate of at least one transistor in the first pull-down maintenance unit. By connecting the second electrode of the leakage prevention transistor to the second gate of at least one transistor in the first pull-down maintenance unit, when the potential of the first node is pulled up, the leakage prevention transistor inputs a low potential to the gate of at least one transistor in the first pull-down maintenance unit, thereby closing at least one transistor in the first pull-down maintenance unit, thereby reducing the leakage current of the first node, preventing the leakage prevention unit from failing, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0062] In an embodiment, as shown in Figure 3 The first pull-down maintenance unit 14 includes a third transistor T43A and a fourth transistor T44A, the first gate of the third transistor T43A and the first gate of the fourth transistor T44A are connected to the second node QB[n], the first electrode of the third transistor T43A is connected to the first node Q[n], the second electrode of the third transistor T43A and the first electrode of the fourth transistor T44A are connected to the output end N[n] of the first leakage prevention unit 15, the second electrode of the fourth transistor T44A is connected to the first low potential signal end VGL1, and the second electrode of the leakage prevention transistor Tn is connected to the second gate of at least one of the third transistor T43A and the fourth transistor T44A. By connecting the second electrode of the leakage prevention transistor to the second gate of at least one of the third transistor and the fourth transistor, the problem of leakage of the first node caused by negative threshold voltage bias of the third transistor and / or the fourth transistor is avoided, the leakage prevention unit is prevented from failing, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0063] Specifically, the second electrode of the leakage prevention transistor is connected to the second gate of the third transistor. By connecting the second electrode of the leakage prevention transistor to the second gate of the third transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the third transistor is avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0064] Specifically, the second electrode of the leakage prevention transistor is connected to the second gate of the fourth transistor. By connecting the second electrode of the leakage prevention transistor to the second gate of the fourth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the fourth transistor is avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0065] In an embodiment, the third transistor includes a first gate and a second gate. When the third transistor is arranged, two gates can be arranged on both sides of the active pattern of the third transistor, and the two gates are respectively connected to different signal terminals to obtain a third transistor with a double-gate structure.

[0066] In an embodiment, the fourth transistor includes a first gate and a second gate. When the fourth transistor is arranged, two gates can be arranged on both sides of the active pattern of the fourth transistor, and the two gates are respectively connected to different signal terminals to obtain a fourth transistor with a double-gate structure.

[0067] Specifically, as shown in Figure 3 the second electrode of the leakage prevention transistor Tn is connected to the second gate of the third transistor T43A, and the second electrode of the leakage prevention transistor Tn is connected to the second gate of the fourth transistor T44A. By connecting the second electrode of the leakage prevention transistor to the second gate of the third transistor and the second gate of the fourth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the third transistor and the fourth transistor is avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0068] In an embodiment, as shown in Figure 1As shown, the first pull-down maintaining unit 14 further includes a fifth transistor T43B and a sixth transistor T44B, a first gate of the fifth transistor T43B and a first gate of the sixth transistor T44B are connected with the third node QB[n-1], a first electrode of the fifth transistor T43B is connected with the first node Q[n], a second electrode of the fifth transistor T43B and a first electrode of the sixth transistor T44B are connected with an output end N[n] of the first leakage prevention unit 15, a second electrode of the sixth transistor T44B is connected with the first low potential signal end VGL1, and the second electrode of the leakage prevention transistor is connected to a second gate of at least one of the fifth transistor T43B and the sixth transistor T44B. By connecting the second electrode of the leakage prevention transistor with the second gate of at least one of the fifth transistor and the sixth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the fifth transistor and / or the sixth transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0069] Specifically, the second electrode of the leakage prevention transistor is connected with the second gate of the fifth transistor. By connecting the second electrode of the leakage prevention transistor with the second gate of the fifth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the fifth transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0070] Specifically, the second electrode of the leakage prevention transistor is connected with the second gate of the sixth transistor. By connecting the second electrode of the leakage prevention transistor with the second gate of the sixth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the sixth transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0071] Specifically, the second electrode of the leakage prevention transistor is connected with the second gate of the fifth transistor, and the second electrode of the leakage prevention transistor is connected with the second gate of the sixth transistor. By connecting the second electrode of the leakage prevention transistor with the second gate of the fifth transistor and the second gate of the sixth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the fifth transistor and the sixth transistor can be avoided, the leakage prevention unit is prevented from being invalid, the gate drive circuit can normally output signals, and the display panel can normally display.

[0072] To address the issue of leakage current in the transistors of the global reset unit before the first leakage protection unit operates, in one embodiment, the second electrode of the leakage protection transistor is connected to the second gate of at least one transistor in the global reset unit. By connecting the second electrode of the leakage protection transistor to the second gate of at least one transistor in the global reset unit, when the potential of the first node is pulled high, the leakage protection transistor inputs a low potential to the gate of at least one transistor in the global reset unit, thereby turning off at least one transistor in the global reset unit. This reduces the leakage current of the first node, prevents the leakage protection unit from failing, allows the gate drive circuit to output signals normally, and enables the display panel to display normally.

[0073] In one embodiment, the seventh transistor includes a first gate and a second gate. When setting the seventh transistor, two gates can be set on both sides of the active pattern of the seventh transistor, and the two gates can be connected to different signal terminals respectively to obtain a seventh transistor with a dual-gate structure.

[0074] In one embodiment, the eighth transistor includes a first gate and a second gate. When setting the eighth transistor, two gates can be set on both sides of the active pattern of the eighth transistor, and the two gates can be connected to different signal terminals respectively to obtain the eighth transistor with a dual-gate structure.

[0075] In one embodiment, such as Figure 4 As shown, the global reset unit 16 includes a seventh transistor T45, an eighth transistor T46, and a global reset signal terminal VST. The first gates of the seventh transistor T45 and the eighth transistor T46 are connected to the global reset signal terminal VST. The first electrode of the seventh transistor T45 is connected to the first node Q[n]. The second electrodes of the seventh transistor T45 and the eighth transistor T46 are connected to the output terminal N[n] of the first leakage protection unit 15. The second electrode of the eighth transistor T46 is connected to the output signal terminal WR[n]. The second electrode of the leakage protection transistor Tn is connected to the second gate of at least one of the seventh transistor T45 and the eighth transistor T46. By connecting the second electrode of the leakage protection transistor to the second gate of the seventh transistor and the second gate of at least one of the eighth transistors, the problem of leakage current in the first node caused by the negative bias of the threshold voltage of the seventh transistor and / or the eighth transistor can be avoided, thus preventing the leakage protection unit from failing, ensuring that the gate drive circuit outputs a signal normally, and enabling the display panel to display normally.

[0076] Specifically, the second electrode of the anti-leakage transistor is connected with the second gate of the seventh transistor. By connecting the second electrode of the anti-leakage transistor with the second gate of the seventh transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the seventh transistor is avoided, the anti-leakage unit is prevented from being invalid, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0077] Specifically, the second electrode of the anti-leakage transistor is connected with the second gate of the eighth transistor. By connecting the second electrode of the anti-leakage transistor with the second gate of the eighth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the eighth transistor is avoided, the anti-leakage unit is prevented from being invalid, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0078] Specifically, as shown in Figure 4 the second electrode of the anti-leakage transistor Tn is connected with the second gate of the seventh transistor T45, and the second electrode of the anti-leakage transistor Tn is connected with the second gate of the eighth transistor T46. By connecting the second electrode of the anti-leakage transistor with the second gate of the seventh transistor and the second gate of the eighth transistor, the problem of leakage of the first node caused by negative bias of the threshold voltage of the seventh transistor and the eighth transistor is avoided, the anti-leakage unit is prevented from being invalid, the gate drive circuit normally outputs signals, and the display panel can normally display.

[0079] Specifically, after a frame ends, the global reset unit can output a high potential through the global reset signal end VST to open the seventh transistor T45 and the eighth transistor T46, and pull down the first node of the gate drive unit of all levels.

[0080] In order to solve the problem that the transistors in the pull-down unit, the first pull-down maintaining unit and the global reset unit will appear leakage before the first leakage prevention unit works. In an embodiment, the second electrode of the leakage prevention transistor is connected with the second gate of at least one transistor in the pull-down unit, the second electrode of the leakage prevention transistor is connected with the second gate of at least one transistor in the first pull-down maintaining unit, and the second electrode of the leakage prevention transistor is connected with the second gate of at least one transistor in the global reset unit. By connecting the second electrode of the leakage prevention unit with the second gate of at least one transistor in the pull-down unit, the threshold voltage negative bias of the transistor in the pull-down unit can be prevented from causing the first node to leak. By connecting the second electrode of the leakage prevention unit with the second gate of at least one transistor in the first pull-down maintaining unit, the threshold voltage negative bias of the transistor in the first pull-down maintaining unit can be prevented from causing the first node to leak. By connecting the second electrode of the leakage prevention unit with the second gate of at least one transistor in the global reset unit, the threshold voltage negative bias of the transistor in the global reset unit can be prevented from causing the first node to leak. Thus, the problem that the transistors in the pull-down unit, the first pull-down maintaining unit and the global reset unit will appear leakage before the first leakage prevention unit works is solved, the leakage current of the first node is reduced, the leakage prevention unit is prevented from failing, the gate drive circuit can normally output signals, and the display panel can normally display.

[0081] Specifically, for the connection structure of the leakage prevention transistor and the transistor in the pull-down unit, the connection structure of the leakage prevention transistor and the transistor in the first pull-down maintaining unit, and the connection structure of the leakage prevention transistor and the transistor in the global reset unit, please refer to the above embodiments, which will not be described here.

[0082] In view of the poor stability of a single transistor and the problem that the single transistor cannot prevent leakage when it fails, in an embodiment, the leakage prevention transistor includes a first leakage prevention transistor, a second leakage prevention transistor and a third leakage prevention transistor, the gate of the first leakage prevention transistor, the gate of the second leakage prevention transistor and the gate of the third leakage prevention transistor are connected to the second-stage signal transmission terminal, the first electrode of the first leakage prevention transistor, the first electrode of the second leakage prevention transistor and the first electrode of the third leakage prevention transistor are connected to the first low potential signal terminal, the second electrode of the first leakage prevention transistor is connected to the second gate of at least one transistor in the pull-down unit, the second electrode of the second leakage prevention transistor is connected to the second gate of at least one transistor in the first pull-down maintenance unit, and the second electrode of the third leakage prevention transistor is connected to the second gate of at least one transistor in the global reset unit. By arranging multiple leakage prevention transistors, each leakage prevention transistor prevents leakage of the pull-down unit, the pull-down maintenance unit and the global reset unit, respectively, thereby improving the leakage prevention effect of the gate drive circuit, avoiding failure of the leakage prevention unit, enabling the gate drive circuit to normally output signals and enabling the display panel to normally display.

[0083] Specifically, for the connection structure of the first leakage prevention transistor and the transistor in the pull-down unit, the connection structure of the second leakage prevention transistor and the transistor in the first pull-down maintenance unit, and the connection structure of the third leakage prevention transistor and the transistor in the global reset unit, refer to the above embodiments, which will not be described here.

[0084] The above embodiments take the example of the second electrode of the leakage prevention transistor being connected to the second gate of the transistor in the pull-down unit, the first pull-down maintenance unit and the global reset unit, but the embodiments of the present application are not limited thereto. For example, when other circuit units are connected to the first node and cause leakage of the first node, the second leakage prevention unit in the embodiments of the present application can be used to connect the circuit units to prevent leakage.

[0085] The above embodiments take the example of the gate of the leakage prevention transistor being directly connected to the second-stage signal transmission terminal, but the embodiments of the present application are not limited thereto. For example, an input signal terminal can be added, the timing signal of the input signal terminal is the same as the timing signal of the second-stage signal transmission terminal, and the leakage prevention transistor is controlled to be turned on and off.

[0086] The above embodiments take the example of the first electrode of the leakage prevention transistor being directly connected to the first low potential signal terminal, but the embodiments of the present application are not limited thereto. For example, an input signal terminal can be added, the input signal terminal is kept at a low potential, and a low potential is input to the leakage prevention transistor. Alternatively, the first electrode of the leakage prevention transistor is connected to a second low potential signal terminal, or the first electrode of the leakage prevention transistor is connected to a third low potential signal terminal.

[0087] The above embodiments are described in detail using the example of a single leakage-proof transistor connected to a circuit unit. This design is intended to reduce the complexity and space occupied by the gate drive circuit. However, the embodiments of this application are not limited to this. For example, multiple leakage-proof transistors can be used to connect to a single circuit unit.

[0088] In one embodiment, such as Figure 1 As shown, the pull-up control unit 11 includes a ninth transistor T11 and a tenth transistor T12. The gate and first electrode of the ninth transistor T11 and the gate of the tenth transistor T12 are connected to the second-stage signal transmission terminal Cout-PU. The second electrode of the ninth transistor T11 is connected to the first electrode of the tenth transistor T12, and the second electrode of the tenth transistor T12 is connected to the first node Q[n]. The pull-up control unit controls the potential of the first node, thereby controlling whether a signal is output.

[0089] In one embodiment, such as Figure 1 As shown, the pull-up unit 12 includes an eleventh transistor T21, a twelfth transistor T22, a first clock signal terminal CKa, and a second clock signal terminal CKb. The gates of the eleventh transistor T21 and the twelfth transistor T22 are connected to the first node Q[n]. The first electrode of the eleventh transistor T21 is connected to the first clock signal terminal CKa, the first electrode of the twelfth transistor T22 is connected to the second clock signal terminal CKb, the second electrode of the eleventh transistor T21 is connected to the first stage transmission signal terminal Cout[n], and the second electrode of the twelfth transistor T22 is connected to the output signal terminal WR[n]. By using a clock signal input, each gate driving unit can be controlled to control the display panel display.

[0090] In one embodiment, such as Figure 1 As shown, the first leakage protection unit 15 includes a thirteenth transistor T71, a fourteenth transistor T72, and a high-potential signal terminal VGH. The gates of the thirteenth transistor T71 and the fourteenth transistor T72 are connected to the first node Q[n]. The first electrode of the fourteenth transistor T72 is connected to the high-potential signal terminal VGH, and the second electrode of the fourteenth transistor T72 is connected to the first electrode of the thirteenth transistor T71. The second electrode of the thirteenth transistor T71 is connected to the output terminal N[n]. By connecting the gate of the first leakage protection unit to the first node, the first leakage protection unit outputs a high-potential signal. The output terminal of the first leakage protection unit is connected to the transistors of the pull-down unit, the first pull-down sustaining unit, and the global reset unit, thereby preventing leakage current from the transistors of the pull-down unit, the first pull-down sustaining unit, and the global reset unit.

[0091] In one embodiment, such as Figure 1 As shown, the inverter 17 includes a fifteenth transistor T51A, a sixteenth transistor T51B, a seventeenth transistor T52, an eighteenth transistor T53, a nineteenth transistor T54, a twentieth transistor T55, a twenty-first transistor T56, and a low-frequency clock signal LC. The gate and first electrode of the fifteenth transistor T51A, the gate of the sixteenth transistor T51B, and the first electrode of the eighteenth transistor T53 are connected to the low-frequency clock signal LC. The second electrode of the fifteenth transistor T51A is connected to the first electrode of the sixteenth transistor T51B. The second electrode of the sixteenth transistor T51B, the first electrode of the seventeenth transistor T52, the gate of the eighteenth transistor T53, and the first electrode of the twentieth transistor T55 are connected. The gates of the seventeenth transistor T52 and the nineteenth transistor T54 are connected to the first node Q[n]. The second electrode of the seventeenth transistor T52 and the second electrode of the twentieth transistor T55 are connected to the second low-potential signal terminal VGL2. The second electrode of the eighteenth transistor T53, the first electrode of the nineteenth transistor T54, and the first electrode of the twenty-first transistor T56 are connected to the second node QB[n]. The second electrodes of the nineteenth transistor T54 and the twenty-first transistor T56 are connected to the first low-potential signal terminal VGL1. The gate of the twentieth transistor T55 is connected to the fourth node Q[n-1], and the gate of the twenty-first transistor T56 is connected to the second-stage signal transmission terminal Cout-PU. By setting an inverter, the potentials of the first and second nodes are reversed, allowing the circuit to operate normally.

[0092] In one embodiment, such as Figure 1As shown, the gate driving unit further comprises a second pull-down maintaining unit, the second pull-down maintaining unit comprises a twenty-second transistor T31A, a twenty-third transistor T31B, a twenty-fourth transistor T32A and a twenty-fifth transistor T32B, a gate of the twenty-second transistor T31A and the twenty-fourth transistor T32A is connected to the second node QB[n], a first electrode of the twenty-second transistor T31A and the twenty-third transistor T31B is connected to the first low potential signal end VGL1, a second electrode of the twenty-second transistor T31A and the twenty-third transistor T31B is connected to the first stage transmission signal end Cout[n], a gate of the twenty-third transistor T31B and the twenty-fifth transistor T32B is connected to the third node QB[n-1], a first electrode of the twenty-fourth transistor T32A and the twenty-fifth transistor T32B is connected to the third low potential signal end, a second electrode of the twenty-fourth transistor T32A and the twenty-fifth transistor T32B is connected to the output signal end WR[n], by setting the second pull-down maintaining unit, the potential of the first stage transmission signal end Cout[n] and the output signal end WR[n] can be maintained at a low potential after the gate driving circuit outputs a signal.

[0093] In an embodiment, as shown in Figure 1 , the gate driving unit further comprises a first capacitor C1 and a second capacitor C2.

[0094] Specifically, Figure 1 The n-th gate driving unit in the gate driving circuit provided by the embodiment of the present application, therefore, the output signal end is marked as WR[n], it can be understood that according to the value of n, it represents the design of the gate driving unit of different stages. At the same time, part of the signal end in the embodiment of the present application is the signal end of the previous stage, for example, the third node QB[n-1] represents the second node in the previous stage gate driving circuit, the fourth node Q[n-1] represents the first node in the previous stage gate driving circuit, the second stage transmission signal end Cout-PU represents the signal end of the previous stage, for example, the first stage transmission signal end of the first stage gate driving unit is the second stage transmission signal end of the fourth stage gate driving unit, and the third stage transmission signal end Cout-PD is the signal end of the previous stage.

[0095] Specifically, the output signal end WR[n] is the opening signal of the pixel internal switch transistor of the present stage.

[0096] Specifically, the gate driving unit shown in Figure 1 , the timing diagram of each signal end and each point in the gate driving unit shown in Figure 2 , the working process of the gate driving unit is described, as shown in Figure 1 , Figure 2As shown, in the first stage T1, the second stage transmission signal end Cout-PU inputs high potential, the ninth transistor T11 and the tenth transistor T12 are turned on, the first node Q[n] is pulled up to high potential, the thirteenth transistor T71 and the fourteenth transistor T72 are turned on, and the output end N[n] of the first leakage prevention unit 15 outputs high potential.

[0097] In the second stage T2, the first clock signal end CKa (not shown in the figure) and the second clock signal end CKb input high potential, the eleventh transistor T21 and the twelfth transistor T22 are turned on, the first stage transmission signal end Cout[n] and the output signal end WR[n] output high potential signal, and the switch transistor in the pixel can be turned on, and the first node Q[n] is coupled to higher potential due to the first capacitor C1. Figure 2

[0098] In the third stage T3, after the signal output of the first stage transmission signal end Cout[n] and the output signal end WR[n] is completed, the third stage transmission signal end Cout-PD inputs high potential, the first transistor T41 and the second transistor T42 are turned on, the potential of the first node Q[n] is pulled down, at the same time, the thirteenth transistor T71 and the fourteenth transistor T72 are turned off, and the output end N[n] of the first leakage prevention unit 15 has no high potential output.

[0099] In an embodiment, the above-mentioned transistors can be low-temperature polysilicon thin film transistors, oxide thin film transistors and hydrogenated polycrystalline thin film transistors grown by low-temperature solid-phase crystallization process.

[0100] Meanwhile, the embodiment of the present application provides a display panel, which comprises the gate drive circuit according to any one of the above-mentioned embodiments.

[0101] According to the above-mentioned embodiments, it can be known that:

[0102] ​The embodiment of the present application provides a kind of gate drive circuit and display panel;The gate drive circuit includes a plurality of cascaded multiple gate drive units, and the gate drive unit includes pull-up control unit, pull-up unit, pull-down unit, first pull-down maintenance unit, first anti-leakage unit, global reset unit and inverter, pull-up control unit is connected with first node, for the potential of first node is pulled high, pull-up unit is connected with first node, for the potential of first stage signal end and output signal end is pulled high, pull-down unit is connected with first node, for the potential of first node is pulled low, first pull-down maintenance unit is connected with first node, for maintaining the low potential of first node, first anti-leakage unit is connected with first node, the output of first anti-leakage unit is connected with pull-down unit and first pull-down maintenance unit, for preventing pull-down unit and first pull-down maintenance unit from leaking, global reset unit is connected with first node, for the potential of first node is pulled low, inverter is connected with second node, for the potential of first node and second node is reversed, wherein, at least one gate drive unit further includes second anti-leakage unit, second anti-leakage unit is connected with at least one of pull-down unit, first pull-down maintenance unit and global reset unit, and second anti-leakage unit is used to close at least one transistor of pull-down unit, first pull-down maintenance unit and global reset unit when the potential of first node is at high potential.The present application is increased by adding second anti-leakage unit in at least one gate drive unit, so that second anti-leakage unit is connected with at least one of pull-down unit, first pull-down maintenance unit and global reset unit, so that when the threshold voltage of transistor in pull-down unit, first pull-down maintenance unit and global reset unit is negative, since second anti-leakage unit can close at least one transistor of pull-down unit, first pull-down maintenance unit and global reset unit when first node is at high potential, so that the closed transistor cannot leak, thereby reducing the leakage current of first node, so that display panel can be normally displayed.

[0103] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0104] The above has carried out detailed introduction to the gate drive circuit and display panel provided by the embodiment of the present application, the principle and implementation mode of the present application are described in this paper, the above embodiment is only used to help understanding the technical scheme and core idea of the present application;Ordinary skilled in the art should understand that: it can still modify the technical scheme recorded in the foregoing embodiments, or equivalent replacement to part of technical features;And these modifications or replacements, do not make the essence of corresponding technical scheme deviate from the scope of the technical scheme of the embodiment of the present application.

Claims

1. A gate drive circuit characterized by comprising: The gate drive unit comprises a plurality of gate drive units connected in cascade, and each gate drive unit comprises: a pull-up control unit connected to the first node and configured to pull up the potential of the first node; a pull-up unit connected to the first node and configured to pull up the potentials of the first-stage signal terminal and the output signal terminal; a pull-down unit connected to the first node and configured to pull down the potential of the first node; a first pull-down maintaining unit connected to the first node and configured to maintain the low potential of the first node; a first anti-leakage unit connected to the first node, and an output terminal of the first anti-leakage unit being connected to the pull-down unit and the first pull-down maintaining unit, the first anti-leakage unit being configured to prevent the pull-down unit and the first pull-down maintaining unit from leaking electricity; a global reset unit connected to the first node and configured to pull down the potential of the first node; an inverter connected to the second node and configured to invert the potentials of the first node and the second node; wherein at least one of the gate drive units further comprises a second anti-leakage unit connected to at least one of the pull-down unit and the global reset unit, the second anti-leakage unit being configured to turn off at least one transistor of the pull-down unit and the global reset unit when the potential of the first node is at a high potential.

2. The gate drive circuit of claim 1, wherein The second anti-leakage unit comprises a second-stage signal terminal and an anti-leakage transistor, a gate of the anti-leakage transistor being connected to the second-stage signal terminal, a first electrode of the anti-leakage transistor being connected to a first low-potential signal terminal, and a second electrode of the anti-leakage transistor being connected to a second gate of at least one transistor of the pull-down unit and the global reset unit.

3. The gate drive circuit of claim 2, wherein, The second electrode of the anti-leakage transistor is connected to the second gate of at least one transistor of the pull-down unit.

4. The gate drive circuit of claim 3, wherein, The pull-down unit comprises a first transistor, a second transistor, and a third-stage signal terminal, a first gate of the first transistor and a first gate of the second transistor being connected to the third-stage signal terminal, a first electrode of the first transistor being connected to the first node, a second electrode of the first transistor and a second electrode of the second transistor being connected to an output terminal of the first anti-leakage unit, a first electrode of the second transistor being connected to the first low-potential signal terminal, and a second electrode of the anti-leakage transistor being connected to a second gate of at least one of the first transistor and the second transistor.

5. The gate drive circuit of claim 2, wherein, The second electrode of the anti-leakage transistor is connected to a second gate of at least one transistor of the global reset unit.

6. The gate drive circuit of claim 5, wherein, The global reset unit comprises a seventh transistor, an eighth transistor and a global reset signal terminal, a first gate of the seventh transistor and a first gate of the eighth transistor are connected with the global reset signal terminal, a first electrode of the seventh transistor is connected with the first node, a second electrode of the seventh transistor and a first electrode of the eighth transistor are connected with an output terminal of the first leakage prevention unit, a second electrode of the eighth transistor is connected with the output signal terminal, and a second electrode of the leakage prevention transistor is connected to a second gate of at least one of the seventh transistor and the eighth transistor.

7. The gate drive circuit of claim 2, wherein, The second electrode of the leakage prevention transistor is connected with a second gate of at least one transistor in the pull-down unit, and the second electrode of the leakage prevention transistor is connected with a second gate of at least one transistor in the global reset unit.

8. The gate drive circuit of claim 2, wherein, The leakage prevention transistor comprises a first leakage prevention transistor and a third leakage prevention transistor, a gate of the first leakage prevention transistor and a gate of the third leakage prevention transistor are connected with the second level signal terminal, a first electrode of the first leakage prevention transistor and a first electrode of the third leakage prevention transistor are connected with the first low potential signal terminal, a second electrode of the first leakage prevention transistor is connected with a second gate of at least one transistor in the pull-down unit, and a second electrode of the third leakage prevention transistor is connected with a second gate of at least one transistor in the global reset unit.

9. A display panel, characterized by, The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 8.

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