A semiconductor device structure and a method of fabricating the same

Abstract

The application provides a semiconductor device structure and a preparation method thereof, which comprises the following steps: providing a semiconductor substrate, forming a well region and an active region in the semiconductor substrate; forming a gate structure composed of a gate isolation layer, a polysilicon layer and a gate insulation layer on the semiconductor substrate between the well regions, and forming a second metal layer on the surface of the well region on both sides of the gate structure, wherein the gate isolation layer further comprises a first metal layer which forms a Schottky contact with the surface of the semiconductor substrate. The application introduces the first metal layer into the gate isolation layer on the basis of the gate structure, forms a Schottky contact between the first metal layer and the surface of the semiconductor substrate between the well regions, thereby reducing the forward opening voltage drop and the reverse recovery time of the semiconductor device structure, limiting the generation of reverse leakage current, and reducing the width between cells, and further improving the device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device structure and a preparation method thereof. BACKGROUND

[0002] In recent years, the third generation semiconductor material represented by silicon carbide (SiC) is widely used in the field of high-voltage semiconductor technology due to its excellent material performance. On this basis, SiC MOSFET device products exhibit low on-resistance and fast switching speed, and have also appeared in the semiconductor market, especially in the fields of new energy vehicles, photovoltaic solar inverters and the like, and have a broad application prospect.

[0003] Compared with the planar SiC MOSFET, the trench SiC MOSFET needs to form a trench on the SiC crystal by additional etching, and the quality of the trench directly determines the performance of the device, such as breakdown voltage, switching life and on-resistance, and the technical difficulty of the preparation process is relatively high. In contrast, the planar SiC MOSFET has a more mature and simple preparation process, and since the process of forming a trench by additional etching is avoided, the planar SiC MOSFET still occupies a dominant position in the SiC MOSFET market.

[0004] As a switching device, the body diode of the SiC MOSFET transistor has a high PN junction built-in voltage, and thus has problems of high on-voltage drop and long reverse recovery time, which greatly limits the application of the SiC MOSFET body diode in reverse current scenarios and the like. To solve the above problems, the prior art increases a Schottky contact region in the middle region of the device cell, and shields the opening of the PN junction diode during reverse conduction through the internally integrated Schottky diode, thereby reducing the recovery time and voltage drop of the device during reverse conduction. However, the increase of the Schottky contact region in the middle region of the P-well increases the width (Cell Pitch) of a single SiC MOSFET cell, thereby increasing the on-resistance of the device, which is not conducive to device design.

[0005] Therefore, how to provide a semiconductor device structure and a preparation method thereof, which can further reduce the size of the device structure and improve the performance of the semiconductor device, has become a problem to be solved in the field. SUMMARY

[0006] The purpose of the present application is to provide a semiconductor device structure and a preparation method thereof, which integrates a Schottky diode in the internal structure of a semiconductor cell, thereby reducing the size of the semiconductor device structure and improving the performance of the semiconductor device.

[0007] In a first aspect, the present application provides a semiconductor device structure, comprising:

[0008] providing a semiconductor substrate, forming a plurality of first conductive type well regions arranged at intervals in the semiconductor substrate, and an active region of a second conductive type in the well regions;

[0009] forming a gate structure on the semiconductor substrate between adjacent well regions, the gate structure comprising a gate isolation layer, a polysilicon layer and a gate insulation layer stacked in sequence; wherein the gate isolation layer is provided with a first metal layer in Schottky contact with the surface of the semiconductor substrate, and the first metal layer is not in contact with the polysilicon layer;

[0010] forming a second metal layer on the surface of the well regions on both sides of the gate structure, and electrically connecting the second metal layer with the first metal layer.

[0011] In a possible implementation, the forming step of the gate isolation layer comprises:

[0012] forming a first oxide layer on the surface of the semiconductor substrate between the well regions, and etching a first opening exposing the surface of the semiconductor substrate on the first oxide layer;

[0013] forming a first metal layer on the first oxide layer, and the first metal layer filling the first opening is in Schottky contact with the surface of the semiconductor substrate;

[0014] forming a second oxide layer on the first oxide layer, the second oxide layer covering at least the first opening.

[0015] In a possible implementation, the forming step of the first metal layer comprises:

[0016] sputtering a metal layer on the first oxide layer, the metal layer covering the surface of the first oxide layer and filling the first opening;

[0017] Schottky annealing the metal layer filling the first opening to form Schottky contact with the surface of the semiconductor substrate;

[0018] etching to remove part of the metal layer on the surface of the first oxide layer, forming a patterned first metal layer.

[0019] In a possible implementation, the first oxide layer is formed by a thermal oxidation process, and the first opening exposes at least part of the surface of the semiconductor substrate between adjacent well regions.

[0020] In a possible implementation, the gate insulation layer covers the polysilicon layer and extends to the semiconductor substrate beyond the polysilicon layer, and the step of forming a second metal layer on the semiconductor substrate comprises:

[0021] forming a second opening on the gate insulation layer, the second opening exposing at least part of the well region and the second active region;

[0022] forming a second metal layer in the second opening, the second metal layer forming ohmic contact with the contact surface of the well region and the active region.

[0023] In a possible implementation, the etching range of the second opening covers at least part of the gate insulation layer, and the second metal layer is electrically connected to the first metal layer at the sidewall of the second opening.

[0024] In a possible implementation, the semiconductor substrate comprises a substrate layer of a second conductivity type and an epitaxial layer, the doping concentration of ions of the second conductivity type in the epitaxial layer is lower than that in the substrate layer; and the material of the substrate layer is 4H-SiC.

[0025] In a possible implementation, the first metal layer is a single-layer structure of a nickel layer, a titanium layer or a molybdenum layer.

[0026] In a possible implementation, the method for manufacturing the semiconductor device structure further comprises the steps of forming a plurality of lead electrodes and a third metal layer, the plurality of lead electrodes are respectively electrically connected to the second metal layer and the polysilicon layer, and the third metal layer is located on the surface of the semiconductor substrate away from the gate structure.

[0027] In a second aspect, the present application also provides a semiconductor device structure manufactured by the method for manufacturing the semiconductor device structure.

[0028] Compared with the prior art, the present application has at least the following advantages:

[0029] The application provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a semiconductor substrate, a well region and an active region formed in the semiconductor substrate; a gate structure is formed on the semiconductor substrate between adjacent well regions, the gate structure comprises a gate isolation layer, a polysilicon layer and a gate insulation layer, the gate isolation layer further comprises a first metal layer which forms a Schottky contact with the surface of the semiconductor substrate; and a second metal layer is formed on the surface of the well region on both sides of the gate structure. The first metal layer is introduced into the gate isolation layer based on the gate structure, the Schottky contact is formed between the first metal layer and the surface of the semiconductor substrate, thereby reducing the forward opening voltage drop and the reverse recovery time of the semiconductor device structure, limiting the generation of reverse leakage current, reducing the width between cells, and further improving the device performance. Compared with the prior art which integrates a Schottky diode outside the cell, the Schottky diode is integrated in the cell, thereby reducing the width between cells, avoiding the problem that the forward conduction resistance of the device increases with the increase of the cell size, and further improving the device performance. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0031] Figure 1 A step flow chart of a preparation method of a semiconductor device structure according to an embodiment of the application is shown.

[0032] Figure 2 A schematic diagram of a semiconductor device structure according to the prior art is shown.

[0033] Figure 3 A structure schematic diagram of a semiconductor substrate according to an embodiment of the application is shown.

[0034] Figure 4 A structure schematic diagram of a gate structure according to an embodiment of the application is shown.

[0035] Figure 5 A cross-sectional structure schematic diagram of a first metal layer according to an embodiment of the application is shown.

[0036] Figure 6 A schematic diagram of a semiconductor device structure according to an embodiment of the application is shown.

[0037] ILLUSTRATION:

[0038] 100 semiconductor substrate; 110 substrate layer; 120 epitaxial layer; 130 well region; 140 active region; 150 JFET region; 200 gate structure; 210 gate isolation layer; 211 first oxide layer; 212 second oxide layer; 220 polysilicon layer; 230 gate insulation layer; 240 first metal layer; 300 second metal layer. DETAILED DESCRIPTION

[0039] The above objects, advantages and other features of the present application are explained in more detail in the detailed description below.

[0040] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal connection of two elements. For those skilled in the art, the specific meaning of the above-mentioned term in the present application can be understood according to the specific circumstances. In addition, the terms "first" and "second" are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0041] The body diode of SiC MOSFET transistor as a switching device has the problems of high conduction voltage drop and long recovery time in reverse conduction due to the high PN junction built-in voltage, which greatly limits the application of SiC MOSFET body diode in reverse current continuation scenes and the like. Referring to Figure 2 To solve the above problems, the prior art adds a Schottky contact region 400 inside the device structure, and through the internal integrated Schottky diode, the opening of the PN junction diode is shielded in reverse conduction, thereby reducing the recovery time and voltage drop of the device in reverse conduction. However, the addition of the Schottky contact region in the middle of the well region 130 increases the width of the single SiC MOSFET cell, thereby increasing the forward conduction resistance of the device, which is not conducive to the design of the device.

[0042] To solve the above problems, the applicant finds that, on the basis of the existing cell structure, the Schottky contact region 400 is arranged in the JFET region (Junction Field Effect Transistor region) directly below the anode structure, that is, the Schottky diode formed can reduce the forward conduction voltage drop, and the pinch-off effect of the JFET region can also reduce the reverse leakage current of the Schottky diode, forming a JBS structure. At the same time, the Schottky contact region is arranged in the JFET region in the existing cell, so as not to increase the width between the cells, avoiding the increase of the forward conduction resistance of the device. Based on the above finding, the applicant provides a semiconductor device structure and a preparation method thereof to reduce the size of the semiconductor device structure and improve the performance of the semiconductor device.

[0043] According to one aspect of the present application, referring to Figure 1 , a preparation method of a semiconductor device structure is provided. The method specifically comprises the following steps:

[0044] Firstly, step S1 is performed to provide a semiconductor substrate 100, and a plurality of first conductive type well regions 130 arranged at intervals and an active region 140 of a second conductive type in the well region 130 are formed in the semiconductor substrate 100. The first conductive type can be P type, such as an area doped with aluminum (Al) ions, boron (B) ions, etc., and the second conductive type can be N type, such as an area doped with phosphorus (P) ions, arsenic (As) ions, etc., or the first conductive type and the second conductive type are opposite, that is, the first conductive type is N type and the second conductive type is P type.

[0045] As an example, referring to Figure 3 , the semiconductor substrate 100 includes a substrate layer 110 of the second conductive type and an epitaxial layer 120, which can be formed on the substrate layer 110 by an epitaxial process. The subsequently formed well regions 130 and other structures are located in the epitaxial layer 120, and the bottom of each structure is preferably kept a certain distance from the bottom of the epitaxial layer 120. That is, the depth of each structure formed subsequently in the epitaxial layer 120 is less than the thickness of the epitaxial layer 120, and the region of the epitaxial layer 120 between adjacent well regions 130 is a JFET region 150.

[0046] Optionally, the specific steps of forming the plurality of spaced first-conductivity-type well regions 130 in the epitaxial layer 120 and the active region 140 of the second-conductivity-type in the well region 130 include: first, forming a first mask layer on the epitaxial layer 120 for defining the pattern position of the well region 130 on the epitaxial layer 120, and then performing ion implantation of the first-conductivity-type on the epitaxial layer 120 under the action of the first mask layer, thereby forming the plurality of spaced first-conductivity-type well regions 130, and the area covered by the first mask layer is the JFET region 150. Then, a second mask layer is formed for defining the pattern of the active region 140. Under the joint action of the first mask layer and the second mask layer, ion implantation of the second-conductivity-type is performed on the well region 130, thereby forming the active region 140 in the well region 130. Finally, the residual first mask layer and the second mask layer are removed. It should be noted that the ion implantation parameters of the well region 130 and the active region 140 can refer to the conventional parameters in the art, which are not limited in the present embodiment, but the well region 130 is usually lightly doped, and the active region 140 is heavily doped. It should be noted that the active region 140 can be a single active region 140 of the second-conductivity-type, or a combination of a plurality of active regions 140 of different conductivity types. The specific arrangement of the active region 140 is not limited in the present application.

[0047] Optionally, based on the consideration of the lattice matching and thermal matching between the substrate layer 110 and the epitaxial layer 120, the material of the epitaxial layer 120 is preferably the same as that of the substrate layer 110, i.e., when the material of the substrate layer 110 is 4H-SiC, the material of the epitaxial layer 120 is also 4H-SiC, and the doping concentration of the second-conductivity-type conductive ions in the epitaxial layer 120 is lower than that of the substrate layer 110.

[0048] Then, step S2 is performed to form a gate structure 200 on the semiconductor substrate 100 between adjacent well regions 130, the gate structure 200 including a gate isolation layer 210, a polysilicon layer 220, and a gate insulating layer 230 stacked in order from bottom to top. Among them, referring to Figure 4 , the gate isolation layer 210 is provided with a first metal layer 240 forming a Schottky contact with the surface of the semiconductor substrate 100, and the first metal layer 240 does not contact the polysilicon layer 220.

[0049] As an example, the forming step of the gate isolation layer 210 specifically includes:

[0050] Step S21, forming a first oxide layer 211.

[0051] Optionally, the first oxide layer 211 is formed on the surface of the semiconductor substrate 100 between two adjacent well regions 130, including forming by a method including a thermal oxidation process, etc. After the first oxide layer 211 is formed, an opening exposing the surface of the semiconductor substrate 100 is etched on the first oxide layer 211 by a process such as exposure and etching, and the vertical projection position of the opening on the semiconductor substrate 100 needs to overlap the surface of the partial JFET region 150. That is, the opening position of the opening on the first oxide layer 211 needs to at least expose the surface of the JFET region 150 to provide a channel for the subsequent Schottky contact between the first metal layer 240 and the surface of the JFET region 150.

[0052] Step S22, forming a first metal layer 240.

[0053] Optionally, the first metal layer 240 is formed on the first oxide layer 211 and fills the first opening to directly contact the surface of the semiconductor substrate 100 of the JFET region 150, thereby forming a Schottky diode.

[0054] Step S23, forming a second oxide layer 212.

[0055] Optionally, the second oxide layer 212 is formed on the first oxide layer 211 by a method including vapor deposition, and the second oxide layer 212 at least covers the first metal layer 240 filled in the first opening, and the polysilicon layer 220 is formed on the second oxide layer 212. That is, the second oxide layer 212 functions to separate the polysilicon layer 220 and the first metal layer 240 by the second oxide layer. Therefore, the thickness of the second oxide layer 212 needs to be greater than that of the first oxide layer 211 to avoid the risk of short circuit between the polysilicon layer 220 and the first metal layer 240.

[0056] As an example, the forming step of the first metal layer 240 specifically includes:

[0057] Step S221, forming a metal layer on the first oxide layer 211, the metal layer covering the surface of the first oxide layer 211 and filling the first opening.

[0058] Optionally, the metal layer is a single-layer structure of a nickel layer, a titanium layer or a molybdenum layer formed by a magnetron sputtering method. For example, in the embodiment, the metal layer formed by sputtering is a Ti metal layer.

[0059] Step S222, Schottky annealing the metal layer filled in the first opening to form a Schottky contact between the metal layer in the first opening and the surface of the semiconductor substrate 100 of the JFET region 150.

[0060] Step S223, the metal layer on the surface of the first oxide layer 211 is removed by etching to form a patterned first metal layer 240.

[0061] Optionally, referring to Figure 5 , the metal layer on the surface of the first oxide layer 211 is removed by etching to form a patterned first metal layer 240.

[0062] Optionally, the first metal layer 240 further includes an extended lead end portion for maintaining electrical connection with the source metal electrode in subsequent process steps.

[0063] Finally, step S3 is performed, referring to Figure 6 , a second metal layer 300 is formed on the surface of the well region 130 on both sides of the gate structure 200, and the second metal layer 300 is in contact with the surface of part of the well region 130 and the active region 140.

[0064] It should be noted that the gate insulating layer 230 is on the polysilicon layer 220 and covers and extends to the semiconductor substrate 100 beyond the polysilicon layer 220, so that the step of forming the second metal layer 300 on the semiconductor substrate 100 includes:

[0065] Step S31, etching a second opening on the gate insulating layer 230 to expose part of the well region 130 and the second active region 140.

[0066] Step S32, depositing a second metal layer 300 in the second opening, and the second metal layer 300 forms ohmic contact with the contact surface of the well region 130 and the second active region 140.

[0067] As an example, after the second opening is formed, a process of further opening at the sidewall of the second opening is included, etching the gate insulating layer in a direction perpendicular to the sidewall of the second opening until part of the lead end portion of the first metal layer 240 is exposed, so that the second metal layer 300 is electrically connected with the first metal layer 240.

[0068] As an example, the method of manufacturing the semiconductor device structure further includes the steps of forming a plurality of lead electrodes and a third metal layer, the plurality of lead electrodes are respectively electrically connected with the second metal layer 300 and the polysilicon layer 220, and the third metal layer is on the surface of the semiconductor substrate 100 away from the second metal layer 300.

[0069] In a second aspect, the application also provides a semiconductor device structure manufactured by the method of manufacturing the semiconductor device structure described in any of the above embodiments.

[0070] Referring toFigure 6 The first metal layer 240 is arranged on the JFET region 150, and forms a Schottky junction with the surface of the JFET region 150 at the first opening, while the well region 130 and the epitaxial layer 120 form a PN junction. In a forward voltage, the opening voltage of the Schottky junction is lower than that of the PN junction, and the threshold voltage is only about 1V, that is, the Schottky diode will be turned on before the PN diode, so that the semiconductor device structure exhibits the characteristics of the Schottky diode at a low forward conduction voltage, that is, the potential barrier on the semiconductor side is reduced, and the transmission of current in the device is dominated by the majority carriers (electrons) injected by the Schottky diode, and thus the Schottky diode has the characteristic of fast switching speed. As the forward bias increases, the PN diode is turned on, and the forward voltage drop of the semiconductor device structure is reduced.

[0071] Under a reverse voltage, the Schottky junction has the characteristics of short reverse recovery time and small influence on the switching speed of the device. In addition, when conducting in the reverse direction, the Schottky junction can shield the opening of the PN junction, and the depletion layer formed by the PN junction will expand along the channel to both sides until the connected conductive channel is pinched off, thereby forming a potential barrier in the channel region. The depletion layer will extend below the channel as the reverse voltage increases, and the increased reverse voltage will fall on the depletion layer, thereby shielding the Schottky junction from high electric fields, effectively suppressing the barrier lowering effect, thereby solving the problem of increased leakage current under high reverse voltage.

[0072] At the same time, the Schottky diode is arranged directly below the gate structure 200, which is equivalent to integrating a Schottky diode in the cell. Compared with the prior art of integrating a Schottky diode outside the cell, the width between cells is further reduced, and the forward conduction resistance of the device is reduced.

[0073] In summary, the application provides a semiconductor device structure and a preparation method thereof, which comprises providing a semiconductor substrate 100 and a well region 130 and an active region 140 formed in the semiconductor substrate 100; then forming a gate structure 200 on the semiconductor substrate 100 between the adjacent well regions 130, the gate structure 200 comprising a gate isolation layer 210, a polysilicon layer 220 and a gate insulation layer 230, wherein the gate isolation layer 210 further comprises a first metal layer 240 forming a Schottky contact with the surface of the semiconductor substrate 100; and finally forming a second metal layer 300 on the surface of the well region 130 on both sides of the gate structure 200. The application introduces the first metal layer 240 in the gate isolation layer 210 on the basis of the gate structure 200, and forms a Schottky contact between the first metal layer 240 and the surface of the semiconductor substrate 100 between the well regions 130, thereby reducing the forward opening voltage drop and the reverse recovery time of the semiconductor device structure, and limiting the generation of reverse leakage current. At the same time, compared with the prior art of integrating a Schottky diode outside the cell, the application integrates the Schottky diode in the cell, thereby reducing the width between the cells and avoiding the problem of increasing the forward conduction resistance of the device caused by the increase of the cell size, and further improving the performance of the device.

[0074] The above only describes the preferred embodiments of the application, and it should be pointed out that those skilled in the art can make several improvements and replacements without departing from the technical principles of the application, and these improvements and replacements should also be considered as the protection scope of the application.

Claims

1. A method for fabricating a semiconductor device structure, characterized in that, include: A semiconductor substrate is provided, in which a plurality of well regions of a first conductivity type are formed at intervals, and an active region of a second conductivity type is located within the well regions; A gate structure is formed on the semiconductor substrate between adjacent well regions. The gate structure includes a gate isolation layer, a polysilicon layer, and a gate insulating layer stacked sequentially. The gate insulating layer covers the polysilicon layer and extends to the semiconductor substrate outside the polysilicon layer. The gate isolation layer contains a first metal layer that makes a Schottky contact with the surface of the semiconductor substrate, and the first metal layer does not contact the polysilicon layer. The step of forming a second metal layer on the surface of the well region on both sides of the gate structure and electrically connecting the second metal layer to the first metal layer includes: A second opening is etched into the gate insulating layer, the second opening exposing at least a portion of the well region and the second active region; A second metal layer is formed within the second opening, and the second metal layer forms an ohmic contact with the contact surface of the well region and the active region; the etching range of the second opening at least covers a portion of the gate isolation layer, and the second metal layer is electrically connected to the first metal layer at the sidewall of the second opening.

2. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, The steps for forming the gate isolation layer include: A first oxide layer is formed on the surface of the semiconductor substrate between the well regions, and a first opening is etched on the first oxide layer to expose the surface of the semiconductor substrate. A first metal layer is formed on the first oxide layer, and the first metal layer filling the first opening forms a Schottky contact with the surface of the semiconductor substrate; A second oxide layer is formed on the first oxide layer, the second oxide layer at least covering the first opening.

3. The method for fabricating a semiconductor device structure according to claim 2, characterized in that, The steps for forming the first metal layer include: A metal layer is sputtered onto the first oxide layer, the metal layer covering the surface of the first oxide layer and filling the first opening; The metal layer filled in the first opening is subjected to Schottky annealing to form a Schottky contact with the surface of the semiconductor substrate; The metal layer located on the surface of the first oxide layer is etched away to form a patterned first metal layer.

4. The method for fabricating a semiconductor device structure according to any one of claims 2 to 3, characterized in that, The first oxide layer is formed using a thermal oxidation process, and the first opening exposes at least a portion of the upper surface of the semiconductor substrate located between adjacent well regions.

5. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, The semiconductor substrate includes a substrate layer of a second conductivity type and an epitaxial layer, wherein the doping concentration of ions of the second conductivity type in the epitaxial layer is lower than that in the substrate layer; the substrate layer is made of 4H-SiC.

6. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, The first metal layer is a single-layer structure of nickel, titanium, or molybdenum.

7. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, It also includes the steps of forming a plurality of lead-out electrodes and a third metal layer, wherein the plurality of lead-out electrodes are electrically connected to the second metal layer and the polysilicon layer respectively; the third metal layer is located on the surface of the semiconductor substrate opposite to the gate structure.

8. A semiconductor device structure, characterized in that, It includes the semiconductor device structure fabrication method described in any one of claims 1 to 7.

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