A multi-grid composite dielectric grating photosensitive detector and working method

Abstract

The present invention discloses a multi-gate composite dielectric grating photosensitive detector and a working method. The photosensitive detector includes a photosensitive transistor and a reading transistor formed on the same substrate. The photosensitive transistor and the reading transistor share a composite dielectric gate. The composite dielectric gate includes a first bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate. The reading transistor is provided with a source terminal and a drain terminal. The substrate of the reading transistor is also provided with a second bottom dielectric layer and a selection gate in sequence. The second bottom dielectric layer and the selection gate are two independent parts from the composite dielectric gate. The readout method of the photosensitive detector of the present invention includes a method of reading current in a linear region or a method of reading voltage by source following. The composite dielectric grating photosensitive detector based on a multi-gate structure of the present invention provides a traditional composite dielectric grating photosensitive detector with a choice of noise reduction and multiple readout methods and working modes, and provides more choices and functions for the composite dielectric grating photosensitive detector in imaging applications.

Description

Technical Field

[0001] The invention relates to a novel photosensitive detector structure, in particular to a multi-grid composite dielectric grating photosensitive detector, and provides a variety of working methods for the composite dielectric grating photosensitive detector. Background Art

[0002] As a photoelectric signal converter, photodetectors can effectively convert light signals into electrical signals and further display images. They are widely used in daily life, security, national defense, etc. Currently, the mainstream photodetectors are divided into two categories: CCD and CMOS-APS, and each has its own advantages in different fields.

[0003] Due to its own structure, the photodetector based on composite dielectric grating has the advantages of combining CCD and CMOS-APS photodetectors, and is expected to become the mainstream photodetector of the new generation. However, the reading transistor of a typical photodetector based on composite dielectric grating generally has only one gate, which greatly limits the working mode of the photodetector. This detector usually uses a sweeping ramp voltage for reading, which is difficult in circuit design and functional application. Summary of the invention

[0004] In view of the defects existing in the prior art, the present invention improves the structure of the photosensitive detector based on the composite dielectric grating, and changes it into a multi-gate structure, which can provide more working methods for the detector.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A multi-gate composite dielectric gate photosensitive detector includes a photosensitive transistor and a read transistor formed on the same substrate, wherein the photosensitive transistor and the read transistor share a composite dielectric gate, wherein the composite dielectric gate includes a first bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate, and the read transistor is provided with a source terminal and a drain terminal. It is characterized in that a second bottom dielectric layer and a select gate are sequentially provided on the substrate of the read transistor, and the second bottom dielectric layer and the select gate are two independent parts from the composite dielectric gate.

[0007] The present invention discloses another multi-gate composite dielectric gate photosensitive detector, wherein the photosensitive transistor comprises a first composite dielectric gate, and the reading transistor comprises a second composite dielectric gate, a source terminal and a drain terminal, and is characterized in that the first composite dielectric gate and the second composite dielectric gate share a bottom dielectric layer, a charge coupling layer and a top dielectric layer, the top of the first composite dielectric gate is a control gate, the top of the second composite dielectric gate is a selection gate, the bottom dielectric layer and the selection gate of the second composite dielectric gate form a semi-enclosed structure for the charge coupling layer and the top dielectric layer; the selection gate and the control gate are two independent parts.

[0008] The present invention provides a working method of the above-mentioned multi-grating composite dielectric grating photosensitive detector, comprising the following steps:

[0009] (1) Reset: applying a negative voltage to the control gate, grounding the substrate, and resetting the electrons collected by the photosensitive transistor of the photosensitive detector;

[0010] (2) Exposure: A positive voltage is applied to the control gate, and the substrate is grounded or negatively voltageed. When light is applied, when the energy of the photoelectron is greater than the bandgap width of the substrate, an electron-hole pair will be excited. Under the action of the electric field in the depletion region, the photosensitive transistor collects the generated photoelectrons. The potential of the photosensitive transistor will change and couple to the charge coupling layer of the composite dielectric gate to change the potential of the charge coupling layer, thereby controlling the read transistor.

[0011] (3) Reading: During the reading phase, a positive voltage is applied to the control gate, a negative voltage is applied to the substrate or the substrate is grounded, a positive voltage is applied to the drain terminal so that the read transistor operates in a linear region or a saturation region, the source terminal is grounded or connected to a current source, and a positive voltage is applied to the select gate so that the read transistor is turned on to read the drain current or the source voltage.

[0012] Furthermore, in the readout stage of step (3), high voltage is applied to both the selection gate and the control gate, and the voltage should be higher than the threshold voltage of the reading transistor when the photosensitive detector is in the full-well state, so that the reading transistor is in the on state, and a low voltage is applied to the drain end, and the source end is grounded. The voltage applied to the drain end should make the reading transistor work in the linear region when the photosensitive detector is in the full-well state. At this time, the photoelectrons collected by the photosensitive transistor are coupled to the charge coupling layer of the composite dielectric gate, changing its potential, and regulating the drain current of the reading transistor, thereby further realizing the quantization of the light signal.

[0013] Furthermore, an imaging chip is composed of a plurality of the composite dielectric grating photosensitive detectors, and the imaging chip has a plurality of working mode options: (a) normal working mode: the control gate is connected to positive high voltage and the substrate is grounded; (b) high dynamic range mode: the control gate of the photosensitive detector is connected to positive high voltage and the substrate is connected to negative high voltage, so that the depletion region of the photosensitive transistor is expanded, thereby obtaining a larger full well capacity; (c) extremely high dynamic range mode: the control gate of the photosensitive detector is connected to positive high voltage and the substrate is connected to negative high voltage, and a plurality of photosensitive detectors are combined, at which time the full well capacity is further expanded, and high frame rate readout is performed.

[0014] Furthermore, in the readout stage of step (3), high voltage is applied to both the selection gate and the control gate, and the voltage should be higher than the threshold voltage of the reading transistor when the photosensitive detector is in the full well state, so that the reading transistor is in the on state, the substrate is grounded, the drain terminal is applied with high voltage, and the source terminal is connected to a current source. The voltage applied to the drain terminal should make the reading transistor work in the saturation region when the photosensitive detector is in the empty well state, so that the reading transistor works in the source follower mode. At this time, the photoelectrons collected by the photosensitive transistor are coupled to the charge coupling layer of the composite dielectric gate, changing its potential, and regulating the source terminal voltage of the reading transistor, thereby further realizing the quantization of the light signal.

[0015] The detector of the present invention provides a variety of reading mode options for the photosensitive detector at the device level, and because the multi-gate structure increases the channel length of the reading transistor, the gate oxide area is increased, which is beneficial to reduce 1 / f noise and RTN noise. The present invention uses a multi-gate structure, and because the device is additionally controlled by the selection gate, when the selection gate of the device is closed and the control gate is applied with high voltage, the reading transistor will not be turned on, thus providing noise reduction and multiple readout modes and working modes for the traditional composite dielectric gate photosensitive detector, and providing more options and functions for this type of photosensitive detector in imaging applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of the multi-gate composite dielectric grating photosensitive detector in Example 1;

[0017] Figure 2 for Figure 1 Schematic diagram of the structure of the AA' section of the composite dielectric grating photosensitive detector with medium multi-gate;

[0018] Figure 3 for Figure 1 Schematic diagram of the structure of the cross section of the composite dielectric grating photosensitive detector BB' of the medium multi-gate;

[0019] Figure 4 for Figure 1 Schematic diagram of the cross section of the composite dielectric grating photosensitive detector CC' of the medium multi-gate;

[0020] Figure 5 for Figure 4 Schematic diagram of energy bands at different working states at the gate oxide interface of the middle reading transistor DD' cross section;

[0021] Figure 6 The schematic diagram of a readout method of a photosensitive detector;

[0022] Figure 7 A schematic diagram of another readout method of a photosensitive detector;

[0023] Figure 8A schematic diagram of the layout design of a multi-gate composite dielectric grating photosensitive detector;

[0024] Fig. 9 Schematic diagram of the structure of the multi-gate composite dielectric grating photosensitive detector in Example 2;

[0025] Fig.10 for Fig. 9 Schematic diagram of the structure of the cross section of the composite dielectric grating photosensitive detector EE' of the medium multi-gate;

[0026] Fig.11 for Fig. 9 Schematic diagram of the structure of the cross section of the composite dielectric grating photosensitive detector FF' of the medium multi-gate;

[0027] Fig.12 for Fig. 9 Schematic diagram of the cross-section structure of the composite dielectric grating photosensitive detector GG' with medium multi-gate. DETAILED DESCRIPTION

[0028] Example 1

[0029] This embodiment uses Figure 1 The structure of the multi-gate composite dielectric gate photosensitive detector shown is as follows: it includes a photosensitive transistor 101 and a read transistor 102 formed on the same P-type semiconductor substrate, the photosensitive transistor 101 and the read transistor 102 are separated by a shallow trench isolation 103, and the photosensitive transistor 101 and the read transistor 102 share a composite dielectric gate, wherein the composite dielectric gate includes a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107 from bottom to top, and the top control gate 107 controls the read transistor 102 and the photosensitive transistor 101 together. In addition, the read transistor 102 is additionally controlled by a select gate 109, and below the select gate 109 is a second bottom dielectric layer 108, and the read transistor 102 also includes two ports, a source terminal 110 and a drain terminal 111. The photosensitive transistor 101 is used to sense light and convert light signals into electrical signals, and the reading transistor 102 is used to read the electrical signals. The reading transistor 102 is controlled by two gates, the selection gate 109 and the control gate 107, so that the overall channel length of the reading transistor 102 is longer than the channel length controlled by only one gate, reducing the noise of the reading transistor and allowing multiple reading methods.

[0030] for Figure 1 The AA' section in Figure 2As shown, its structure is as follows: it includes a photosensitive transistor 101 and a read transistor 102 formed on the same P-type semiconductor substrate, the photosensitive transistor 101 and the read transistor 102 are separated by a shallow trench isolation 103, and the photosensitive transistor 101 is controlled by a composite dielectric gate, wherein the composite dielectric gate includes a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107 from bottom to top, and in addition, the read transistor 102 is controlled by a select gate 109, and below the select gate 109 is a second bottom dielectric layer 108. In this cross section, the read transistor 102 will not be affected by the charge coupling layer 105, so in this cross section, the light signal collected by the photosensitive transistor 101 will not affect the read transistor 102.

[0031] for Figure 1 The BB' section in Figure 3 As shown, its structure is as follows: it includes a photosensitive transistor 101 and a read transistor 102 formed on the same P-type semiconductor substrate, the photosensitive transistor 101 and the read transistor 102 are separated by a shallow trench isolation 103, and the photosensitive transistor 101 and the read transistor 102 are controlled by a composite dielectric gate at the same time, wherein the composite dielectric gate includes, from bottom to top, a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107. In this cross section, the read transistor 102 will be affected by the charge coupling layer 105, so in this cross section, the light signal collected by the photosensitive transistor 101 will change the drain current or source voltage of the read transistor 102, thereby realizing photoelectric conversion in the readout process.

[0032] for Figure 1 The CC' section in Figure 4 As shown, the structure is as follows: it includes a read transistor 102 formed on a P-type semiconductor substrate, and the read transistor 102 is controlled by a control gate 107 and a select gate 109 at the same time, wherein the select gate 109 is under a second bottom dielectric layer 108, and the composite dielectric gate as a whole is composed of a first bottom dielectric layer 104, a charge coupling layer 105, a top dielectric layer 106 and a control gate 107. In this cross section, the read transistor 102 is affected by the select gate 109 and the charge coupling layer 105, so in this cross section, the working state of the read transistor 102 is jointly determined by the voltage of the select gate 109, the potential of the charge coupling layer 105 and the substrate voltage, wherein the potential of the charge coupling layer 105 is determined by the number of photoelectrons collected by the photosensitive transistor 101, the voltage of the control gate 107 and the substrate voltage.

[0033] The switching state of the read transistor 102 is jointly affected by the select gate 109 and the charge coupling layer 105. The energy band diagram of the channel cross section DD' is shown as follows: Figure 5 As shown: Figure 5Figure (a) shows the state when the select gate 109 is closed. At this time, when the electrons flow from the source to the drain, they encounter a higher potential barrier under the select gate, which blocks the flow of electrons, thereby turning off the read transistor 102. Figure 5 Figure (b) shows the state when the select gate 109 is turned on. At this time, an inversion layer is formed on the channel surface under the select gate, the potential barrier disappears, and electrons can flow from the source end to the drain end, thereby turning on the read transistor 102. The high voltage signal of the select gate 109 can ensure that the read transistor 102 is fully turned on, and the source-drain current or source-end voltage of the read transistor is determined by the charge coupling layer 105 and satisfies the square law relationship of MOSFET.

[0034] This embodiment can use Figure 6 The schematic diagram of the readout method shown in the figure is used to read out the optical signal. The control gate CG is added with a voltage of 3.3V (the specific working voltage is determined by the circuit design, which is generally the power supply voltage), the substrate Vb is added with a voltage of 0V or -3V (the specific working voltage is determined by the circuit design, which is generally grounded, and connecting a negative high voltage can expand the full well capacity), the drain voltage Vd is added with 0.2V (the specific working voltage is determined by the circuit design, and the read transistor needs to work in the linear region), the source voltage Vs is added with 0V (the specific working voltage is determined by the circuit design, which is generally grounded), the select gate MG is given a high voltage signal to turn on the read transistor, and the column readout circuit Column is connected to the control gate CG. The source-drain current is read on the Bus; in this readout mode, the imaging chip can have multiple working modes to choose from: 1. Normal working mode: the control gate CG is connected to a positive high voltage (generally higher than 3V, the higher the voltage, the larger the full well), and the substrate Vb is grounded. At this time, the full well of the device is small and the dynamic range is small, which is suitable for use in an environment without strong light; 2. High dynamic range mode: the control gate CG of the photosensitive detector is connected to a positive high voltage, and the substrate Vb is connected to a negative high voltage, so that the depletion region of the photosensitive transistor is expanded, thereby obtaining a larger full well capacity, thereby improving the dynamic range and peak signal-to-noise ratio of the device, which is suitable for use in a long exposure or strong light environment; 3. Ultra-high dynamic range mode: the control gate CG of the photosensitive detector is connected to a positive high voltage, and the substrate Vb is connected to a negative high voltage, and multiple pixels are merged (the specific number of pixels is determined by the layout design, typically 4 pixels are merged into 1 pixel). At this time, the full well capacity is further expanded, which can further improve the dynamic range and peak signal-to-noise ratio of the device, and because the merging will reduce the resolution of the imaging chip, high frame rate readout can be performed, which is suitable for use in a long exposure or strong light environment.

[0035] This embodiment can use Figure 7The schematic diagram of the readout method shown in the figure is used to read out the light signal. The control gate CG is added with a voltage of 3.3V (the specific working voltage is determined by the circuit design, generally the power supply voltage), the substrate is added with a voltage of 0V (the specific working voltage is determined by the circuit design, generally grounded), the drain voltage is added with 3.3V (the specific working voltage is determined by the circuit design, and the reading transistor needs to work in the saturation region), the source terminal is connected to the current source to form a source follower structure, the selection gate MG is given a high voltage signal to turn on the reading transistor, and the source terminal voltage is read on the column reading circuit Column Bus. When the photosensitive detector uses this readout method, its advantage is that since the drain terminal needs to be connected to a positive high voltage, in order to avoid avalanche of the PN junction between the drain and the substrate, the substrate generally needs to be grounded so that the reverse bias voltage of the PN junction is small enough. At this time, since the source terminal of the reading transistor is connected with a current source to form a source follower mode, the readout circuit directly reads the source terminal voltage of the photosensitive detector reading transistor 102, which can directly reflect the light signal collected by the photosensitive transistor. This readout method will improve the reading speed of the entire device and is suitable for application in high frame rate mode.

[0036] This embodiment can use Figure 8 The layout shown in the figure realizes the mode of multiple devices sharing the readout circuit, and realizes the switching of different resolutions, dynamic ranges and frame rates through timing control. If every two columns of pixels share a column of readout circuit, and every two rows are reset, exposed and read at the same time, 2×2 merging can be realized; if every four columns of pixels share a column of readout circuit, and every four rows are reset, exposed and read at the same time, 4×4 merging can be realized; if only each row is reset, exposed and read separately, full sampling can be realized to achieve the maximum resolution.

[0037] Example 2

[0038] For a multi-gate composite dielectric gate photosensitive detector pixel with a typical size of less than 0.5um, it is difficult to manufacture two separate gates in parallel above the read transistor due to the limitation of process rules at a 65nm or 50nm process node. In view of this process limitation, this embodiment can utilize the following method: Fig. 9The multi-gate photosensitive detector structure shown in the figure includes a photosensitive transistor 901 and a read transistor 902 formed on the same substrate, the photosensitive transistor 901 and the read transistor 902 are separated by a shallow trench isolation 903, the photosensitive transistor 901 and the read transistor 902 share a bottom dielectric layer 904, a charge coupling layer 905, and a top dielectric layer 906, the top dielectric layer 906 of the photosensitive transistor 901 is provided with a control gate 907, the top dielectric layer 906 of the read transistor 902 is provided with a select gate 908 on the bottom dielectric layer 904, and the other parts are provided with a charge coupling layer 905, a top dielectric layer 906, and a select gate 908 in sequence, the control gate 907 and the select gate 908 are two independent parts, and the read transistor 902 also includes two ports, a source terminal 909 and a drain terminal 910.

[0039] for Fig. 9 The EE' section in Fig.10 As shown, its structure is as follows: it includes a photosensitive transistor 901 and a read transistor 902 formed on the same P-type semiconductor substrate, the photosensitive transistor 901 and the read transistor 902 are separated by a shallow trench isolation 903, and both the photosensitive transistor 901 and the read transistor 902 are controlled by a composite dielectric gate, wherein the composite dielectric gate includes a bottom dielectric layer 904, a charge coupling layer 905, a top dielectric layer 906, a control gate 907 and a select gate 908 from bottom to top, wherein the control gate 907 is above the photosensitive transistor 901, and the select gate 908 is above the read transistor 902. In this cross section, the potential of the charge coupling layer 905 is determined by the number of photoelectrons collected by the photosensitive transistor 901, the voltage of the control gate 907, the voltage of the select gate 908 and the substrate voltage.

[0040] for Fig. 9 The FF' section in Fig.11 As shown, its structure is as follows: it includes a photosensitive transistor 901 and a read transistor 902 formed on the same P-type semiconductor substrate, the photosensitive transistor 901 and the read transistor 902 are separated by a shallow trench isolation 903, and the photosensitive transistor 901 is controlled by a composite dielectric gate, wherein the composite dielectric gate includes a bottom dielectric layer 904, a charge coupling layer 905, a top dielectric layer 906 and a control gate 907 from bottom to top, and in addition, the top of the read transistor 902 is only controlled by a select gate 908. In this cross section, the read transistor 902 will not be affected by the charge coupling layer 905, so in this cross section, the light signal collected by the photosensitive transistor 901 will not affect the read transistor 902.

[0041] for Fig. 9 The GG' section in Fig.12As shown, the structure is as follows: it includes a read transistor 902 formed on a P-type semiconductor substrate, wherein a select gate 908 on a bottom dielectric layer 904 forms a semi-enclosed structure for a charge coupling layer 905 and a top dielectric layer 906. The read transistor 902 is controlled by the potential of the charge coupling layer 905 and the potential of the select gate 908, wherein the potential of the charge coupling layer 905 is determined by the number of photoelectrons collected by the photosensitive transistor 901, the voltage of the control gate 907, the voltage of the select gate 908, and the substrate voltage.

Claims

1. A multi-gate composite dielectric gate photosensitive detector, comprising a photosensitive transistor and a read transistor formed on the same substrate, wherein the photosensitive transistor and the read transistor share a composite dielectric gate, wherein the composite dielectric gate comprises a first bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate, wherein the read transistor is provided with a source terminal and a drain terminal, wherein: A second bottom dielectric layer and a selection gate are sequentially arranged on the substrate of the read transistor. The second bottom dielectric layer and the selection gate are two independent parts from the composite dielectric gate.

2. The operating method of a multi-gate composite dielectric grating photosensitive detector according to claim 1, characterized in that: The working method comprises the following steps: (1) Reset: applying a negative voltage to the control gate, grounding the substrate, and resetting the electrons collected by the photosensitive transistor of the photosensitive detector; (2) Exposure: A positive voltage is applied to the control gate, and the substrate is grounded or negatively voltageed. When light is applied, when the energy of the photoelectron is greater than the bandgap width of the substrate, an electron-hole pair will be excited. Under the action of the electric field in the depletion region, the photosensitive transistor collects the generated photoelectrons. The potential of the photosensitive transistor will change and couple to the charge coupling layer of the composite dielectric gate to change the potential of the charge coupling layer, thereby controlling the read transistor. (3) Reading: During the reading phase, a positive voltage is applied to the control gate, a negative voltage is applied to the substrate or the substrate is grounded, a positive voltage is applied to the drain terminal so that the read transistor operates in a linear region or a saturation region, the source terminal is grounded or connected to a current source, and a positive voltage is applied to the select gate so that the read transistor is turned on to read the drain current or the source voltage.

3. The working method according to claim 2, characterized in that: In the readout stage of step (3), high voltage is applied to both the selection gate and the control gate, and the voltage should be higher than the threshold voltage of the reading transistor when the photosensitive detector is in the full-well state, so that the reading transistor is in the on state, and a low voltage is applied to the drain end, and the source end is grounded. The voltage applied to the drain end should make the reading transistor work in the linear region when the photosensitive detector is in the full-well state. At this time, the photoelectrons collected by the photosensitive transistor are coupled to the charge coupling layer of the composite dielectric gate, changing its potential, and regulating the drain current of the reading transistor, thereby further realizing the quantization of the light signal.

4. The working method according to claim 3, characterized in that: An imaging chip is composed of a plurality of the composite dielectric grating photosensitive detectors, and the imaging chip has a plurality of working mode options: (a) normal working mode: the control gate is connected to a positive high voltage and the substrate is grounded; (b) high dynamic range mode: the control gate of the photosensitive detector is connected to a positive high voltage and the substrate is connected to a negative high voltage, so that the depletion region of the photosensitive transistor is expanded, thereby obtaining a larger full well capacity; (c) extremely high dynamic range mode: the control gate of the photosensitive detector is connected to a positive high voltage and the substrate is connected to a negative high voltage, and a plurality of photosensitive detectors are combined, at which time the full well capacity is further expanded, and high frame rate readout is performed.

5. The working method according to claim 2, characterized in that: In the readout stage of step (3), high voltage is applied to both the selection gate and the control gate, and the voltage should be higher than the threshold voltage of the reading transistor when the photosensitive detector is in the full well state, so that the reading transistor is in the on state, the substrate is grounded, the drain terminal is applied with high voltage, and the source terminal is connected to a current source. The voltage applied to the drain terminal should make the reading transistor work in the saturation region when the photosensitive detector is in the empty well state, so that the reading transistor works in the source follower mode. At this time, the photoelectrons collected by the photosensitive transistor are coupled to the charge coupling layer of the composite dielectric gate, changing its potential, and regulating the source terminal voltage of the reading transistor, thereby further realizing the quantization of the light signal.

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