Current detection circuit and dc-dc step-down converter

Abstract

The application discloses a current detection circuit and a DC-DC step-down converter. The current detection circuit comprises: a bias current unit for generating a first bias current and delivering the first bias current to a connection node of a main power tube and a secondary power tube of the DC-DC step-down converter; a first starting unit for improving the establishment speed of the bias current unit; and a comparator for comparing the voltage of the connection node with a ground voltage and outputting a control signal to the gate of the secondary power tube. According to the current detection circuit and the DC-DC step-down converter, the bias current unit is quickly established by the first starting unit, and the comparator is quickly established by the second starting unit, so that the detection circuit can operate more efficiently. The circuit structure of the first starting unit and the second starting unit is simple, the performance of the circuit is greatly improved under the condition of small occupied area, and the cost of the chip is negligible.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a current detection circuit and a DC-DC step-down converter. Background Art

[0002] As a type of DC-DC converter, efficiency is an important indicator of performance. In terms of energy loss in the BUCK circuit, a major issue is the return loss of the secondary power transistor. Figure 1 As shown, under light load conditions, when the inductor current of the secondary power transistor M2 drops to zero, the current in the output capacitor will flow back to ground through the inductor and the secondary power transistor M2, resulting in low efficiency. At this time, current zero-crossing detection is performed on the connection node SW. The general approach is: when the secondary power transistor M2 is turned on, the voltage at the connection node SW gradually increases from a negative voltage to 0V. When the voltage at the connection node SW exceeds 0V, the secondary power transistor M2 is turned off. A common current zero-crossing detection method is to pass a bias current through a resistor and then input it to the connection node SW. At this time, the secondary power transistor M2 is turned off by comparing the voltage at the connection node SW with the ground voltage. Therefore, the accuracy and speed of detection are particularly important for improving efficiency.

[0003] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0004] An object of the present invention is to provide a current detection circuit and a DC-DC buck converter, which can improve the response speed of a bias current unit and a comparator, thereby improving the efficiency of the entire system and improving the ability to suppress ground noise.

[0005] To achieve the above objectives, an embodiment of the present invention provides a current detection circuit for a DC-DC buck converter. The DC-DC buck converter includes a primary power tube and a secondary power tube. The source of the primary power tube and the drain of the secondary power tube are connected to form a connection node SW. The drain of the primary power tube is used to receive a power supply voltage, the source of the secondary power tube is connected to a ground voltage, and the gates of the primary power tube and the secondary power tube are used to receive a control signal. The current detection circuit includes: a bias current unit, a first startup unit, and a comparator.

[0006] The bias current unit is used to generate a first bias current and transmit the first bias current to the connection node SW, and the bias current unit includes a first current mirror, a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MP4, a first resistor R1, and a second resistor R2;

[0007] The gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MP3, the sources of the first MOS transistor MP1 and the third MOS transistor MP3 are connected to the power supply voltage AVDD, the gate of the second MOS transistor MP2 is connected to the gate of the fourth MOS transistor MP4, the source of the second MOS transistor MP2 is connected to the drain of the first MOS transistor MP1, and the source of the fourth MOS transistor MP4 is connected to the drain of the third MOS transistor MP3. A first end of the first resistor R1 is connected to the drain of the second MOS transistor MP2 and the gate of the first MOS transistor MP1 to form a first node A1, a second end of the first resistor R1 is connected to a first current mirror and the gate of the second MOS transistor MP2 to form a second node A2, and the first current mirror is also used to receive an input current. A first end of the second resistor R2 is connected to the drain of the fourth MOS transistor MP4, and a second end of the second resistor R2 is connected to the connection node SW.

[0008] The first startup unit is connected to the first node A1 and the second node A2, and is used to increase the speed of establishing the voltage on the first node A1 and the second node A2;

[0009] The comparator is used for comparing the voltage of the connection node SW with the ground voltage and outputting a control signal to the gate of the secondary power transistor.

[0010] In one or more embodiments of the present invention, the first startup unit comprises a first capacitor, a fifteenth MOS transistor, and a twenty-fifth MOS transistor, wherein a first end of the first capacitor is connected to a power supply voltage, a second end of the first capacitor is connected to a drain of the twenty-fifth MOS transistor and a source of the fifteenth MOS transistor, the source of the twenty-fifth MOS transistor is connected to a ground voltage, the drain of the fifteenth MOS transistor is connected to a first node, and gates of the fifteenth MOS transistor and the twenty-fifth MOS transistor are configured to receive a second control signal.

[0011] In one or more embodiments of the present invention, the first startup unit further includes a fourteenth MOS transistor and a sixteenth MOS transistor, wherein the source of the fourteenth MOS transistor and the source of the sixteenth MOS transistor are connected to the power supply voltage, the drain of the fourteenth MOS transistor is connected to the second node, the drain of the sixteenth MOS transistor is connected to the first node, and the gate of the fourteenth MOS transistor and the gate of the sixteenth MOS transistor are used to receive the third control signal.

[0012] In one or more embodiments of the present invention, the bias current unit further includes a twentieth MOS transistor, wherein the drain of the twentieth MOS transistor is connected to the second node, the source of the twentieth MOS transistor is connected to the first current mirror, and the gate of the twentieth MOS transistor is used to receive the first control signal.

[0013] In one or more embodiments of the present invention, the comparator includes a second current mirror, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a third current mirror, a twenty-fourth MOS transistor, a third resistor, a fourth resistor, and a fifth resistor;

[0014] A first end of the third resistor is connected to the second current mirror, and a second end of the third resistor is connected to the ground voltage. The source of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and is also connected to the second current mirror. The gate of the tenth MOS transistor is connected to the connection node, and the gate of the eleventh MOS transistor is also connected to the ground voltage. A first end of the fourth resistor is connected to the drain of the tenth MOS transistor, and a second end of the fourth resistor is connected to the ground voltage. A first end of the fifth resistor is connected to the drain of the eleventh MOS transistor, and a second end of the fifth resistor is connected to the ground voltage. The source of the twelfth MOS transistor is connected to the source of the thirteenth MOS transistor and is also connected to the second current mirror. The gate of the twelfth MOS transistor is connected to the drain of the eleventh MOS transistor, the gate of the thirteenth MOS transistor is connected to the drain of the tenth MOS transistor, and the drains of the twelfth MOS transistor and the thirteenth MOS transistor are both connected to the third current mirror. The drain of the twenty-fourth MOS transistor is connected to the second current mirror, the gate of the twenty-fourth MOS transistor is connected to the drain of the thirteenth MOS transistor, and the source of the twenty-fourth MOS transistor is connected to the ground voltage.

[0015] In one or more embodiments of the present invention, the comparator further includes a twenty-first MOS transistor, a drain of the twenty-first MOS transistor being connected to the second end of the third resistor, a gate of the twenty-first MOS transistor being used to receive the first control signal, and a source of the twenty-first MOS transistor being connected to the ground voltage.

[0016] In one or more embodiments of the present invention, the current detection circuit further includes a second startup unit connected to the gates of the MOS transistors of the second current mirror, and the second startup unit is used to increase the settling speed of the comparator.

[0017] In one or more embodiments of the present invention, the second startup unit includes a second capacitor, a seventeenth MOS transistor, and a twenty-sixth MOS transistor. The first end of the second capacitor is connected to the power supply voltage, the source of the seventeenth MOS transistor and the drain of the twenty-sixth MOS transistor are connected to the second end of the second capacitor, the gate of the seventeenth MOS transistor and the gate of the twenty-sixth MOS transistor are used to receive the second control signal, the source of the twenty-sixth MOS transistor is connected to the ground voltage, and the drain of the seventeenth MOS transistor is connected to the gates of each MOS transistor of the second current mirror.

[0018] In one or more embodiments of the present invention, the comparator further includes a seventh MOS transistor, a source of the seventh MOS transistor being connected to the power supply voltage, a gate of the seventh MOS transistor being used to receive a third control voltage, and a drain of the seventh MOS transistor being connected to the gates of each MOS transistor of the second current mirror.

[0019] The invention also discloses a DC-DC step-down converter, comprising: the current detection circuit.

[0020] Compared to the prior art, the current detection circuit and DC-DC buck converter according to embodiments of the present invention rapidly establish a bias current unit through a first startup unit, and rapidly establish a comparator through a second startup unit, thereby enabling more efficient operation of the detection circuit. The simple circuit structure of the first and second startup units significantly improves circuit performance while occupying a small area, negligibly impacting chip cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a circuit diagram of a DC-DC converter in the prior art.

[0022] Figure 2 FIG. 4 is a circuit schematic diagram of a current detection circuit according to an embodiment of the present invention.

[0023] Figure 3 FIG. 4 is a circuit schematic diagram of a signal generating circuit according to an embodiment of the present invention.

[0024] Figure 4 4 is a first waveform diagram of each control signal and each node according to an embodiment of the present invention.

[0025] Figure 5 4 is a second waveform diagram of each control signal and each node according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0027] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0028] like Figure 1As shown, the DC-DC step-down converter includes a primary power transistor M1 and a secondary power transistor M2. The source of the primary power transistor M1 and the drain of the secondary power transistor M2 are connected to form a connection node SW. The drain of the primary power transistor M1 is used to receive the power supply voltage AVDD, and the source of the secondary power transistor M2 is connected to the ground voltage. The gate of the primary power transistor M1 is used to receive a control signal K1, and the gate of the secondary power transistor M2 is used to receive a control signal K2.

[0029] like Figure 2 As shown, a current detection circuit for a DC-DC buck converter includes: a bias current unit 10 , a first startup unit 20 , a comparator 30 and a second startup unit 40 .

[0030] The bias current unit 10 is used to generate a first bias current I1 and transmit the first bias current I1 to the node SW.

[0031] like Figure 2 As shown, the bias current unit 10 includes a first current mirror, a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MP4, a twentieth MOS transistor MN3, a first resistor R1 and a second resistor R2.

[0032] Specifically, the gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MP3, the sources of the first MOS transistor MP1 and the third MOS transistor MP3 are connected to the power supply voltage AVDD, the gate of the second MOS transistor MP2 is connected to the gate of the fourth MOS transistor MP4, the source of the second MOS transistor MP2 is connected to the drain of the first MOS transistor MP1, and the source of the fourth MOS transistor MP4 is connected to the drain of the third MOS transistor MP3. A first end of the first resistor R1 is connected to the drain of the second MOS transistor MP2 and the gate of the first MOS transistor MP1 to form a first node A1. A second end of the first resistor R1 is connected to the drain of the twentieth MOS transistor MN3 and the gate of the second MOS transistor MP2 to form a second node A2. The source of the twentieth MOS transistor MN3 is connected to a first current mirror, and the gate of the twentieth MOS transistor MN3 is configured to receive a first control signal s1. The first current mirror is also configured to receive an input current. A first end of the second resistor R2 is connected to the drain of the fourth MOS transistor MP4, and a second end of the second resistor R2 is connected to a connection node SW.

[0033] In addition, the first current mirror includes an eighteenth MOS transistor MN1 and a nineteenth MOS transistor MN2. The gate and drain of the eighteenth MOS transistor MN1 are connected and are also connected to a constant current source A to receive an input current I0. The gate of the eighteenth MOS transistor MN1 is connected to the gate of the nineteenth MOS transistor MN2, and the source of the eighteenth MOS transistor MN1 and the source of the nineteenth MOS transistor MN2 are connected to ground.

[0034] In this embodiment, the first startup unit 20 is connected to the first node A1 and the second node A2. The first startup unit 20 is used to increase the speed of establishing the voltages on the first node A1 and the second node A2.

[0035] like Figure 2 As shown, the first startup unit 20 includes a first capacitor C1, a fourteenth MOS transistor MP14, a fifteenth MOS transistor MP15, a sixteenth MOS transistor MP16 and a twenty-fifth MOS transistor MN8.

[0036] A first end of the first capacitor C1 is connected to the power supply voltage AVDD, and a second end of the first capacitor C1 is connected to the drain of the twenty-fifth MOS transistor MN8 and the source of the fifteenth MOS transistor MP15. The source of the twenty-fifth MOS transistor MN8 is connected to the ground voltage, and the drain of the fifteenth MOS transistor MP15 is connected to the first node A1. The gates of the fifteenth MOS transistor MP15 and the twenty-fifth MOS transistor MN8 are configured to receive the second control signal s2.

[0037] The source of the fourteenth MOS transistor MP14 and the source of the sixteenth MOS transistor MP16 are connected to the power supply voltage AVDD, the drain of the fourteenth MOS transistor MP14 is connected to the second node A2, the drain of the sixteenth MOS transistor MP16 is connected to the first node A1, and the gate of the fourteenth MOS transistor MP14 and the gate of the sixteenth MOS transistor MP16 are used to receive the third control signal s3.

[0038] In this embodiment, the comparator 30 is arranged to compare the voltage at the connection node SW with the ground voltage and output a control signal K2 to the gate of the secondary power transistor M2 .

[0039] like Figure 2 As shown, the comparator 30 includes a second current mirror, a seventh MOS transistor MP7, a tenth MOS transistor MP10, an eleventh MOS transistor MP11, a twelfth MOS transistor MP12, a thirteenth MOS transistor MP13, a third current mirror, a twenty-first MOS transistor MN4, a twenty-fourth MOS transistor MN7, a third resistor R3, a fourth resistor R4 and a fifth resistor R5.

[0040] The second current mirror is used to provide multiple bias currents to the comparator 30. The second current mirror includes multiple MOS transistors connected in common gate. Specifically, the second current mirror includes a fifth MOS transistor MP5, a sixth MOS transistor MP6, an eighth MOS transistor MP8, and a ninth MOS transistor MP9. The gate and drain of the fifth MOS transistor MP5 are connected, and the sources of the fifth MOS transistor MP5, the sixth MOS transistor MP6, the eighth MOS transistor MP8, and the ninth MOS transistor MP9 are connected and connected to the power supply voltage AVDD.

[0041] The first end of the third resistor R3 is connected with the drain of the fifth MOS transistor MP5, the second end of the third resistor R3 is connected with the drain of the twenty-first MOS transistor MN4, the gate of the twenty-first MOS transistor MN4 is used for receiving the first control signal s1, and the source of the twenty-first MOS transistor MN4 is connected with the ground voltage.

[0042] The source of the tenth MOS transistor MP10 and the source of the eleventh MOS transistor MP11 are connected with each other and connected with the drain of the sixth MOS transistor MP6 of the second current mirror, the gate of the tenth MOS transistor MP10 is connected with the connection node SW, and the gate of the eleventh MOS transistor MP11 is connected with the ground voltage. The first end of the fourth resistor R4 is connected with the drain of the tenth MOS transistor MP10, the second end of the fourth resistor R4 is connected with the ground voltage, the first end of the fifth resistor R5 is connected with the drain of the eleventh MOS transistor MP11, and the second end of the fifth resistor R5 is connected with the ground voltage.

[0043] The source of the twelfth MOS transistor MP12 and the source of the thirteenth MOS transistor MP13 are connected with each other and connected with the drain of the eighth MOS transistor MP8 of the second current mirror, the gate of the twelfth MOS transistor MP12 is connected with the drain of the eleventh MOS transistor MP11, the gate of the thirteenth MOS transistor MP13 is connected with the drain of the tenth MOS transistor MP10, and the drain of the twelfth MOS transistor MP12 and the drain of the thirteenth MOS transistor MP13 are connected with the third current mirror. The third current mirror comprises a twenty-second MOS transistor MN5 and a twenty-third MOS transistor MN6. The gate of the twenty-second MOS transistor MN5 and the gate of the twenty-third MOS transistor MN6 are connected with each other, the gate and the drain of the twenty-second MOS transistor MN5 are connected with each other and connected with the drain of the twelfth MOS transistor MP12, the drain of the twenty-third MOS transistor MN6 is connected with the gate of a twenty-fourth MOS transistor MN7 and the drain of the thirteenth MOS transistor MP13. The source of the twenty-second MOS transistor MN5 and the source of the twenty-third MOS transistor MN6 are connected with the ground voltage.

[0044] The drain of the twenty-fourth MOS transistor MN7 is connected with the drain of the ninth MOS transistor MP9 of the second current mirror, the gate of the twenty-fourth MOS transistor MN7 is connected with the drain of the thirteenth MOS transistor MP13, and the source of the twenty-fourth MOS transistor MN7 is connected with the ground voltage.

[0045] The source of the seventh MOS transistor MP7 is connected with the power voltage AVDD, the gate of the seventh MOS transistor MP7 is used for receiving the third control voltage s3, and the drain of the seventh MOS transistor MP7 is connected with the gates of the sixth MOS transistor MP6, the eighth MOS transistor MP8 and the ninth MOS transistor MP9 of the second current mirror.

[0046] In this embodiment, the second startup unit 40 is connected to the gate of each MOS transistor of the second current mirror. The second startup unit 40 is used to increase the settling speed of the second current mirror.

[0047] like Figure 2 As shown, the second startup unit 40 includes a second capacitor C2, a seventeenth MOS transistor MP17, and a twenty-sixth MOS transistor MN9. A first end of the second capacitor C2 is connected to the power supply voltage AVDD. The source of the seventeenth MOS transistor MP17 and the drain of the twenty-sixth MOS transistor MN9 are connected to the second end of the second capacitor C2. The gates of the seventeenth MOS transistor MP17 and the twenty-sixth MOS transistor MN9 are configured to receive a second control signal s2. The source of the twenty-sixth MOS transistor MN9 is connected to the ground voltage. The drain of the seventeenth MOS transistor MP17 is connected to the gates of the sixth MOS transistor MP6, the eighth MOS transistor MP8, and the ninth MOS transistor MP9 of the second current mirror to form a third node A3.

[0048] like Figure 3 As shown, the current detection circuit further includes a signal generating circuit 50. The signal generating circuit 50 includes a buffer 51 and an inverter 52. The buffer 51 is configured to receive the third control signal s3 and output a first control signal s1. The first control signal s1 is slightly delayed compared to the third control signal s3. The inverter 52 is configured to receive the first control signal s1 and output a second control signal s2 with a delay.

[0049] In this embodiment, the third control signal s3 is first turned to a high-level signal, and the fourteenth MOS transistor MP14, the sixteenth MOS transistor MP16, and the seventh MOS transistor MP7 are all turned off. At this time, the voltages of the first node A1, the second node A2, and the third node A3 are no longer controlled by the fourteenth MOS transistor MP14, the sixteenth MOS transistor MP16, and the seventh MOS transistor MP7, respectively, and are released.

[0050] Next, the first control signal s1 is turned over to a high-level signal, the twentieth MOS transistor MN3 and the twenty-first MOS transistor MN4 are both turned on, and the input bias voltage of the connection node SW and the bias voltage of the comparator 30 begin to build up.

[0051] Furthermore, because the second control signal s2 is initially a high-level signal, the twenty-fifth MOS transistor MN8 and the twenty-sixth MOS transistor MN9 are both turned on, and the first capacitor C1 and the second capacitor C2 store charge based on the power supply voltage AVDD and the ground voltage. After the first control signal s1 flips to a high-level signal, the voltages of the first node A1, the third node A3, and the second node A2 begin to slowly build up. When the second control signal s2 flips to a low-level signal, the fifteenth MOS transistor MP15 and the seventeenth MOS transistor MP17 are both turned on. The charge initially stored in the first capacitor C1 is equal to C1*AVDD, which is now fully released onto the first node A1. A path is quickly established between the power supply voltage AVDD, the first capacitor C1, and the first node A1, rapidly lowering the voltage on the first node A1 and causing the bias current unit 10 to rapidly generate the first bias current I1. After the first node A1 stabilizes, no current flows into the first capacitor C1, thus having no impact on normal operation. Similarly, the voltage at the third node A3 changes in the same manner as the voltage at the first node A1 , causing the second current mirror to quickly generate a bias current, thereby accelerating the settling of the comparator 30 .

[0052] The initial charge on the first capacitor C1 is C1*AVDD, and the charge on the first capacitor C1 after stabilization is C1*(AVDD-V A1 ), C1 is the capacitance value of the first capacitor C1, AVDD is the voltage value of the power supply voltage AVDD, V A1 is the voltage of the first node A1. The charge consumed by the first capacitor C1 is C1*V A1 The time it takes for the voltage on the first node A1 to be established is ΔT. By reasonably setting the sizes of the fifteenth MOS transistor MP15 and the first capacitor C1, we can obtain ΔI is the change in current across the first resistor R1. After the first node A1 and the second node A2 are quickly established, the first bias current I1 is established. When the secondary power transistor M2 turns on and backflow occurs, the voltage at the connection node SW is zero. Assuming the internal resistance of the secondary power transistor M2 is Ron, the current flowing from the ground voltage through the secondary power transistor M2 into the connection node SW is I. Based on the equation Ron*I=R2*I1, where R2 is the resistance value of the second resistor R2, the value of the current I flowing through the secondary power transistor M2 can be set to determine whether backflow occurs.

[0053] Combine Figure 4 and Figure 5It can be seen that, through the orderly optimized control logic of the first control signal s1, the second control signal s2 and the third control signal s3, the voltage establishment speed on the third node A3 and the first node A1 is within 10 ns, compared with the traditional detection circuit, the reaction speed will be improved by more than ten times, so that the bias current unit and the comparator can be quickly established, the sensitivity of detection is provided, the circuit can be more efficient, and the efficiency of the whole chip is provided.

[0054] The embodiment further discloses a DC-DC step-down converter comprising the current detection circuit.

[0055] The embodiment further discloses a chip comprising the current detection circuit.

[0056] The foregoing description of specific exemplary embodiments of the application is intended to be illustrative only and is not intended to limit the application to the precise forms described. Many modifications and variations are possible in light of the above teachings without departing from the spirit or essential characteristics of the application. The exemplary embodiments are chosen and described in order to explain the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the application be defined by the claims and their equivalents.

Claims

1. A current detection circuit for a DC-DC step-down converter, the DC-DC step-down converter comprising a primary power transistor and a secondary power transistor, wherein the source of the primary power transistor and the drain of the secondary power transistor are connected to form a connection node, the drain of the primary power transistor is configured to receive a power supply voltage, the source of the secondary power transistor is connected to a ground voltage, and the gates of the primary power transistor and the secondary power transistor are configured to receive a control signal, wherein: The current detection circuit includes: a bias current unit, configured to generate a first bias current and transmit the first bias current to the connection node, the bias current unit comprising a first current mirror, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor, and a second resistor; The gate of the first MOS transistor is connected to the gate of the third MOS transistor, the source of the first MOS transistor and the source of the third MOS transistor are connected to a power supply voltage, the gate of the second MOS transistor is connected to the gate of the fourth MOS transistor, the source of the second MOS transistor is connected to the drain of the first MOS transistor, and the source of the fourth MOS transistor is connected to the drain of the third MOS transistor. A first end of the first resistor is connected to the drain of the second MOS transistor and the gate of the first MOS transistor to form a first node, a second end of the first resistor is connected to a first current mirror and the gate of the second MOS transistor to form a second node, the first current mirror is also used to receive an input current, a first end of the second resistor is connected to the drain of the fourth MOS transistor, and a second end of the second resistor is connected to the connection node; a first startup unit connected to the first node and the second node, and configured to increase a speed at which the voltages on the first node and the second node are established; and The comparator is used for comparing the voltage of the connection node with the ground voltage and outputting a control signal to the gate of the secondary power transistor.

2. The current detection circuit according to claim 1, wherein: The first startup unit includes a first capacitor, a fifteenth MOS transistor, and a twenty-fifth MOS transistor. The first end of the first capacitor is connected to a power supply voltage, the second end of the first capacitor is connected to a drain of the twenty-fifth MOS transistor and a source of the fifteenth MOS transistor, the source of the twenty-fifth MOS transistor is connected to a ground voltage, the drain of the fifteenth MOS transistor is connected to a first node, and the gates of the fifteenth MOS transistor and the twenty-fifth MOS transistor are used to receive a second control signal.

3. The current detection circuit according to claim 2, wherein: The first startup unit also includes a fourteenth MOS transistor and a sixteenth MOS transistor, the source of the fourteenth MOS transistor and the source of the sixteenth MOS transistor are connected to the power supply voltage, the drain of the fourteenth MOS transistor is connected to the second node, the drain of the sixteenth MOS transistor is connected to the first node, and the gate of the fourteenth MOS transistor and the gate of the sixteenth MOS transistor are used to receive a third control signal.

4. The current detection circuit according to claim 1, wherein: The bias current unit further includes a twentieth MOS transistor, a drain of the twentieth MOS transistor is connected to the second node, a source of the twentieth MOS transistor is connected to the first current mirror, and a gate of the twentieth MOS transistor is used to receive the first control signal.

5. The current detection circuit according to claim 1, wherein: The comparator includes a second current mirror, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a third current mirror, a twenty-fourth MOS transistor, a third resistor, a fourth resistor and a fifth resistor; A first end of the third resistor is connected to the second current mirror, and a second end of the third resistor is connected to the ground voltage. The source of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and is also connected to the second current mirror. The gate of the tenth MOS transistor is connected to the connection node, and the gate of the eleventh MOS transistor is also connected to the ground voltage. A first end of the fourth resistor is connected to the drain of the tenth MOS transistor, and a second end of the fourth resistor is connected to the ground voltage. A first end of the fifth resistor is connected to the drain of the eleventh MOS transistor, and a second end of the fifth resistor is connected to the ground voltage. The source of the twelfth MOS transistor is connected to the source of the thirteenth MOS transistor and is also connected to the second current mirror. The gate of the twelfth MOS transistor is connected to the drain of the eleventh MOS transistor, the gate of the thirteenth MOS transistor is connected to the drain of the tenth MOS transistor, and the drains of the twelfth MOS transistor and the thirteenth MOS transistor are both connected to the third current mirror. The drain of the twenty-fourth MOS transistor is connected to the second current mirror, the gate of the twenty-fourth MOS transistor is connected to the drain of the thirteenth MOS transistor, and the source of the twenty-fourth MOS transistor is connected to the ground voltage.

6. The current detection circuit according to claim 5, wherein: The comparator further includes a twenty-first MOS transistor, a drain of the twenty-first MOS transistor being connected to the second end of the third resistor, a gate of the twenty-first MOS transistor being used to receive the first control signal, and a source of the twenty-first MOS transistor being connected to the ground voltage.

7. The current detection circuit according to claim 5, wherein: The current detection circuit further includes a second startup unit connected to the gates of the MOS tubes of the second current mirror, and the second startup unit is used to increase the settling speed of the comparator.

8. The current detection circuit according to claim 7, wherein: The second startup unit includes a second capacitor, a seventeenth MOS transistor, and a twenty-sixth MOS transistor. The first end of the second capacitor is connected to the power supply voltage, the source of the seventeenth MOS transistor and the drain of the twenty-sixth MOS transistor are connected to the second end of the second capacitor, the gate of the seventeenth MOS transistor and the gate of the twenty-sixth MOS transistor are used to receive a second control signal, the source of the twenty-sixth MOS transistor is connected to the ground voltage, and the drain of the seventeenth MOS transistor is connected to the gates of each MOS transistor of the second current mirror.

9. The current detection circuit according to claim 5, wherein: The comparator further includes a seventh MOS transistor, a source of the seventh MOS transistor being connected to the power supply voltage, a gate of the seventh MOS transistor being used to receive a third control voltage, and a drain of the seventh MOS transistor being connected to the gates of the MOS transistors of the second current mirror.

10. A DC-DC step-down converter, characterized in that: include: The current detection circuit according to any one of claims 1 to 9.

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