A variable frequency synchronization system, method, device and storage medium

Abstract

The application discloses a variable frequency synchronization system, comprising a variable frequency part, a first branch part, a second branch part and n to-be-synchronized parts; the variable frequency part is used for generating a variable frequency clock signal; the first branch part and the second branch part are used for respectively branching the clock signal and a synchronization signal; the to-be-synchronized part comprises a circuit for synchronization; the output end of the variable frequency part is connected with the first branch part; the multiple output ends of the first branch part are connected with the n to-be-synchronized parts, and the multiple output ends of the second branch part are connected with the n to-be-synchronized parts; one of the n to-be-synchronized parts is used as a master synchronization part; the remaining n-1 to-be-synchronized parts are used as slave synchronization parts; one output end of the to-be-synchronized part as the master synchronization part is connected with the second branch part; a corresponding synchronization method is further disclosed; the whole device has greater arrangement redundancy, the use frequency of the synchronization can be further improved, and the synchronization process has higher reliability.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency and laser equipment, and specifically relates to a frequency conversion synchronization device and method. Background Technology

[0002] Traditional synchronization processes rely on a main synchronization section issuing a synchronization signal, followed by other sections aligning to the signal. This process is prone to misalignment at higher clock frequencies, leading to reduced synchronization reliability. This invention addresses this by frequency conversion. During the synchronization establishment phase, a lower frequency clock signal is output from the frequency conversion section to complete clock synchronization. The clock frequency is then gradually increased to enter normal operating conditions, thereby improving the reliability of synchronization establishment. Summary of the Invention

[0003] To address the aforementioned problems, the invention proposes a frequency conversion synchronization system, comprising a frequency conversion section, a first branch section, a second branch section, and n parts to be synchronized (n is a positive integer greater than 1); the frequency conversion section is used to generate a frequency conversion clock signal; the first branch section and the second branch section are used to split the clock signal and the synchronization signal respectively; the parts to be synchronized include circuits for synchronization, which are devices or modules to be synchronized.

[0004] The output of the frequency converter section is connected to the first branch section; multiple outputs of the first branch section are connected to n parts to be synchronized; multiple outputs of the second branch section are connected to n parts to be synchronized; one of the n parts to be synchronized serves as the master synchronization part; the remaining n-1 parts to be synchronized serve as slave synchronization parts, and one output of the master synchronization part is connected to the second branch section.

[0005] Furthermore, the frequency conversion section is a DDS, a VCO, or a frequency source plus a frequency divider.

[0006] Furthermore, the first branch section and the second branch section are power dividers or buffers.

[0007] Furthermore, the synchronization circuit of the main synchronization section generates a synchronization signal for other parts to be synchronized, and then the main synchronization section and the slave synchronization section receive the synchronization signal to synchronize; the frequency conversion section outputs a low frequency clock signal during the synchronization establishment phase to complete the synchronization, and then gradually increases the clock frequency, and finally enters the normal use state.

[0008] As another aspect of the present invention, a frequency conversion synchronization method is also provided, comprising the following steps:

[0009] Step 1: Before synchronization begins, output a low-frequency system clock signal from the frequency converter section;

[0010] Step 2: Synchronization establishment phase, under a lower system clock, each part to be synchronized completes clock synchronization using internal synchronization circuits;

[0011] Step 3: After synchronization is complete, stop updating the synchronization value Num, and each part that has completed synchronization enters its respective synchronization hold state;

[0012] Step 4: Entering the transition phase, the frequency converter gradually increases the system clock frequency to the operating frequency;

[0013] Step 5: Once the system clock frequency reaches the operating frequency, the system enters the operating phase.

[0014] Furthermore, the method in step 1 specifically involves: the system clock signal A output from the frequency converter section is divided and connected by the first branch section to become system clock signals B1, B2...B1. n The time delays introduced during the process are denoted as ΔB1, ΔB2...ΔB. n After passing through each of the n parts to be synchronized, the input clock signals B1, B2...B... are respectively synchronized within each of the n parts to be synchronized. n Frequency division is performed to generate its own initial synchronization clocks C1, C2...C n The time delays introduced during the process are denoted as Δt1, Δt2...Δt. n Take part 1 to be synchronized as the master synchronization part, and the others as slave synchronization parts; transmit the synchronization clock of the master synchronization part to each part to be synchronized through the second branch section to synchronize each part, using D1, D2...D n This signal represents the time delays introduced during the process, denoted as ΔD1, ΔD2...ΔD. n .

[0015] Furthermore, the method in step 2 is specifically as follows: Let the time of the i-th rising edge at point A be t(A i The time of the i-th rising edge at B1 is t(B1). i The time of the i-th rising edge at point B2 is t(B2). i ), B n The time of the i-th rising edge of the timing sequence is t(B) n i The time of the i-th rising edge at C1 is t(C1). i The time of the i-th rising edge at C2 is t(C2). i ), C n The time of the i-th rising edge of the timing sequence is t(C) n i The time of the i-th rising edge at point D1 is t(D1). iThe time of the i-th rising edge at point D2 is t(D2). i ), D n Place

[0016] The time of the i-th rising edge of the timing sequence is t(D) n i ).

[0017] Therefore, in C1, C2...C n The time of the i-th rising edge of the timing sequence is:

[0018] t(C1 i )=t(B1 m·i )+Δt1=t(A m·i )+ΔB1+Δt1

[0019] t(C2 i )=t(B2 m·i )+Δt2=t(A m·i )+ΔB2+Δt2

[0020] t(C n i )=t(B n m·i )+Δt n =t(A m·i )+ΔB n +Δt n

[0021] When the synchronization part internally divides the system clock by m to generate a synchronization clock, where m ·i indicates that the i-th rising edge of the synchronous clock after frequency division corresponds to the i-th rising edge of the system clock. m • i rising edges.

[0022] Then in D1, D2...D n The time of the i-th rising edge of the timing sequence is:

[0023] t(D1 i )=t(C1 i )+ΔD1=t(A m·i )+ΔB1+Δt1+ΔD1

[0024] t(D2 i )=t(C1 i )+ΔD2=t(A m·i )+ΔB1+Δt1+ΔD2

[0025] t(D n i )=t(C1 i )+ΔD n =t(Am·i )+ΔB1+Δt1+ΔD n

[0026] The synchronization establishment process involves the internal synchronization clocks C1, C2...C1 of each part to be synchronized. n These are respectively synchronized with the received master synchronization clocks D1, D2...D... n Alignment is achieved within a single system clock cycle, thereby enabling synchronization between each part to be synchronized.

[0027] The above locations A, B1, ..., B n C1, ..., C n D1, ..., D n The locations represent the input ports of the branch section and the input ports of the section to be synchronized, respectively.

[0028] As another aspect of the present invention, a frequency conversion synchronization device is also provided, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the above-described frequency conversion synchronization method is implemented.

[0029] In another aspect, the present invention relates to a computer storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it implements the above-described frequency conversion synchronization method.

[0030] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0031] (1) The frequency conversion synchronization system and method of the present invention improves the reliability of synchronization establishment by converting the clock frequency therein, using the frequency conversion part to output a lower frequency clock signal to complete the clock synchronization during the synchronization establishment stage, and then gradually increasing the clock frequency to enter the normal use state.

[0032] (2) The frequency conversion synchronization system and method of the present invention reduce the clock frequency of the synchronization stage, thereby increasing the margin of the synchronization process and making the entire equipment have greater layout redundancy, which can further increase the frequency of synchronization and make the synchronization process more reliable. Attached Figure Description

[0033] Figure 1 This is a schematic diagram illustrating the principle of a preferred embodiment of the present invention;

[0034] Figure 2 The accompanying drawings show the timing process of the synchronization process in a preferred embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0036] Example 1:

[0037] Please refer to Figure 1 A frequency conversion synchronization system is characterized by comprising a frequency conversion section, a first branch section, a second branch section, and n sections to be synchronized (n is a positive integer greater than 1); the frequency conversion section is used to generate a frequency-convertible clock signal, which can be a DDS, a VCO, or a frequency source with a frequency divider.

[0038] The first and second branch sections are used to split the clock signal and the synchronization signal respectively, and can be power dividers or buffers; the section to be synchronized includes circuitry for synchronization, which is the device or module to be synchronized.

[0039] The output of the frequency converter section is connected to the first branch section; multiple outputs of the first branch section are connected to n parts to be synchronized; multiple outputs of the second branch section are connected to n parts to be synchronized; one of the n parts to be synchronized serves as the master synchronization part; the remaining n-1 parts to be synchronized serve as slave synchronization parts, and one output of the master synchronization part is connected to the second branch section.

[0040] The synchronization circuit of the main synchronization section generates a synchronization signal for other parts to be synchronized. Then, the main synchronization section and the slave synchronization section receive the synchronization signal and synchronize. The frequency conversion section outputs a low-frequency clock signal during the synchronization establishment phase to complete the synchronization. Then, the clock frequency is gradually increased, and finally, it enters the normal operation state.

[0041] It also involves a frequency conversion synchronization method, including the following steps:

[0042] Step 1: Before synchronization begins, output a low-frequency system clock signal from the frequency converter section;

[0043] Step 2: Synchronization establishment phase, under a lower system clock, each part to be synchronized completes clock synchronization using internal synchronization circuits;

[0044] Step 3: After synchronization is complete, stop updating the synchronization value Num, and each part that has completed synchronization enters its respective synchronization hold state;

[0045] Step 4: Entering the transition phase, the frequency converter gradually increases the system clock frequency to the operating frequency;

[0046] Step 5: Once the system clock frequency reaches the operating frequency, it enters the operating phase.

[0047] Specific calculation examples are as follows: The principle block diagram is shown below. Figure 1 As shown, the timing is as follows Figure 2 As shown. In Figure 1 In the process, the system clock signal A output from the frequency converter section is divided and connected by the first branch section to become system clock signals B1, B2...B1. n The time delays introduced during the process are denoted as ΔB1, ΔB2...ΔB. n After passing through each of the n parts to be synchronized, the input clock signals B1, B2...B... are respectively synchronized within each of the n parts to be synchronized. n Frequency division is performed to generate its own initial synchronization clocks C1, C2...C n The time delays introduced during the process are denoted as Δt1, Δt2...Δt. n Take part 1 to be synchronized as the master synchronization part, and the others as slave synchronization parts; transmit the synchronization clock of the master synchronization part to each part to be synchronized through the second branch section to synchronize each part, using D1, D2...D n This signal represents the time delays introduced during the process, denoted as ΔD1, ΔD2...ΔD. n .

[0048] Let t(A) be the time of the i-th rising edge of the timing sequence at point A. i The time of the i-th rising edge at B1 is t(B1). i The time of the i-th rising edge at point B2 is t(B2). i ), B n The time of the i-th rising edge of the timing sequence is t(B) n i The time of the i-th rising edge at C1 is t(C1). i The time of the i-th rising edge at C2 is t(C2). i ), C n The time of the i-th rising edge of the timing sequence is t(C) n i The time of the i-th rising edge at point D1 is t(D1). i The time of the i-th rising edge at point D2 is t(D2). i ), D n Place

[0049] The time of the i-th rising edge of the timing sequence is t(D) n i ).

[0050] Therefore, in C1, C2...Cn The time of the i-th rising edge of the timing sequence is:

[0051] t(C1 i )=t(B1 m·i )+Δt1=t(A m·i )+ΔB1+Δt1

[0052] t(C2 i )=t(B2 m·i )+Δt2=t(A m·i )+ΔB2+Δt2

[0053] t(C n i )=t(B n m·i )+Δt n =t(A m·i )+ΔB n +Δt n

[0054] When the synchronization part internally divides the system clock by m to generate a synchronization clock, where m ·i indicates that the i-th rising edge of the synchronous clock after frequency division corresponds to the i-th rising edge of the system clock. m • i rising edges.

[0055] Then in D1, D2...D n The time of the i-th rising edge of the timing sequence is:

[0056] t(D1 i )=t(C1 i )+ΔD1=t(A m·i )+ΔB1+Δt1+ΔD1

[0057] t(D2 i )=t(C1 i )+ΔD2=t(A m·i )+ΔB1+Δt1+ΔD2

[0058] t(D n i )=t(C1 i )+ΔD n =t(A m·i )+ΔB1+Δt1+ΔD n

[0059] The synchronization establishment process involves the internal synchronization clocks C1, C2...C1 of each part to be synchronized. n These are respectively synchronized with the received master synchronization clocks D1, D2...D... nAlignment is achieved within a single system clock cycle, thereby enabling synchronization between each part to be synchronized; points A, B1, ..., B... n C1, ..., C n D1, ..., D n The locations indicated are the input ports of the splitter section and the input ports of the section to be synchronized, respectively. Figure 1 The position marked by the black dot.

[0060] The synchronization process is misaligned, meaning that the time delays introduced by each stage cause the internal synchronization clocks C1, C2...C1 to be out of sync during alignment. n Synchronization clocks D1, D2...D with the main synchronization section n The intervals are staggered by one or more system clock cycles. (Using C...) n and D n For example:

[0061] Let floor(x) be the floor function and T be the system clock period. For the part n to be synchronized, the synchronization result is the synchronization value Num:

[0062]

[0063] It can be seen that when the time delay ΔB is at each point n +Δt n -ΔB1-Δt1-ΔD n When the fluctuation exceeds T, the synchronization result will change, resulting in a synchronization misalignment. However, if the system clock frequency is reduced during the synchronization establishment phase through frequency conversion, the same delay ΔB at each point can be reduced. n +Δt n -ΔB1-Δt1-ΔD n As a result, fluctuations are less likely to exceed T, thus improving the reliability of the synchronization establishment process. At the same time, due to the increase in T, the time delay ΔB at various points is also reduced. n +Δt n -ΔB1-Δt1-ΔD n The resulting fluctuations have a greater margin, thus enabling the establishment and synchronization of more complex scenarios.

[0064] Example 2:

[0065] Embodiment 2 of the present invention provides a frequency conversion synchronization device, including a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the frequency conversion synchronization method provided in Embodiment 1.

[0066] Example 3:

[0067] Embodiment 3 of the present invention provides a computer storage medium storing a computer program thereon, characterized in that, when the computer program is executed by a processor, it implements the frequency conversion synchronization method provided in Embodiment 1.

[0068] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A variable frequency synchronization system, characterized by, The frequency conversion part is used for generating a variable frequency clock signal; the first shunt part and the second shunt part are used for respectively shunting the clock signal and the synchronization signal; the to-be-synchronized part includes a circuit for synchronization, and is used for a device or a module to be synchronized; The output end of the frequency conversion part is connected with the input end of the first shunt part; the multiple output ends of the first shunt part are connected with the input ends of the n to-be-synchronized parts, and the multiple output ends of the second shunt part are connected with the input ends of the n to-be-synchronized parts; One of the n to-be-synchronized parts is used as a master synchronization part; The remaining n-1 to-be-synchronized parts are used as slave synchronization parts, and one output end of the master synchronization part is connected with the input end of the second shunt part.

2. The variable frequency synchronization system of claim 1, wherein, The frequency conversion part is a DDS or a VCO or a frequency source plus a frequency divider.

3. The variable frequency synchronization system of claim 2, wherein, The first shunt part and the second shunt part are power dividers or buffers.

4. The variable frequency synchronization system of claim 1, wherein, The synchronization circuit of the master synchronization part generates a synchronization signal for the other to-be-synchronized parts, and then the master synchronization part and the slave synchronization parts receive the synchronization signal to be synchronized; a lower frequency clock signal is outputted by the frequency conversion part in the synchronization establishment stage to complete the synchronization, and then the clock frequency is gradually increased, and finally enters a normal use state.

5. The method of claim 1, wherein the frequency synchronization is performed by a frequency synchronization system comprising: a frequency synchronization controller; a frequency synchronization memory; a frequency synchronization processor; a frequency synchronization transmitter; and a frequency synchronization receiver. The method comprises the following steps: Step 1: before synchronization starts, a lower frequency system clock signal is outputted by the frequency conversion part; Step 2: in the synchronization establishment stage, each to-be-synchronized part completes clock synchronization by using an internal synchronization circuit under a lower system clock; Step 3: after synchronization is completed, the update of the synchronization value Num is stopped, and each to-be-synchronized part after completing synchronization enters a respective synchronization maintaining state, and the synchronization value Num is a value obtained by rounding down a ratio of a time delay to a system clock period T; Step 4: a transition stage is entered, and the frequency conversion part gradually increases the system clock frequency to a use frequency; Step 5: after the system clock frequency reaches the use frequency, a use stage is entered.

6. The variable frequency synchronization method of claim 5, wherein, The method of step 1 is specifically: the system clock signal A output from the frequency conversion part is divided by a first shunt part and connected to become system clock signals B1, B2...B n , and the time delay introduced in the process is respectively set as ; After passing through each of the n parts to be synchronized, the input clock signals B1, B2...B... are respectively processed within each of the n parts to be synchronized. n Frequency division is performed to generate its own initial synchronization clocks C1, C2...C n The time delays introduced during the process are respectively set as Take part 1 to be synchronized as the master synchronization part, and the others as slave synchronization parts; transmit the synchronization clock of the master synchronization part to each part to be synchronized through the second branch section to synchronize each part, using D1, D2...D n This signal represents the time delay introduced during the process, which is set as follows: .

7. The variable frequency synchronization method of claim 6, wherein, The method of step 2 is specifically: the time of the i-th rising edge of timing at A is , the time of the i-th rising edge of timing at B1 is , the time of the i-th rising edge of timing at B2 is , …, the time of the i-th rising edge of timing at B n is , the time of the i-th rising edge of timing at C1 is , the time of the i-th rising edge of timing at C2 is , …, the time of the i-th rising edge of timing at C n is , the time of the i-th rising edge of timing at D1 is , the time of the i-th rising edge of timing at D2 is , …, the time of the i-th rising edge of timing at D n is ; So at C1, C2...C n the time of the i-th rising edge of the clock is: When the synchronization part internally divides the system clock by m to generate a synchronization clock, where This indicates that the i-th rising edge of the synchronous clock after frequency division corresponds to the i-th rising edge of the system clock. One rising edge; for At this location, corresponding to the system clock's [number]th [time / location] The time of the rising edge At point A, corresponding to the system clock's [number]th [number]th [time]. The times of the i-th rising edge at points D1, D2, ..., Dn are respectively: The synchronization establishment process is that the internal synchronization clock C1, C2...C n of each part to be synchronized is respectively aligned to the synchronization clock D1, D2...D n of the received main synchronization part within one system clock cycle, so as to achieve the synchronization between each part to be synchronized; A, B1, …, B n 1, C1, …, C n 1, D1, …, D n 1 respectively represent the clock signal transmission to the input port of the branch part or the input port of the part to be synchronized.

8. A variable frequency synchronization apparatus, characterized by, The computer program is executed by the processor to realize the variable frequency synchronization method.

9. A computer storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to realize the variable frequency synchronization method.

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