Image Sensor Containing CMOS Image Sensor Pixels and Dynamic Vision Sensor Pixels

Abstract

An image sensor includes CIS (CMOS image sensor) pixels, DVS (dynamic vision sensor), and an image signal processor. The CIS pixels include: a photoelectric conversion device that generates charges corresponding to incident light; and a readout circuit that generates an output voltage corresponding to the generated charges. The DVS pixels detect a change in the intensity of incident light based on the generated charges and output an event signal, and do not include a separate photoelectric conversion device. The image signal processor enables the photoelectric conversion device to be connected to the readout circuit or the DVS pixels.

Description

[0001] This application is a divisional application of the invention application with the application date of September 9, 2019, the application number of 2019108568114, and the invention name of "Image Sensor Comprising CMOS Image Sensor Pixels and Dynamic Vision Sensor Pixels".

[0002] Cross - reference to related applications

[0003] This application claims the priority of Korean Patent Application No. 10 - 2018 - 0107280, filed with the Korean Intellectual Property Office on September 7, 2018, and Korean Patent Application No. 10 - 2019 - 0028938, filed with the Korean Intellectual Property Office on March 13, 2019, the disclosures of which are incorporated herein by reference in their entireties. Technical Field

[0004] The present disclosure relates to an image sensor, and more particularly, to an image sensor including two different types of pixels. Background Art

[0005] Conventional types of image sensors include complementary metal - oxide - semiconductor (CMOS) image sensors and dynamic vision sensors. The advantage of a CMOS image sensor may be that the captured image is provided to a user without modification, but the disadvantage may be that the amount of data to be processed is high. Since a dynamic vision sensor only detects events of changes in light intensity and provides an output of the detected events, the advantage of a dynamic vision sensor may be that the amount of data to be processed is low, but the disadvantage may be that the size of the dynamic vision sensor is larger than that of the CMOS image sensor.

[0006] However, both a CMOS image sensor and a dynamic vision sensor may require a photoelectric conversion device for detecting light. Generally, since the photoelectric conversion device occupies most of the size of the image sensor, when a CMOS image sensor and a dynamic vision sensor are implemented together in one device, the size of the device increases. Therefore, there is a need for a structure of an image sensor for reducing the size of the image sensor and lowering the manufacturing cost of the image sensor. Summary of the Invention

[0007] Aspects of embodiments of the present disclosure provide a structure for sharing a photoelectric conversion device between a CMOS image sensor and a dynamic vision sensor.

[0008] Aspects of embodiments provide a structure in which a dynamic vision sensor uses a photoelectric conversion device included in a CMOS image sensor.

[0009] According to an embodiment, an image sensor includes: a CIS pixel including a photoelectric conversion device and a readout circuit, the photoelectric conversion device being configured to generate charges corresponding to incident light incident on the CIS pixel, and the readout circuit being configured to generate an output voltage corresponding to the charges; a dynamic vision sensor (DVS) pixel configured to detect a change in the intensity of incident light based on the charges generated by the photoelectric conversion device and output an event signal based on the change in intensity; and an image signal processor configured to selectively control the image sensor to generate first image data of the image sensor based on the output voltage generated by the CIS pixel and generate second image data based on the event signal generated by the DVS pixel.

[0010] According to an embodiment, an image sensor includes: a CIS pixel including a photoelectric conversion device, a driving transistor, and a reset transistor, the photoelectric conversion device being configured to generate charges corresponding to incident light incident on the CIS pixel, the driving transistor including a gate electrode connected to a floating diffusion node to which the charges generated by the photoelectric conversion device are transferred, and the reset transistor being configured to reset the voltage of the floating diffusion node; a dynamic vision sensor (DVS) pixel including a logarithmic current source and configured to detect a change in the intensity of incident light based on the charges generated by the photoelectric conversion device and output an event signal based on the change in intensity; and an image signal processor configured to connect the gate electrode of the reset transistor and one end of the driving transistor to the logarithmic current source.

[0011] According to an embodiment, an image sensor includes: a first substrate on which a CIS pixel array including a plurality of complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) pixels is formed, each CIS pixel of the CIS pixel array including a photoelectric conversion device and a readout circuit, the photoelectric conversion device being configured to generate charges corresponding to incident light incident on the CIS pixel, and the readout circuit being configured to generate an output voltage corresponding to the charges generated by the photoelectric conversion device; a second substrate on which a DVS pixel array including a plurality of dynamic vision sensor (DVS) pixels is formed, each DVS pixel of the DVS pixel array being configured to detect a change in the intensity of incident light based on the charges generated by the CIS pixel array and output an event signal based on the change in intensity; and an image signal processor configured to selectively control the image sensor to generate image data of the image sensor based on the output voltage and generate image data based on the event signal generated by the DVS pixel array. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0013] Figure 1Shows an image sensor according to an embodiment of the present disclosure;

[0014] Figure 2 Shows Figure 1 the structure of a CMOS image sensor;

[0015] Figure 3 Shows Figure 2 the circuit diagram of the structure of a CIS pixel;

[0016] Figure 4 Shows Figure 1 the structure of a dynamic vision sensor;

[0017] Figure 5 Shows Figure 4 the circuit diagram of the structure of a DVS pixel in a DVS pixel array;

[0018] Figure 6 Shows Figure 5 the structure of a DVS pixel backend circuit;

[0019] Figure 7 Shows a CIS pixel and a DVS pixel of a shared photoelectric conversion device according to an embodiment of the present disclosure;

[0020] Figure 8 Shows a cross-sectional view of an image sensor according to an embodiment of the present disclosure;

[0021] Figure 9 Shows the circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0022] Figure 10 Is a diagram showing Figure 9 the image sensor operating in the first mode;

[0023] Figure 11 Is a diagram showing Figure 9 the image sensor operating in the second mode;

[0024] Figure 12 Shows the circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0025] Figure 13 Shows the circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0026] Figure 14 Shows the circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0027] Figure 15 Shows the circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0028] Figure 16Shows Figure 2 The circuit diagram of the structure of the CIS pixel;

[0029] Figure 17 The circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0030] Figure 18 The circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0031] Figure 19 The circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0032] Figure 20 Is a diagram showing Figure 19 The image sensor of [ID] operating in the first mode;

[0033] Figure 21 Is a diagram showing Figure 19 The image sensor of [ID] operating in the second mode;

[0034] Figure 22 The circuit diagram of an image sensor according to an embodiment of the present disclosure;

[0035] Figure 23 The circuit diagram of an image sensor according to an embodiment of the present disclosure; and

[0036] Figure 24 The circuit diagram of an image sensor according to an embodiment of the present disclosure. Detailed Description of the Invention

[0037] Embodiments of the present disclosure will be described in detail and clearly below to the extent that those of ordinary skill in the art to which the present disclosure pertains can easily implement these embodiments.

[0038] The components described in the detailed description with reference to terms such as "unit", "module", "……er" or "……or" and the functional blocks shown in the drawings will be implemented using software, hardware, or a combination thereof. In an embodiment, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof. In addition, unless otherwise stated in this specification, the expression "the first component is connected to the second component" includes a configuration in which the two components are indirectly connected by a third component inserted therebetween.

[0039] Figure 1FIG. 0 shows an image sensor 1000 according to an embodiment of the present disclosure. The image sensor 1000 includes an image signal processor 1100, a complementary metal oxide semiconductor (CMOS) image sensor 1200, and a dynamic vision sensor (DVS) 1300.

[0040] The image signal processor 1100 may process signals output from the CMOS image sensor 1200 and / or the dynamic vision sensor 1300, and may generate and output an image IMG. In an embodiment, the image signal processor 1100 may process frame-based image data received from the CMOS image sensor 1200, and may generate the image IMG based on the frame-based image data. Alternatively, the image signal processor 1100 may process packet-based or frame-based image data received from the dynamic vision sensor 1300, and may generate the image IMG based on the packet-based or frame-based image data.

[0041] The image signal processor 1100 may perform various processes on the image data received from the CMOS image sensor 1200. For example, the image signal processor 1100 may perform various processes such as color interpolation, color correction, automatic white balance, gamma correction, color saturation correction, formatting, bad pixel correction, and chromaticity correction.

[0042] The image signal processor 1100 may perform various processes on the image data received from the dynamic vision sensor 1300. For example, the image signal processor 1100 may correct (or calibrate) the timestamp values of noise pixels, hot pixels, or dead pixels by using the temporal correlation between the timestamp values of adjacent pixels of the dynamic vision sensor 1300.

[0043] The CMOS image sensor 1200 includes a plurality of CMOS image sensor (CIS) pixels, and each CIS pixel of the plurality of CIS pixels includes a photoelectric conversion device (PSD). In contrast, each DVS pixel of the plurality of DVS pixels of the dynamic vision sensor 1300 does not include a photoelectric conversion device. Instead, the dynamic vision sensor 1300 may utilize the photoelectric conversion device PSD of the CMOS image sensor 1200. That is, the CMOS image sensor 1200 and the dynamic vision sensor 1300 may share the photoelectric conversion device PSD.

[0044] In an embodiment, when the CMOS image sensor 1200 is operating to generate frame-based image data, the path electrically connecting the photoelectric conversion device PSD and the DVS 1300 can be blocked, disconnected, or the DVS 1300 can be inaccessible. Conversely, when the CMOS image sensor 1200 is not operating to generate frame-based image data, the photoelectric conversion device PSD and the DVS 1300 can be electrically connected. Thus, when the CMOS image sensor 1200 is not operating to generate frame-based image data and the photoelectric conversion device PSD is not used, the DVS 1300 can instead utilize the photoelectric conversion device PSD to generate packet-based or frame-based image data. In an embodiment, the image signal processor 1100 can control the operation mode of the image sensor 1000. For example, the image signal processor 1100 can generate at least one control signal for changing the operation mode to control the switching between various operation modes. The structure in which the CMOS image sensor 1200 and the dynamic vision sensor 1300 share the photoelectric conversion device can reduce the size and manufacturing cost of the image sensor 1000. The detailed structure will be described in more detail below.

[0045] Here, the CIS pixels of the CMOS image sensor 1200 and the DVS pixels of the DVS 1300 sharing the photoelectric conversion device will be described, but such a concept can be applied to different types of sensors and pixels and their combinations other than CMOS sensors and pixels and DVS sensors and pixels. For example, this concept can be applied to a combination of charge-coupled device (CCD)-type pixels and CIS pixels. In addition, this concept can be applied to a combination of CCD-type pixels and DVS pixels. In addition, this concept can be applied to an image sensor including CCD-type pixels, CIS pixels, and DVS pixels. The types of sensors and pixels and their combinations are not limited to the above types and combinations.

[0046] Figure 2 is shown Figure 1 the structure of the CMOS image sensor 1200.

[0047] The CMOS image sensor 1200 is configured to generate image data of the object 10 incident through the lens 1201. The CMOS image sensor 1200 includes a CIS pixel array 1210, a row decoder 1220, a correlated double sampler (CDS) 1230, an analog-to-digital converter (ADC) 1240, an output buffer 1250, a timing controller 1260, and a ramp generator 1270.

[0048] The CIS pixel array 1210 may include a plurality of CIS pixels (PX) 1211 arranged in rows and columns. In an embodiment, each of the plurality of CIS pixels 1211 may have a three-transistor (3TR) pixel structure in which a pixel is implemented with three transistors, a four-transistor (4TR) pixel structure in which a pixel is implemented with four transistors, or a five-transistor (5TR) pixel structure in which a pixel is implemented with five transistors. Alternatively, at least two of the plurality of CIS pixels constituting the CIS pixel array 1210 may share the same floating diffusion region FD (or floating diffusion node). However, the structure of the CIS pixel is not limited to the above configurations.

[0049] The row decoder 1220 may select and drive the rows of the CIS pixel array 1210. In an embodiment, the row decoder 1220 decodes the row address and / or control signal output from the timing controller 1260 and generates a control signal for selecting and driving the row of the CIS pixel array 1210 indicated by the row address and / or control signal. For example, the row decoder 1220 may generate a selection signal VSEL, a reset signal VRST, and a transfer signal VTG, and may send the generated signals VSEL, VRST, and VTG to the pixels corresponding to the selected row.

[0050] The correlated double sampler 1230 may sequentially sample and hold a set of reference signals and image signals provided from the CIS pixel array 1210 through the column lines CL1 to CLn. In other words, the correlated double sampler 1230 may sample and hold the levels of the reference signal and the image signal corresponding to each column. The correlated double sampler 1230 may provide the set of reference signals and image signals sampled for each column to the analog-to-digital converter 1240 under the control of the timing controller 1260.

[0051] The analog-to-digital converter 1240 may convert the correlated double sampled signals of each column output from the correlated double sampler 1230 into digital signals. In an embodiment, the analog-to-digital converter 1240 may compare the correlated double sampled signals with the ramp signals output from the ramp generator 1270 and may generate digital signals corresponding to the comparison results.

[0052] The output buffer 1250 may temporarily store the digital signals provided from the analog-to-digital converter 1240.

[0053] The timing controller 1260 may control the operations of at least one of the CIS pixel array 1210, the row decoder 1220, the correlated double sampler 1230, the analog-to-digital converter 1240, the output buffer 1250, and the ramp generator 1270.

[0054] The ramp generator 1270 can generate a ramp signal and can supply the ramp signal to the analog-to-digital converter 1240.

[0055] For example, at least a part of the row decoder 1220, the correlated double sampler 1230, the analog-to-digital converter 1240, the output buffer 1250, the timing controller 1260, and the ramp generator 1270 can be referred to as "CIS peripheral circuits".

[0056] Figure 3 Shows Figure 2 An exemplary configuration of the CIS pixel 1211. In an embodiment, the CIS pixel 1211 can have a four-transistor (4TR) structure including four transistors. The CIS pixel 1211 can include a photoelectric conversion device PSD, a transfer transistor TG, a reset transistor RT, a driving transistor DT, and a selection transistor ST.

[0057] The photoelectric conversion device PSD can generate photoelectrons (hereinafter referred to as "charges") in response to incident light. That is, the photoelectric conversion device PSD can convert an optical signal into an electrical signal to generate a photocurrent IP. For example, the photoelectric conversion device PSD can include a photodiode, a phototransistor, a pinned photodiode, or any other similar device.

[0058] The transfer transistor TG can transfer the charges generated by the photoelectric conversion device PSD to the floating diffusion region FD. For example, the source terminal of the transfer transistor TG can be connected to the photoelectric conversion device PSD, and the drain terminal of the transfer transistor TG can be connected to the floating diffusion region FD. In response to the transfer signal VTG received from the row decoder 1220 (refer to Figure 2 ) at the gate of the transfer transistor TG, the transfer transistor TG can be turned on or off.

[0059] The floating diffusion region FD can have a function of detecting charges corresponding to the amount of incident light. During the time when the transfer signal VTG is activated, the charges provided by the photoelectric conversion device PSD can be accumulated in the floating diffusion region FD. The floating diffusion region FD can be connected to the gate terminal of the driving transistor DT operating as a source follower amplifier. The floating diffusion region FD can be reset to the power supply voltage VDD provided when the reset transistor RT is turned on.

[0060] The reset transistor RT can be reset by a reset signal VRST and can supply a power supply voltage VDD to the floating diffusion region FD. In this case, the charge accumulated in the floating diffusion region FD can move to the terminal of the power supply voltage VDD, and the voltage of the floating diffusion region FD can be reset. Even if the power supply voltage VDD is described as the voltage to be applied to the floating diffusion region FD, voltages of various levels (i.e., reset voltages) can be used to reset the floating diffusion region FD.

[0061] The driving transistor DT can be used as a source follower amplifier. The driving transistor DT can amplify the change in the potential of the floating diffusion region FD and can output an output voltage VOUT corresponding to the amplification result through the first column line CL1. Figure 3 An embodiment in which the CIS pixel 1211 is connected to the first column line CL1 is shown.

[0062] The selection transistor ST can be driven by a selection signal VSEL and can select pixels to be read in units of rows. When the selection transistor ST is turned on, the potential of the floating diffusion region FD can be amplified by the driving transistor DT and can be transmitted to the drain electrode of the selection transistor ST.

[0063] In the embodiment, the driving transistor DT and the selection transistor ST can be referred to as a "readout circuit". That is, the readout circuit can generate an output voltage VOUT corresponding to the charge accumulated in the floating diffusion region FD.

[0064] Figure 4 Shown is Figure 1 an exemplary configuration of the dynamic vision sensor 1300.

[0065] The dynamic vision sensor 1300 can include a DVS pixel array 1310, a column address event representation (AER) circuit 1320, a row AER circuit 1330, and an output buffer 1340. The dynamic vision sensor 1300 can detect an event in which the intensity of light incident on the DVS pixels changes, can determine the type of the detected event (i.e., whether the detected event is an event in which the intensity of light increases or an event in which the intensity of light decreases), and can output a value corresponding to the event. For example, events can mainly occur in the contour of a moving object. Different from the CMOS image sensor 1200 (refer to Figure 1 ), the dynamic vision sensor 1300 can only output a value corresponding to the light whose intensity changes, thereby significantly reducing the amount of data to be processed by the dynamic vision sensor 1300 and / or the image signal processor 1100 (refer to Figure 1 ).

[0066] The DVS pixel array 1310 may include a plurality of DVS pixels arranged in a matrix along a plurality of rows and a plurality of columns. The DVS pixels in the plurality of DVS pixels of the DVS pixel array 1310 that detect an event may output a signal (i.e., a column request) CR indicating an event of an increase or decrease in the intensity of light occurring to the column AER circuit 1320.

[0067] The column AER circuit 1320 may output an acknowledgment signal ACK to the DVS pixel in response to the column request CR received from the DVS pixel that detected the event. The DVS pixel that receives the acknowledgment signal ACK may output the polarity information PoI of the event to the row AER circuit 1330. The column AER circuit 1320 may generate a column address C_ADDR of the DVS pixel that detected the event based on the column request CR received from the pixel that detected the event.

[0068] The row AER circuit 1330 may receive the polarity information PoI from the DVS pixel that detected the event. The row AER circuit 1330 may generate a timestamp including information about the time of occurrence of the event based on the polarity information PoI. In an embodiment, the timestamp may be generated by a timestamp generator 1332 provided in the row AER circuit 1330. For example, the timestamp generator 1332 may be implemented by using a time period generated in units of a few microseconds to dozens of microseconds. The row AER circuit 1330 may output a reset signal RST to the DVS pixel that detected the event in response to the polarity information PoI. The DVS pixel that detected the event may be reset by the reset signal RST. In addition, the row AER circuit 1330 may generate a row address R_ADDR of the DVS pixel that detected the event.

[0069] The row AER circuit 1330 may control the period during which the reset signal RST is generated. For example, in order to prevent an increase in workload due to a large number of events occurring, the row AER circuit 1330 may control the period during which the reset signal RST is generated such that no event occurs during a specific period. That is, the row AER circuit 1330 may control the refractory period of event occurrence.

[0070] The output buffer 1340 may generate a packet based on the timestamp, the column address C_ADDR, the row address R_ADDR, and the polarity information PoI. The output buffer 1340 may add a header indicating the start of the packet in front of the packet and add a tail indicating the end of the packet at the end of the packet.

[0071] For example, at least a part of the column AER circuit 1320, the row AER circuit 1330, and the output buffer 1340 may be referred to as a "DVS peripheral circuit".

[0072] Figure 5 is shown Figure 4Circuit diagram of the structure of a DVS pixel in a DVS pixel array. The DVS pixel 1311 may include a photosensor 1313 and a DVS pixel backend circuit 1315.

[0073] The photosensor 1313 may include a logarithmic amplifier LA and a feedback transistor FB. However, different from a general DVS pixel, the photosensor 1313 may not include a photoelectric conversion device PSD. Figure 5 The illustrated photoelectric conversion device PSD may be a component of the CIS pixel 1211 (refer to Figure 3 ). The logarithmic amplifier LA amplifies the voltage corresponding to the photocurrent IP generated by the photoelectric conversion device PSD of the CIS pixel 1211. The logarithmic amplifier LA may output a logarithmic voltage VLOG on a logarithmic scale. The feedback transistor FB may separate the photosensor 1313 from the differentiator 1316 described below with reference to Figure 6 .

[0074] The DVS pixel backend circuit 1315 may perform various processes on the logarithmic voltage VLOG. In an embodiment, the DVS pixel backend circuit 1315 may amplify the logarithmic voltage VLOG, compare the amplified voltage with a reference voltage to determine whether the light incident on the photoelectric conversion device PSD is light whose intensity increases or decreases, and output an event signal corresponding to the determination result (i.e., an on-event or an off-event). After the DVS pixel backend circuit 1315 outputs an on-event or an off-event, the DVS pixel backend circuit 1315 may be reset by a reset signal RST.

[0075] Figure 6 Illustrated is Figure 5 the structure of the DVS pixel backend circuit. The DVS pixel backend circuit 1315 may include a differentiator 1316, a comparator 1317, and a readout circuit 1318.

[0076] The differentiator 1316 may amplify the voltage VLOG to generate a voltage VDIFF. For example, the differentiator 1316 may include capacitors C1 and C2, a differential amplifier DA, and a switch SW, and the switch SW may operate in response to the reset signal RST. For example, the capacitors C1 and C2 may store the electric energy generated by at least one photoelectric conversion device PSD. For example, the capacitances of the capacitors C1 and C2 may be appropriately selected in consideration of the shortest time (e.g., refractory period) between two events that can occur continuously at one pixel. When the switch SW is closed by the reset signal RST, the pixel may be initialized (or reset). The reset signal RST may be received from the row AER circuit 1330 (refer to Figure 3 ).

[0077] Comparator 1317 can compare the level of the output voltage VDIFF of differential amplifier DA with the level of reference voltage Vref, and can determine whether the event detected by the pixel is a turn-on event or a turn-off event. When an event of increasing light intensity is detected, comparator 1317 can output a signal ON indicating that the detected event is a turn-on event; when an event of decreasing light intensity is detected, comparator 1317 can output a signal OFF indicating that the detected event is a turn-off event.

[0078] Readout circuit 1318 can output information about the event occurring at the pixel. The information about the event output from readout circuit 1318 can include information (e.g., a bit) indicating whether the occurring event is a turn-on event or a turn-off event. The information indicating the event output from readout circuit 1318 can be referred to as "polarity information PoI" (refer to Figure 4 ). The polarity information PoI can be provided to row AER circuit 1330 (refer to Figure 4 ).

[0079] Meanwhile, Figure 5 and Figure 6 the structure of the pixel shown in the embodiments of

[0080] Figure 7 is exemplary, and event detection can be applied to various structures of DVS pixels configured to determine the event type based on the result of detecting light intensity.

[0081] In an embodiment, in a plan view (i.e., observing the pixel in the Z-axis direction), four CIS pixels can correspond to one DVS pixel. The reason is that the size of the DVS pixel is larger than that of the CIS pixel. However, the number of CIS pixels corresponding to one DVS pixel can vary according to the size of each pixel and is not limited to Figure 7 the ratio of

[0082] The photoelectric conversion device PSD of each CIS pixel 1211 can be connected to DVS pixel 1311 through interconnector IC. In an embodiment, when image sensor 1000 (refer to Figure 1 ) operates in DVS mode, only the photoelectric conversion device PSD of DVS pixel 1311 and CIS pixel 1211 can work. The charge generated by the photoelectric conversion device PSD is transmitted to DVS pixel 1311 through interconnector IC. In an embodiment, interconnector IC can represent various structures for electrically connecting CIS pixel 1211 and DVS pixel 1311. For example, interconnector IC can include at least one of wire, lead wire, solder ball, bump, and through-silicon via (TSV).

[0083] Figure 8 Shows a cross-sectional view of an image sensor according to an embodiment of the present disclosure. It will be described with reference to Figure 3 and Figure 5 together the operation of the image sensor 1000 in the DVS mode.

[0084] The image sensor 1000 includes a CIS pixel array 1210 and a DVS pixel array 1310. Among them, the CIS pixel array 1210 includes CIS pixels 1211, and the DVS pixel array 1310 includes DVS pixels 1311. A lens 1201 may be disposed on the CIS pixel array 1210. The DVS pixels may be isolated from each other by a deep trench isolation structure DTI. The deep trench isolation structure DTI may include an insulating material layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. In addition, the deep trench isolation structure DTI may include a polysilicon pattern disposed therein. The CIS pixel array 1210 and the DVS pixel array 1310 may be formed on different substrates, respectively.

[0085] In an embodiment, a first substrate including the CIS pixel array 1210 and a second substrate including the DVS pixel array 1310 may be electrically connected by solder balls 5 in a flip-chip manner. Alternatively, a first substrate including the CIS pixel array 1210 and a second substrate including the DVS pixel array 1310 may be electrically connected by wires. Alternatively, a first substrate including the CIS pixel array 1210 and a second substrate including the DVS pixel array 1310 may be electrically connected by TSVs. Alternatively, a first substrate including the CIS pixel array 1210 and a second substrate including the DVS pixel array 1310 may be electrically connected by Cu-to-Cu bonding. However, the above coupling methods are exemplary, and the electrical connection is not limited to the above coupling methods.

[0086] The CIS pixel 1211 includes a photoelectric conversion device PSD, which includes a first impurity implantation region 2 and a second impurity implantation region 3. The first impurity implantation region 2 and the second impurity implantation region 3 may be doped with different impurities. In an embodiment, the first impurity implantation region 2 may be doped with a p-type impurity, and the second impurity implantation region 3 may be doped with an n-type impurity. When light is incident on the photoelectric conversion device PSD through the lens 1201, electron-hole pairs EHP corresponding to the intensity of the absorbed light are generated.

[0087] The CIS pixel 1211 includes a transfer transistor TG and a floating diffusion region FD, for example, as described above with respect to Figure 3 The CIS pixel 1211 may further include a reset transistor RT, a driving transistor DT, and a selection transistor ST, for example, also as described above with respect to Figure 3As described above, when the transfer transistor TG is turned on in response to a transfer signal VTG applied to the gate electrode of the transfer transistor TG, charges generated in the first impurity implantation region 2 and the second impurity implantation region 3 can move to the floating diffusion region FD. The charges in the floating diffusion region FD are transmitted to the DVS pixel 1311 through the internal wire 4, the solder ball 5, and the internal wire 6.

[0088] The DVS pixel 1311 may include a photosensor 1313 and a DVS pixel back-end circuit 1315. In an embodiment, one DVS pixel 1311 may determine whether the detected event is an event of decreasing light intensity or an event of increasing light intensity based on the charges received from a plurality of photoelectric conversion devices PSD. Information about the determined event may be output as a signal through the internal wire 7 (e.g., output to the CIS peripheral circuit, the DVS peripheral circuit, or Figure 1 the image signal processor 1100).

[0089] Meanwhile, Figure 8 An example in which the CIS pixel array 1210 and the DVS pixel array 1310 are directly electrically connected as upper and lower layers is shown, but the configuration is not limited thereto. For example, at least one of the image signal processor 1100, the CIS peripheral circuit, and the DVS peripheral circuit may be inserted between the CIS pixel array 1210 and the DVS pixel array 1310. However, in any case, components for transmitting the charges in the floating diffusion region FD to the DVS pixel 1311 (i.e., internal wires such as the internal wire 4, the internal wire 5, and the internal wire 6) may be provided as in Figure 8 the configuration.

[0090] As Figure 8 shown, the size of the photoelectric conversion device PSD implemented using the first impurity implantation region 2 and the second impurity implantation region 3 is relatively large, resulting in an increase in the chip size. However, according to an embodiment of the present disclosure, the DVS pixel 1311 shares the photoelectric conversion devices of a plurality of CIS pixels 1211. Therefore, since the DVS pixel 1311 does not implement an additional photoelectric conversion device, the size of the image sensor can be reduced and the manufacturing cost can be lowered.

[0091] Figure 9 A circuit diagram of an image sensor according to an embodiment of the present disclosure is shown. The image sensor 1000 includes a CIS pixel 1211 and a DVS pixel 1311. In Figure 9 this case, four CIS pixels 1211 are commonly connected to one DVS pixel 1311. However, as described above, the connection ratio between the CIS pixel and the DVS pixel may be set differently according to their sizes.

[0092] The CIS pixel 1211 is configured to output an output voltage VOUT corresponding to the charge accumulated in the floating diffusion region FD. Refer to Figure 3 for a description of the structure and operation of the CIS pixel 1211. However, different from Figure 3 , the floating diffusion region FD of the CIS pixel 1211 can be connected to the DVS pixel 1311 through a reset transistor RT. Specifically, the floating diffusion region FD can be connected through the reset transistor RT to a component (e.g., SW1 and / or SW2) for changing the operation mode of the image sensor 1000. That is, according to the operation mode corresponding to the open or closed state of the switches SW1 and SW2, the CIS pixel 1211 can be selectively connected to the power supply voltage VDD or the feedback transistor FB.

[0093] The DVS pixel 1311 is configured to determine whether the detected event is a turn-on event or a turn-off event based on the charge generated by the photoelectric conversion device PSD of the CIS pixel 1211. Refer to Figure 5 for a description of the structure and operation of the DVS pixel 1311. However, different from the DVS pixel 1311 shown in Figure 5 and Figure 6 , the DVS pixel 1311 may further include components (e.g., a first switch SW1 and a second switch SW2) for changing the operation mode of the image sensor 1000. The first switch SW1 and the second switch SW2 can be controlled by a switch control signal SWC generated by the image signal processor 1100 or the row AER circuit 1330 (see Figure 4 ).

[0094] In an embodiment, the first switch SW1 and the second switch SW2 may not be closed or opened simultaneously in the same period. For example, when the first switch SW1 is implemented with an NMOS transistor, the second switch SW2 may be implemented with a PMOS transistor (and vice versa). In this case, the first switch SW1 and the second switch SW2 can be controlled by one switch control signal SWC.

[0095] In an embodiment, the first switch SW1 and the second switch SW2 can be implemented with the same type of switch. For example, each of the first switch SW1 and the second switch SW2 can be implemented with an NMOS transistor. In this case, a component (e.g., an inverter) for inverting the switch control signal SWC can be further provided so that the first switch SW1 and the second switch SW2 are not closed or opened simultaneously in the same period. For example, the switch control signal SWC can be applied to the first switch SW1, and the inverted switch control signal SWC can be applied to the second switch SW2.

[0096] In an embodiment, the first switch SW1 and the second switch SW2 may be implemented with the same type of switch. For example, control signals for controlling the first switch SW1 and the second switch SW2 may be respectively applied to the first switch SW1 and the second switch SW2.

[0097] Meanwhile, the first switch SW1 and the second switch SW2 are exemplary. That is, in other embodiments, various components that selectively connect the CIS pixel 1211 to the power supply voltage VDD or the feedback transistor FB may be employed. In other embodiments, the first switch SW1 and the second switch SW2 may be disposed outside the DVS pixel 1311, or may be disposed within the CIS pixel 1211. That is, Figure 9 the shown construction and layout of the first switch SW1 and the second switch SW2 are not intended to limit the construction. The construction and operation of the above-described first switch SW1 and second switch SW2 may be applied to the embodiments described below.

[0098] Figure 10 is a diagram showing Figure 9 the image sensor operating in the first mode.

[0099] In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 is closed by the switch control signal SWC, and the second switch SW2 is opened by the switch control signal SWC. In this case, the power supply voltage VDD is applied to the drain electrode of the reset transistor RT through the interconnector IC. During the period when the CIS pixel 1211 is reset, when the reset transistor RT is turned on by the reset signal VRST, the floating diffusion region FD may be reset to the power supply voltage VDD. Conversely, in the first mode, the remaining components of the DVS pixel 1311 other than the first switch SW1 and the second switch SW2 do not operate.

[0100] Figure 11 is a diagram showing Figure 9 the image sensor operating in the second mode.

[0101] In the second mode, the image sensor 1000 may operate in the DVS mode. The first switch SW1 is opened by the switch control signal SWC, and the second switch SW2 is closed by the switch control signal SWC. When the transfer transistor TG is turned on, the charge generated by the photoelectric conversion device PSD moves to the floating diffusion region FD. When the reset transistor RT is turned on by the reset signal VRST, the charge accumulated in the floating diffusion region FD is input to the logarithmic amplifier LA. That is, in the second mode, the remaining components of the CIS pixel 1211 other than the photoelectric conversion device PSD, the transfer transistor TG, and the reset transistor RT do not operate. When the photocurrent IP is generated by the movement of the charge, the DVS pixel 1311 may operate.

[0102] Figure 12 Shows a circuit diagram of an image sensor according to an embodiment of the present disclosure.

[0103] The construction and operation of the image sensor 1000 are similar to those described with reference to Figures 9 to 11 However, different from the embodiment of Figures 9 to 11 , the CIS pixel 1211 may further include a switching transistor SWT. The DVS pixel 1311 may only include a first switch SW1. In an embodiment, the image signal processor 1100 (refer to Figure 1 ) or the row decoder 1220 (refer to Figure 2 ) may generate a DVS enable signal EN_DVS for controlling the switching transistor SWT.

[0104] In the first mode, the image sensor 1000 may operate in the CIS mode. The switching transistor SWT is turned off by the DVS enable signal EN_DVS, and the remaining components of the CIS pixel 1211 operate as in a general CIS pixel. The DVS pixel 1311 does not work.

[0105] In the second mode, the image sensor 1000 may operate in the DVS mode. The switching transistor SWT is turned on by the DVS enable signal EN_DVS. The remaining components of the CIS pixel 1211 except for the photoelectric conversion device PSD and the switching transistor SWT do not work. The first switch SW1 is also closed by the switch control signal SWC. As the charge generated by the photoelectric conversion device PSD moves, a photocurrent IP is generated. When the photocurrent IP is input to the logarithmic amplifier LA, the DVS pixel 1311 may work.

[0106] Figure 13 Shows a circuit diagram of an image sensor according to an embodiment of the present disclosure. Figure 13 The embodiment of Figure 12 is similar to the embodiment of

[0107] in that the DVS pixel 1311 includes a first switch SW1 and the CIS pixel 1211 includes a switching transistor SWT. However, the switching transistor SWT may be connected to the floating diffusion region FD. Figure 12 In the first mode, the image sensor 1000 may operate in the CIS mode. The switching transistor SWT is turned off by the DVS enable signal EN_DVS, and the remaining components of the CIS pixel 1211 operate as in a general CIS pixel. The DVS pixel 1311 does not work. That is, in the first mode, the operation of the CIS pixel 1211 is the same as that of the embodiment of

[0108] In the second mode, the image sensor 1000 may operate in the DVS mode. The switching transistor SWT is turned on by the DVS enable signal EN_DVS. The remaining components of the CIS pixel 1211 other than the photoelectric conversion device PSD, the transfer transistor TG, and the switching transistor SWT do not operate. That is, Figure 13 The embodiment of Figure 12 differs from the embodiment of

[0109] Figure 14 in that the transfer transistor TG operates. The first switch SW1 is also turned on by the switch control signal SWC. As a photocurrent IP is generated with the movement of the charge generated by the photoelectric conversion device PSD, the DVS pixel 1311 may operate.

[0110] The CIS pixel 1211 may include a photoelectric conversion device PSD, a reset transistor RT, a driving transistor DT, and a selection transistor ST. That is, different from the above embodiment, the CIS pixel 1211 includes three transistors and does not include a transfer transistor (e.g., Figure 9 TG of

[0111] In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 is closed by the switch control signal SWC, and the second switch SW2 is opened by the switch control signal SWC. The charge generated by the photoelectric conversion device PSD may be directly transferred to the floating diffusion region FD. The process of outputting an output voltage VOUT corresponding to the charge of the floating diffusion region FD when the selection transistor ST is turned on by the selection signal VSEL is similar to the process described with reference to Figure 3 the embodiment of

[0112] In the second mode, the image sensor 1000 may operate in the DVS mode. The first switch SW1 is opened by the switch control signal SWC, and the second switch SW2 is closed by the switch control signal SWC. The reset transistor RT is turned on by the reset signal VRST. As a photocurrent IP is generated with the movement of the charge generated by the photoelectric conversion device PSD, the DVS pixel 1311 may operate.

[0113] Figure 15 shows a circuit diagram of an image sensor according to an embodiment of the present disclosure.

[0114] The CIS pixel 1211 may include a photoelectric conversion device PSD, a transfer transistor TG, a reset transistor RT, a drive transistor DT, a first selection transistor ST1, and a second selection transistor ST2. That is, the CIS pixel 1211 may have a five-transistor (5TR) structure. The second selection transistor ST2 is turned on by a selection signal VSEL and transmits a transfer signal VTG to the gate electrode of the transfer transistor TG. The gate electrodes of the first selection transistor ST1 and the second selection transistor ST2 may be interconnected to receive the selection signal VSEL.

[0115] In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 is closed by a switch control signal SWC, and the second switch SW2 is opened by the switch control signal SWC. In order to transfer the charge generated by the photoelectric conversion device PSD to the floating diffusion region FD, the selection signal VSEL may be applied to the first selection transistor ST1 and the second selection transistor ST2. When the second selection transistor ST2 is turned on, the transfer signal VTG is applied to the transfer transistor TG, and the transfer transistor TG is turned on. In this case, the charge is transferred to the floating diffusion region FD. Except for adding the second selection transistor ST2, the operation of the CIS pixel 1211 is similar to the operation described in the embodiment with reference to Figures 9 to 11 the operation described in the embodiment with reference to

[0116] In the second mode, the image sensor 1000 may operate in the DVS mode. The second selection transistor ST2 is turned on by the selection signal VSEL. When the transfer signal VTG is applied to the gate electrode of the transfer transistor TG, the transfer transistor TG is turned on. The reset transistor RT is turned on by a reset signal VRST. The first switch SW1 is opened by the switch control signal SWC, and the second switch SW2 is closed by the switch control signal SWC. As a photocurrent IP is generated with the movement of the charge generated by the photoelectric conversion device PSD, the DVS pixel 1311 may operate based on the photocurrent IP.

[0117] Figure 16 shows Figure 2 the circuit diagram of the structure of the CIS pixel of

[0118] The CIS pixel 1211 may include photoelectric conversion devices PSD1 to PSD4, transfer transistors TG1 to TG4, a reset transistor RT, a drive transistor DT, and a selection transistor ST. The first photoelectric conversion device PSD1, the first transfer transistor TG1, the reset transistor RT, the drive transistor DT, and the selection transistor ST may constitute a first sub-CIS pixel 1211a. Figure 16An example is shown where the first sub-CIS pixel 1211a only surrounds the first photoelectric conversion device PSD1 and the first transfer transistor TG1, but this is for simplicity of explanation. As described above, the second photoelectric conversion device PSD2, the second transfer transistor TG2, the reset transistor RT, the drive transistor DT, and the selection transistor ST may form the second sub-CIS pixel 1211b. The third sub-CIS pixel 1211c and the fourth sub-CIS pixel 1211d have the same structure as the above-described structure.

[0119] The first sub-CIS pixel 1211a to the fourth sub-CIS pixel 1211d may share the floating diffusion region FD. In an embodiment, the first sub-CIS pixel 1211a may include a green filter, the second sub-CIS pixel 1211b may include a blue filter, the third sub-CIS pixel 1211c may include a red filter, and the fourth sub-CIS pixel 1211d may include a green filter. The red filter may transmit light in the red wavelength band, the green filter may transmit light in the green wavelength band, and the blue filter may transmit light in the blue wavelength band.

[0120] In an embodiment, the first sub-CIS pixel 1211a to the fourth sub-CIS pixel 1211d may operate sequentially. For example, in the operation of the first sub-CIS pixel 1211a, when the first transfer transistor TG1 is turned on by the first transfer signal VTG1, the charge generated by the first photoelectric conversion device PSD1 is transferred to the floating diffusion region FD. When the selection transistor ST is turned on by the selection signal VSEL, an output voltage VOUT corresponding to the charge in the floating diffusion region FD is output. When the reset transistor RT is turned on by the reset signal VRST, the floating diffusion region FD is reset.

[0121] After the operation of the first sub-CIS pixel 1211a, the second sub-CIS pixel 1211b may operate similarly to the first sub-CIS pixel 1211a. The third sub-CIS pixel 1211c and the fourth sub-CIS pixel 1211d may operate similarly to the first sub-CIS pixel 1211a.

[0122] However, the layout of the color filters in the pixel group, the number of CIS pixels commonly connected to the floating diffusion region FD, the structure of the pixel group, and the operation of the pixel group are exemplary. The structure is not limited thereto. For example, this structure may be applied to CIS image sensors of various structures in which multiple photoelectric conversion devices share the floating diffusion region FD.

[0123] Figure 17 A circuit diagram of an image sensor according to an embodiment of the present disclosure is shown.

[0124] Figure 17 The CIS pixel 1211 shown in Figure 16is substantially the same as the CIS pixel 1211. Thus, Figure 17 The components of Figure 16 can be referred to as the first sub-CIS pixel 1211a, the second sub-CIS pixel 1211b, the third sub-CIS pixel 1211c, and the fourth sub-CIS pixel 1211d, similar to the components of Figure 16 For clarity, the reference numerals 1211a, 1211b, 1211c, and 1211d shown in

[0125] In the first mode, the image sensor 1000 can operate in the CIS mode. The first switch SW1 is closed by the switch control signal SWC, and the second switch SW2 is opened by the switch control signal SWC. The operation of the sub-CIS pixels constituting the CIS pixel 1211 in the CIS mode has been described with reference to Figure 16 Therefore, redundant descriptions are omitted.

[0126] In the second mode, the image sensor 1000 can operate in the DVS mode. The transfer transistors TG1 to TG4 are turned on in response to the transfer signals VTG1 to VTG4 applied to the gate electrodes of the transfer transistors TG1 to TG4. The reset transistor RT is turned on by the reset signal VRST. The first switch SW1 is opened by the switch control signal SWC, and the second switch SW2 is closed by the switch control signal SWC. As the photocurrent IP is generated with the movement of the charges generated by the photoelectric conversion devices PSD1 to PSD4, the DVS pixel 1311 can operate based on the photocurrent IP.

[0127] In an embodiment, only a part of the transfer transistors TG1 to TG4 can be turned on to adjust the sensitivity (or intensity) of the received light. Different from the above embodiment, in Figure 17 the embodiment of

[0128] Figure 18 shows an image sensor according to an embodiment of the present disclosure.

[0129] The image sensor 1000 includes a plurality of photoelectric conversion devices PSD, a first transistor T1, a second transistor T2, a logarithmic current source ILOG, and a DVS pixel backend circuit 1315. In an embodiment, Figure 18Only the components associated with generating an event signal among all components of the image sensor are shown. That is, Figure 18 the components shown in Figure 18 correspond to the components of the image sensor that operate in DVS mode, and some components of the CIS pixels are not shown.

[0130] Hereinafter, the operation of the shown components will be described. The second transistor T2 can be turned on by a photocurrent IP generated by charges of a plurality of photoelectric conversion devices PSD. The first transistor T1 can be turned on by a logarithmic voltage VLOG based on a logarithmic current source ILOG. Here, the amplitude of the logarithmic voltage VLOG can have a value on a logarithmic scale. For example, the node that outputs the current of the logarithmic current source ILOG is referred to as the "logarithmic voltage node".

[0131] In an embodiment, the logarithmic current source ILOG can be a component of a DVS pixel. The first transistor T1, the second transistor T2, and the photoelectric conversion device PSD can be components of a CIS pixel. According to Figure 18 an embodiment, a DVS pixel may not include any other components (e.g., the first transistor T1 and the second transistor T2) and the photoelectric conversion device PSD. Thus, the size of a general DVS pixel can be further reduced. Hereinafter, the structure of an image sensor in which DVS pixels share some components of CIS pixels will be described with reference to Figure 19 Figure 19 .

[0132] Figure 19 A circuit diagram of an image sensor according to an embodiment of the present disclosure is shown. In an embodiment, Figure 19 a circuit structure for implementing Figure 18 is shown in an image sensor 1000. The image sensor 1000 includes CIS pixels 1211 and DVS pixels 1311. Figure 19 An embodiment in which four CIS pixels 1211 are commonly connected to one DVS pixel 1311 is shown in Figure 19 .

[0133] The CIS pixel 1211 is configured to output an output voltage VOUT corresponding to the charges accumulated in the floating diffusion region FD. The structure and operation of the CIS pixel 1211 are substantially the same as those described with reference to Figure 9 Figure 9 for the structure and operation of the CIS pixel 1211. However, there may be differences in the connection between the CIS pixel 1211 and the DVS pixel 1311. Specifically, the gate electrode of the reset transistor RT can be connected to a component (e.g., SW1 and / or SW2) for changing the operation mode of the image sensor 1000 through a first interconnector IC1. Specifically, one end of the driving transistor DT can be connected to a component (e.g., SW2 and / or switch SW3) for changing the operation mode of the image sensor 1000 through a second interconnector IC2.

[0134] The DVS pixel 1311 is configured to determine whether the detected event is a turn-on event or a turn-off event based on the charge generated by the photoelectric conversion device PSD of the CIS pixel 1211. However, the DVS pixel 1311 according to the above embodiment does not include the photoelectric conversion device PSD; in addition, the DVS pixel 1311 according to the Figure 19 embodiment does not include transistors (e.g., Figure 18 T1 and T2). Instead, the DVS pixel 1311 may further include components (e.g., the first switch SW1 to the third switch SW3) for changing the operation mode of the image sensor 1000. The first switch SW1 to the third switch SW3 can be controlled by a switch control signal SWC generated by the image signal processor 1100 or the row AER circuit 1330 (refer to Figure 4 ).

[0135] Meanwhile, the image sensor 1000 may include a fourth switch SW4 for selectively providing the power supply voltage VDD that will be applied to the driving transistor DT in the CIS mode. For example, the fourth switch SW4 may be connected to the second interconnector IC2 and may selectively supply the power supply voltage VDD to the driving transistor DT. For example, the first switch SW1 to the fourth switch SW4 may be referred to as a "switch circuit".

[0136] Figure 20 is a diagram showing Figure 19 the image sensor operating in the first mode.

[0137] In the first mode, the image sensor 1000 may operate in the CIS mode. The first switch SW1 can be closed or opened by the switch control signal SWC. Specifically, the first switch SW1 can be closed to reset the floating diffusion region FD. The second switch SW2 and the third switch SW3 are open. In this case, the fourth switch SW4 can be closed.

[0138] Figure 21 is a diagram showing Figure 19 the image sensor operating in the second mode.

[0139] In the second mode, the image sensor 1000 may operate in the DVS mode. The first switch SW1 and the fourth switch SW4 are opened by the switch control signal SWC, and the second switch SW2 and the third switch SW3 are closed by the switch control signal SWC. That is, the gate electrode of the reset transistor RT and the drain electrode of the driving transistor DT can be connected to the logarithmic voltage node. The transfer transistor TG is turned on by the transfer signal VTG.

[0140] The source electrode of the selection transistor ST that outputs its output voltage VOUT can be grounded. Although not shown for clarity of illustration, components (e.g., switches) can be included for selectively connecting the source electrode of the selection transistor ST to a ground terminal or a column line (e.g., Figure 3 CL1).

[0141] By comparing the circuit diagram corresponding to the switching state of Figure 21 with the circuit diagram of Figure 18 , it can be understood that the image sensor 1000 of Figure 18 is similar to the image sensor 1000 of Figure 21 . That is, Figure 18 the first transistor T1 and the second transistor T2 of Figure 21 correspond to the reset transistor RT and the drive transistor DT of

[0142] Figure 22 shows a circuit diagram of an image sensor according to an embodiment of the present disclosure.

[0143] Figure 22 The embodiment of Figures 19 to 21 is similar to the embodiment of Figures 19 to 21 . However, compared with the embodiment of Figure 22 , the embodiment of

[0144] can be different in the construction and layout of the switches SW1 to SW3. In the embodiment, according to the operation mode, the third switch SW3 can be selectively connected to the power supply voltage VDD or the logarithmic current source ILOG. For example, the third switch SW3 can be connected to the power supply voltage VDD in the first mode and can be connected to the logarithmic current source ILOG in the second mode. Figures 19 to 22 However, the construction for applying the reset signal VRST to the gate electrode of the reset transistor RT, applying the power supply voltage VDD to the drive transistor DT, and connecting the logarithmic current source ILOG to the gate electrodes of the drive transistor DT and the reset transistor RT in the first mode is not limited thereto. That is, various switch constructions for implementing the circuit structure of Figure 18 other than the embodiment of

[0145] Figure 23 shows a circuit diagram of an image sensor according to an embodiment of the present disclosure.

[0146] The image sensor 1000 includes a plurality of photoelectric conversion devices PSD, a first transistor T1, a second transistor T2, a logarithmic current source ILOG, and a DVS pixel backend circuit 1315. In the embodiment, Figure 23 only the components associated with generating the event signal among all the components of the image sensor are shown. That is,Figure 23 The components shown correspond to the components of the image sensor that operate in DVS mode, and some components of the CIS pixels are not shown.

[0147] Figure 23 The circuit diagram of is similar to Figure 18 the circuit diagram of. However, the first transistor T1 can be replaced by a PMOS transistor, and one end of the first transistor T1 is connected to the logarithmic voltage node of the current output from the logarithmic current source ILOG. The logarithmic current source ILOG can be a component of the DVS pixel, and the first transistor T1, the second transistor T2, and the photoelectric conversion device PSD can be components of the CIS pixel. The second transistor T2 can be turned on by the photocurrent IP generated by the charge generated by the photoelectric conversion device PSD. The first transistor T1 can be turned on by a separate voltage "V". The logarithmic voltage node can have a voltage value with a logarithmic scale.

[0148] Figure 24 The circuit diagram of an image sensor according to an embodiment of the present disclosure is shown. In the embodiment, Figure 24 is shown for implementing Figure 23 the circuit structure of the image sensor 1000. The image sensor 1000 includes CIS pixels 1211 and DVS pixels 1311.

[0149] The structure of the CIS pixel 1211 is similar to Figure 19 the structure of. However, the reset transistor RT can be implemented by a PMOS transistor. One end of the reset transistor RT can be connected to the components (such as SW1 and / or SW2) for changing the operation mode of the image sensor 1000 through the first interconnector IC1. One end of the driving transistor DT can be connected to the components (such as SW2 and / or SW3) for changing the operation mode of the image sensor 1000 through the second interconnector IC2.

[0150] In addition to supplying the power supply voltage VDD to the CIS pixel 1211 through the first switch SW1, Figure 24 the structure of the DVS pixel 1311 of is the same as Figure 19 the structure of. Therefore, redundant descriptions will be omitted.

[0151] In the first mode, the image sensor 1000 can operate in CIS mode. During the period for resetting the floating diffusion region FD, the first switch SW1 can be closed through the switch control signal SWC, and the first switch SW1 can be opened during the remaining periods. The second switch SW2 and the third switch SW3 are opened. In this case, the fourth switch SW4 can be closed.

[0152] In the second mode, the image sensor 1000 can operate in the DVS mode. The first switch SW1 and the fourth switch SW4 are turned off by the switch control signal SWC, and the second switch SW2 and the third switch SW3 are turned on by the switch control signal SWC. That is, one end of the reset transistor RT and one end of the driving transistor DT can be connected to the logarithmic voltage node. The transfer transistor TG is turned on by the transfer signal VTG. The reset transistor RT is turned on by the reset signal VRST.

[0153] According to the above embodiments, the DVS pixel of the present disclosure does not include a photoelectric conversion device. Instead, the DVS pixel determines the type of event by using the photoelectric conversion device PSD of the CIS pixel. In addition, in some embodiments, the DVS pixel without PSD does not include some transistors and uses the transistors of the CIS pixel. Therefore, the proposed structure can reduce the size of the image sensor and lower the manufacturing cost.

[0154] According to an embodiment of the present disclosure, the dynamic vision sensor uses a photoelectric conversion device included in a CMOS image sensor.

[0155] Therefore, the size of the image sensor can be reduced, and the manufacturing cost can be lowered.

[0156] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it is obvious to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure set forth in the appended claims.

Claims

1. An image sensor, comprising: A photoelectric conversion device that responds to incident light; A transfer transistor that is disposed between the photoelectric converter and a floating diffusion node and responds to a transfer control signal; A reset transistor that includes a first electrode connected to the floating diffusion node and a gate electrode that receives a reset control signal; A source follower that is configured to sense the floating diffusion node; A selection transistor that is connected to a column line; And A switch circuit that is configured to electrically connect a second electrode of the reset transistor to a power supply voltage or an event detection circuit in response to a mode control signal, wherein the event detection circuit is configured to detect a change in intensity of the incident light based on charges generated by the photoelectric conversion device.

2. The image sensor according to claim 1, wherein, The mode control signal indicates that the image sensor operates in an image sensing mode or an event detection mode, and wherein, when the image sensor operates in the image sensing mode, the second electrode of the reset transistor is connected to the power supply voltage via the switch circuit.

3. The image sensor according to claim 2, wherein, When the image sensor operates in the event detection mode, the second electrode of the reset transistor is connected to the event detection circuit via the switch circuit.

4. The image sensor according to claim 2, wherein, When the image sensor operates in the event detection mode, a photocurrent that responds to the incident light flows through the reset transistor, the transfer transistor, and the photoelectric conversion device.

5. The image sensor according to claim 2, wherein, When the image sensor operates in the event detection mode, the transfer control signal turns on the transfer transistor, and the reset control signal turns on the reset transistor during the event detection mode.

6. The image sensor according to claim 2, wherein, When the image sensor operates in the event detection mode, the selection transistor is turned off.

7. The image sensor according to claim 2, wherein the image sensing mode and the event detection mode of the photoelectric conversion device do not occur simultaneously.

8. An image sensor, comprising: A first image pixel unit that includes two or more pairs, each pair including a photoelectric conversion device and a transfer transistor, each photoelectric conversion device responding to incident light, and each transfer transistor being disposed between the corresponding photoelectric conversion device and a first shared floating diffusion node and responding to a transfer control signal; A first reset transistor that includes a first electrode connected to the first shared floating diffusion node and a gate electrode that receives a first reset control signal; And A switch circuit that is configured to connect a second electrode of the first reset transistor to a power supply voltage or an event detection circuit in response to a mode control signal, wherein the first image pixel unit further includes a first source follower that is configured to sense the first shared floating diffusion node and a first selection transistor that is connected to a first column line, wherein the event detection circuit is configured to detect a change in intensity of the incident light based on charges generated by the photoelectric conversion device.

9. The image sensor according to claim 8, wherein, The mode control signal indicates that the image sensor operates in an image sensing mode or an event detection mode, and wherein, when the image sensor operates in the image sensing mode, the second electrode of the first reset transistor is connected to the power supply voltage via the switch circuit.

10. The image sensor according to claim 9, wherein, When the image sensor operates in the event detection mode, the second electrode of the first reset transistor is connected to the event detection circuit via the switch circuit.

11. The image sensor according to claim 9, wherein, When the image sensor operates in the event detection mode, the transfer control signals turn on the transfer transistors respectively, and the first reset control signals turn on the first reset transistors respectively during the event detection mode.

12. The image sensor according to claim 9, wherein, When the image sensor operates in the event detection mode, photocurrents responsive to the incident light flow through the first reset transistors, the transfer transistors, and the photoelectric conversion devices.

13. The image sensor according to claim 9, further comprising: A second image pixel unit including two or more pairs, each pair including a photoelectric conversion device and a transfer transistor, each photoelectric conversion device responsive to the incident light, and each transfer transistor disposed between the corresponding photoelectric conversion device and a second shared floating diffusion node and responsive to a transfer control signal; and A second reset transistor including a first electrode connected to the second shared floating diffusion node and a gate electrode receiving a second reset control signal, wherein a second electrode of the second reset transistor is connected to a second electrode of the first reset transistor.

14. The image sensor according to claim 13, wherein during the event detection mode, the switching circuit is configured to connect the second electrodes of the first reset transistor and the second reset transistor to the power supply voltage or the event detection circuit in response to the mode control signal.

15. The image sensor according to claim 9, wherein the resolution of the image sensor for the event detection mode is less than the resolution of the image sensor for the image sensing mode.

16. The image sensor according to claim 13, wherein The second image pixel unit further includes a second source follower configured to sense the second shared floating diffusion node and a second selection transistor connected to a second column line.

17. The image sensor according to claim 16, wherein When the image sensor operates in the event detection mode, the first selection transistor and the second selection transistor are turned off.

18. An image sensor, comprising: A photoelectric conversion device responsive to incident light; A first transistor disposed between the photoelectric conversion device and a floating diffusion node and responsive to a transfer control signal; A second transistor including a first electrode connected to the floating diffusion node and a gate electrode receiving a reset control signal; A source follower configured to sense the floating diffusion node; A selection transistor connected to a column line; and An event detection circuit, wherein the second transistor is configured to reset the floating diffusion node for a first operation mode and enable photocurrent to flow from the event detection circuit to the photoelectric conversion device for a second operation mode, wherein the event detection circuit is configured to detect a change in intensity of the incident light based on charges generated by the photoelectric conversion device.

19. The image sensor according to claim 18, wherein The first operation mode is an image sensing mode, and the second operation mode is an event detection mode, and wherein, when the image sensor operates in the image sensing mode, the second transistor is connected to a power supply voltage to reset the floating diffusion node to the power supply voltage in response to the reset control signal.

20. The image sensor according to claim 19, wherein When the image sensor operates in the event detection mode, the photocurrent flows from the event detection circuit through the second transistor and the first transistor to the photoelectric conversion device.

21. The image sensor according to claim 20, wherein The photoelectric conversion device, the first transistor, and the second transistor are disposed in a first semiconductor substrate, and the event detection circuit is disposed in a second semiconductor substrate stacked on the first semiconductor substrate.

22. The image sensor according to claim 21, wherein The second semiconductor substrate does not have any photoelectric conversion devices.

23. A stacked image sensor, comprising: A first semiconductor substrate, which includes a first image pixel unit and a first reset transistor, the first image pixel unit including at least two pairs or more pairs, each pair including a photoelectric conversion device and a transfer transistor, each photoelectric conversion device responding to incident light, and each transfer transistor being disposed between the corresponding photoelectric conversion device and a shared floating diffusion node and responding to a transfer control signal, the first reset transistor including a first electrode connected to the shared floating diffusion node and a gate electrode receiving a first reset control signal; And A second semiconductor substrate, which is stacked on the first semiconductor substrate and includes a switch circuit configured to connect a second electrode of the first reset transistor to a power supply voltage or an event detection circuit in response to a mode control signal, wherein the first image pixel unit further includes a first source follower configured to sense the shared floating diffusion node and a first selection transistor connected to a first column line, wherein the event detection circuit is configured to detect a change in intensity of the incident light based on the charge generated by the photoelectric conversion device.

24. The stacked image sensor according to claim 23, wherein the first semiconductor substrate further comprises: A second image pixel unit and a second reset transistor, the second image pixel unit including at least two pairs or more pairs, each pair including a photoelectric conversion device and a transfer transistor, each photoelectric conversion device responding to the incident light, and each transfer transistor being disposed between the corresponding photoelectric conversion device and a shared floating diffusion node and responding to a transfer control signal, the second reset transistor including a first electrode connected to the shared floating diffusion node and a gate electrode receiving a second reset control signal, and wherein a second electrode of the first reset transistor and a second electrode of the second reset transistor are connected to each other.

25. The stacked image sensor according to claim 24, wherein, The mode control signal instructs the stacked image sensor to operate in an image sensing mode or an event detection mode, wherein, when the stacked image sensor operates in the image sensing mode, the second electrodes of the first reset transistor and the second reset transistor are connected to the power supply voltage via the switch circuit.

26. The stacked image sensor according to claim 25, wherein, When the stacked image sensor operates in the event detection mode, the second electrodes of the first reset transistor and the second reset transistor are connected to the event detection circuit via the switch circuit.

27. The stacked image sensor according to claim 25, wherein, When the stacked image sensor operates in the event detection mode, a first photocurrent responding to the incident light flows through the first reset transistor, the transfer transistor, and the photoelectric conversion device included in the first image pixel unit, and a second photocurrent responding to the incident light flows through the second reset transistor, the transfer transistor, and the photoelectric conversion device included in the second image pixel unit.

Images