PCB board structure for mounting Type-C connector and its combination with Type-C connector

Abstract

The present application discloses a PCB board structure for placing a Type-c connector and a combination thereof with a Type-c connector, wherein the PCB board structure includes multiple sublayers, a first group of Type-c pads is provided on the top layer, and a second group of Type-c pads is provided on the bottom layer, the first group of Type-c pads includes a first row of Type-c pads located on the outside and a second row of Type-c pads located on the inside, the second group of Type-c pads includes a third row of Type-c pads located on the outside and a fourth row of Type-c pads located on the inside, the first row of Type-c pads and the third row of Type-c pads correspond to each other up and down, and the Type-c pads of the two are arranged alternately along the arrangement direction, the second row of Type-c pads and the fourth row of Type-c pads correspond to each other up and down, and the Type-c pads of the two are arranged alternately along the arrangement direction; the arrangement directions of the first row of Type-c pads and the third row of Type-c pads are opposite, and the arrangement directions of the second row of Type-c pads and the fourth row of Type-c pads are opposite; the Type-c connector is welded to the first group of Type-c pads when placed from the upper side, and is welded to the second group of Type-c pads when placed from the lower side.

Description

Technical Field

[0001] The present application relates to the technical field of Type-c connectors, and in particular to a PCB board structure for mounting a Type-c connector and a combination thereof with the Type-c connector. Background Art

[0002] At present, the existing technology can only achieve a single-sided mounting design for the Type-C interface of notebooks. Taking into account the structure and ID modeling issues of the notebook interface, the SMT mounting methods of the Type-C interface of different projects are different. One is to open the hole in the D shell, and the PCB board needs to be mounted on the bottom surface. The other is to open the hole in the C shell, and the PCB board needs to be mounted on the top surface. However, in the case of mounting the PCB board on the bottom or top surface, the existing technology can only use different PCB boards for mounting on the bottom and top surfaces respectively to adapt to different projects, and it is impossible to use the same PCB board to arbitrarily mount the Type-C connector to the corresponding position on its bottom or top surface. Summary of the Invention

[0003] The purpose of this application is to provide a PCB board structure for placing a Type-C connector, a combination of a PCB board structure and a Type-C connector, and an electronic device, which can use the same PCB board structure to arbitrarily place the Type-C connector at the corresponding position on the bottom or top layer.

[0004] To achieve the above-mentioned purpose, the PCB board structure for mounting a Typec connector provided by the present application is a stacked structure, comprising multiple sublayers, wherein the multiple sublayers include a top layer and a bottom layer, the top layer is provided with a first group of Typec pads, and the bottom layer is provided with a second group of Typec pads, the first group of Typec pads includes a first row of Typec pads located on the outside and a second row of Typec pads located on the inside, the second group of Typec pads includes a third row of Typec pads located on the outside and a fourth row of Typec pads located on the inside, the first row of Typec pads and the third row of Typec pads correspond to each other up and down, and the Typec pads of the first row of Typec pads and the Typec pads of the third row of Typec pads are arranged alternately along the arrangement direction, and the second The first row of Typec pads and the fourth row of Typec pads correspond to each other up and down, and the Typec pads of the second row of Typec pads and the Typec pads of the fourth row of Typec pads are alternately arranged along the arrangement direction; the arrangement directions of the first row of Typec pads and the third row of Typec pads are opposite, and the arrangement directions of the second row of Typec pads and the fourth row of Typec pads are opposite; DIP holes are respectively provided on both sides of the first group of Typec pads and the second group of Typec pads, and each DIP hole can be used for each pin of the same Typec connector to be inserted from the upper side and from the lower side thereof. The Typec connector is welded to the first group of Typec pads when placed from the upper side, and is welded to the second group of Typec pads when placed from the lower side.

[0005] Optionally, the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad in the first row of Type-c pads are respectively connected to two pairs of first high-speed traces on the top layer, and the two pairs of first high-speed traces are respectively routed from the relatively close DIP holes and the adjacent GND pads in the second row of Type-c pads to the inner side of the second row of Type-c pads;

[0006] Each GND pad in the first row of Type-C pads and the second row of Type-C pads is independently grounded;

[0007] The RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad in the third row of Type-c pads are respectively connected to two pairs of third high-speed traces of the bottom layer, and the two pairs of third high-speed traces are respectively routed from the relatively close DIP holes and the adjacent GND pads in the fourth row of Type-c pads to the inner side of the fourth row of Type-c pads;

[0008] Each GND pad in the third row of Type-C pads and the fourth row of Type-C pads is independently grounded.

[0009] Optionally, the multiple sub-layers include a first GND layer adjacent to the top layer and a second GND layer adjacent to the bottom layer;

[0010] Grounding plates are provided on both sides of the first group of Type-C pads on the top layer and on both sides of the second group of Type-C pads on the bottom layer, and the DIP holes on both sides of the top layer and the bottom layer are connected to the grounding plates of the top layer and the bottom layer and the first GND layer and the second GND layer;

[0011] The GND pads in the first row of Type-C pads and the GND pads in the third row of Type-C pads are respectively connected to the adjacent ground plates;

[0012] The GND pads in the second row of Typec pads and the adjacent GND pads in the fourth row of Typec pads are respectively connected to the top and bottom of the same ground via through traces, and the ground via is connected to the first GND layer and the second GND layer.

[0013] Optionally, the multiple sub-layers include a first GND layer adjacent to the top layer and a second GND layer adjacent to the bottom layer;

[0014] The RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad in the second row of TypeC pads are respectively connected to two pairs of second high-speed traces on the top layer;

[0015] The RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad in the fourth row of TypeC pads are respectively connected to two pairs of fourth high-speed traces of the bottom layer;

[0016] The top layer is provided with resistors, capacitors, and electrostatic protection devices on the paths of the two pairs of the first high-speed routing lines and the two pairs of the second high-speed routing lines, respectively. The top layer is also provided with a first chip, and the two pairs of the first high-speed routing lines and the two pairs of the second high-speed routing lines are respectively connected to the first chip;

[0017] The bottom layer is provided with resistors, capacitors, and electrostatic protection devices on the paths of the two pairs of the third high-speed routing lines and the two pairs of the fourth high-speed routing lines, respectively. The bottom layer is also provided with a second chip, and the two pairs of the third high-speed routing lines and the two pairs of the fourth high-speed routing lines are respectively connected to the second chip;

[0018] The high-speed lines are completely routed on the top layer or the bottom layer, or the high-speed lines are simultaneously routed on the top layer and the bottom layer and connected through high-speed line vias.

[0019] Optionally, the multiple sub-layers include a VBUS layer;

[0020] The VBUS pads in the first row of Type-C pads are respectively connected to adjacent VBUS pads in the second row of Type-C pads through first VBUS traces, and the VBUS pads in the second row of Type-C pads are connected to a first VBUS connection sheet arranged on the top layer;

[0021] The VBUS pads in the third row of Type-C pads are respectively connected to the adjacent VBUS pads in the fourth row of Type-C pads through second VBUS traces, and the VBUS pads in the fourth row of Type-C pads are connected to the second VBUS connection sheet arranged on the bottom layer;

[0022] A first VBUS through-hole is provided at a position corresponding to the adjacent first VBUS line and the second VBUS line, and the adjacent first VBUS line and the second VBUS line are connected to the VBUS layer through the first VBUS through-hole;

[0023] A second VBUS through-hole is provided at a position corresponding to the adjacent first VBUS connecting piece and the second VBUS connecting piece, and the adjacent first VBUS connecting piece and the second VBUS connecting piece are connected to the VBUS layer through the second VBUS through-hole;

[0024] The first VBUS connecting piece and the second VBUS connecting piece are respectively connected to VBUS capacitors, and the VBUS capacitors are grounded.

[0025] Optionally, at least two middle sub-layers of the plurality of sub-layers located between the top layer and the bottom layer are provided with windings;

[0026] The DN pads in the first row of Type-C pads are connected to the DN pads in the second row of Type-C pads through a DN trace provided on the top layer;

[0027] The DP pads in the third row of Type-C pads are connected to the DP pads in the fourth row of Type-C pads through DP traces provided on the bottom layer;

[0028] One of the SBU2 pad in the first row of Type-C pads and the CC2 pad in the third row of Type-C pads is connected to a first through-hole in the spacing area between the first row of Type-C pads and the second row of Type-C pads and between the third row of Type-C pads and the fourth row of Type-C pads through a first trace, and is connected to a corresponding winding of the corresponding middle sub-layer through the first through-hole, and the other is provided with a first blind hole at its location and is connected to a corresponding winding of the corresponding middle sub-layer through the first blind hole;

[0029] One of the DP pad in the first row of Type-C pads and the DN pad in the third row of Type-C pads is connected to a second through-hole located in the spacing area through a second trace and is connected to a corresponding winding of the corresponding middle sub-layer through the second through-hole, and the other is provided with a second blind hole at its location and is connected to a corresponding winding of the corresponding middle sub-layer through the second blind hole;

[0030] One of the CC2 pad in the first row of Typec pads and the SBU2 pad in the third row of Typec pads is connected to the third through hole located in the spacing area through a third trace and is connected to the corresponding winding of the corresponding middle sublayer through the third through hole, and the other is provided with a third blind hole at its location and is connected to the corresponding winding of the corresponding middle sublayer through the third blind hole.

[0031] Optionally, one of the top layer and the bottom layer is provided with a first OVP protection chip;

[0032] The first OVP protection chip is respectively connected to the first group of zero-ohm resistors through different traces located on the same layer as the first group of Type-C pads, and the traces corresponding to the SBU pad and the CC pad of one of the first group of Type-C pads and the second group of Type-C pads are connected to the first OVP protection chip through the first group of zero-ohm resistors;

[0033] Through holes are respectively provided at the locations of the different routings located between the first OVP protection chip and the first group of zero-ohm resistors, and a second group of zero-ohm resistors is provided on the other of the top layer and the bottom layer. Routes are connected between the second group of zero-ohm resistors and the corresponding through holes, and the routings corresponding to the SBU pads and CC pads of the other of the first group of Typec pads and the second group of Typec pads are connected to the corresponding second group of zero-ohm resistors.

[0034] Optionally, the multiple sublayers include a first GND layer adjacent to the top layer, a second GND layer adjacent to the bottom layer, and a plurality of intermediate sublayers located between the first GND layer and the second GND layer, the plurality of intermediate sublayers include a VBUS layer, and at least part of the plurality of intermediate sublayers are provided with SBU1 windings, SBU2 windings, CC1 windings, CC2 windings, DP windings, and DN windings for performing line connections between corresponding pads in the first group of Type-c pads and the second group of Type-c pads;

[0035] The first GND layer is hollowed out at positions corresponding to at least part of the devices on the high-speed line on the top layer, and a reference GND is set on an intermediate sublayer adjacent to the first GND layer among the multiple intermediate sublayers;

[0036] The second GND layer is hollowed out at positions corresponding to at least some devices on the high-speed line on the bottom layer, and a reference GND is set on an intermediate sublayer adjacent to the second GND layer among the multiple intermediate sublayers.

[0037] To achieve the above-mentioned objectives, the combination of a PCB board structure and a Type-c connector provided in the present application includes the PCB board structure and the Type-c connector as described above, and the Type-c connector is selectively placed on the upper or lower side of the PCB board structure.

[0038] To achieve the above-mentioned objectives, the electronic device provided in this application includes a combination of the PCB board structure and the Type C connector as described above.

[0039] The present application is provided with a first row of Typec pads and a third row of Typec pads corresponding to each other on the top and bottom layers of the PCB board structure, and a second row of Typec pads and a fourth row of Typec pads corresponding to each other on the top and bottom layers, respectively. The Typec pads of the first row of Typec pads and the Typec pads of the third row of Typec pads are arranged alternately along the arrangement direction, and the Typec pads of the second row of Typec pads and the Typec pads of the fourth row of Typec pads are arranged alternately along the arrangement direction; moreover, the arrangement directions of the first row of Typec pads and the third row of Typec pads are opposite, and the arrangement directions of the second row of Typec pads and the fourth row of Typec pads are opposite. In addition, the DIP holes provided in the PCB board structure can allow the pins of the same Typec connector to be inserted from its upper side and from its lower side. When the Typec connector is placed from the upper side, it is soldered to the first group of Typec pads, and when it is placed from the lower side, it is soldered to the second group of Typec pads. The first group of Typec pads and the second group of Typec pads can be connected to each other through multiple sublayers. With the help of the above-mentioned technical means, the present application can selectively place the Typec connector at the corresponding position of the top or bottom layer of the same PCB board structure. That is to say, the present application can meet the needs of different development projects and place the Typec connector at the top or bottom layer of the same PCB board structure without the need to develop different PCB board structures according to different development projects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of the L1 layer of the PCB board structure of an embodiment of the present application.

[0041] Figure 2 yes Figure 1 A partial enlarged view of .

[0042] Figure 3 It is a schematic diagram of the L2 layer of the PCB board structure of an embodiment of the present application.

[0043] Figure 4 It is a schematic diagram of the L3 layer of the PCB board structure of an embodiment of the present application.

[0044] Figure 5 It is a schematic diagram of the L4 layer of the PCB board structure of an embodiment of the present application.

[0045] Figure 6 It is a schematic diagram of the L5 layer of the PCB board structure of an embodiment of the present application.

[0046] Figure 7 It is a schematic diagram of the L6 layer of the PCB board structure of an embodiment of the present application.

[0047] Figure 8 It is a schematic diagram of the L7 layer of the PCB board structure of an embodiment of the present application.

[0048] Figure 9 It is a schematic diagram of the L8 layer of the PCB board structure of an embodiment of the present application.

[0049] Figure 10 yes Figure 9 A partial enlarged view of .

[0050] Figure 11 Schematic diagram showing the overlapping display of L1 layer and L8 layer of the PCB board structure in an embodiment of the present application.

[0051] Figure 12 This is a schematic diagram of the side-mounted components on the PCB board structure according to an embodiment of the present application.

[0052] Figure 13 This is a schematic diagram of the lower side mounting component of the PCB board structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to explain the technical content and structural features of the present application in detail, the following further describes the embodiments in conjunction with the accompanying drawings.

[0054] It should be noted that the terms "top", "bottom", "up", "down", "inside" and "outside" used in this application to express orientation and positional relationships are only used to facilitate the description of this application and should not be construed as limiting this application. Among them, one of the two outermost layers in the multiple sub-layers of the PCB board structure is the bottom layer, and the other is the top layer, that is, the bottom layer defined in this application can also be defined as the top layer, and correspondingly, the top layer defined in this application can also be defined as the bottom layer, and the two are relative; in addition, this application defines the direction in which the TypeC connector is inserted as "inside" and the opposite direction as "outside".

[0055] like Figures 1 to 13 As shown, the present application discloses a PCB board structure for placing a Type C connector.

[0056] The PCB board structure is a laminated structure including multiple sub-layers, including a top layer L1 and a bottom layer L8. In the example shown in the drawings, the PCB board structure includes eight sub-layers, but is not limited thereto.

[0057] The top layer L1 is provided with a first group of Typec pads, and the bottom layer L8 is provided with a second group of Typec pads. The first group of Typec pads includes a first row of Typec pads 1 located on the outside and a second row of Typec pads 2 located on the inside. The second group of Typec pads includes a third row of Typec pads 3 located on the outside and a fourth row of Typec pads 4 located on the inside.

[0058] The first row of Typec pads 1 and the third row of Typec pads 3 correspond to each other up and down (the up and down correspondence does not mean that the positions completely overlap, but that the positions are relative as a whole. In fact, the two are arranged alternately), and the Typec pads of the first row of Typec pads 1 and the Typec pads of the third row of Typec pads 3 are arranged alternately along the arrangement direction, the second row of Typec pads 2 and the fourth row of Typec pads 4 correspond to each other up and down, and the Typec pads of the second row of Typec pads 2 and the Typec pads of the fourth row of Typec pads 4 are arranged alternately along the arrangement direction; the arrangement directions of the first row of Typec pads 1 and the third row of Typec pads 3 are opposite, and the arrangement directions of the second row of Typec pads 2 and the fourth row of Typec pads 4 are opposite. That is, in the arrangement direction, the arrangement order of the Typec pads of the first row of Typec pads 1 and the Typec pads of the third row of Typec pads 3 is from one side to the other: the GND pad of the first row of Typec pads 1, the GND pad of the third row of Typec pads 3, the RX1+ pad of the first row of Typec pads 1, the TX2+ pad of the third row of Typec pads 3, the RX1- pad of the first row of Typec pads 1, the TX2- pad of the third row of Typec pads 3, the VBUS pad of the first row of Typec pads 1, the VBUS pad of the third row of Typec pads 3, the SBU2 pad of the first row of Typec pads 1, the CC2 pad of the third row of Typec pads 3, the DN pad of the first row of Typec pad 1, DP pad of the third row of Typec pad 3, DP pad of the first row of Typec pad 1, DN pad of the third row of Typec pad 3, CC2 pad of the first row of Typec pad 1, SBU2 pad of the third row of Typec pad 3, VBUS pad of the first row of Typec pad 1, VBUS pad of the third row of Typec pad 3, TX2- pad of the first row of Typec pad 1, RX1- pad of the third row of Typec pad 3, TX2+ pad of the first row of Typec pad 1, RX1+ pad of the third row of Typec pad 3, GND pad of the first row of Typec pad 1, GND pad of the third row of Typec pad 3.Similarly, in the arrangement direction, the arrangement order of the Typec pads of the second row of Typec pads 2 and the Typec pads of the fourth row of Typec pads 4 is from one side to the other: the GND pad of the fourth row of Typec pads 4, the GND pad of the second row of Typec pads 2, the RX2+ pad of the fourth row of Typec pads 4, the TX1+ pad of the second row of Typec pads 2, the RX2- pad of the fourth row of Typec pads 4, the TX1- pad of the second row of Typec pads 2, the VBUS pad of the fourth row of Typec pads 4, the VBUS pad of the second row of Typec pads 2, the SBU1 pad of the fourth row of Typec pads 4, the CC1 pad of the second row of Typec pads 2, the DN pads of the fourth row of Typec pads 4, DP pads of the second row of Typec pads 2, DP pads of the fourth row of Typec pads 4, DN pads of the second row of Typec pads 2, CC1 pads of the fourth row of Typec pads 4, SBU1 pads of the second row of Typec pads 2, VBUS pads of the fourth row of Typec pads 4, VBUS pads of the second row of Typec pads 2, TX1- pads of the fourth row of Typec pads 4, RX2- pads of the second row of Typec pads 2, TX1+ pads of the fourth row of Typec pads 4, RX2+ pads of the second row of Typec pads 2, GND pads of the fourth row of Typec pads 4, and GND pads of the second row of Typec pads 2. It should be noted that "alternating arrangement" in this application does not mean that adjacent pads must be completely staggered in the arrangement direction.

[0059] DIP holes 10 are provided on both sides of the first group of Typec pads and the second group of Typec pads. Each DIP hole 10 can be used for the pins (not shown) of the same Typec connector 9 to be inserted from its upper side and from its lower side. When the Typec connector 9 is placed from the upper side, it is soldered to the first group of Typec pads, and when it is placed from the lower side, it is soldered to the second group of Typec pads. In other words, the Typec connector 9 can share the DIP hole 10 when it is placed from the upper side of the PCB board structure and when it is placed from the lower side of the PCB board structure. The pins of the Typec connector 9 are the pins of the metal shell of the Typec connector 9.

[0060] At present, it is somewhat difficult for factories to place components on both sides of the PCB board structure with DIP holes 10; the level of solder paste also determines the placement position of the Type-c connector 9, so when designing the steel mesh file, the DIP hole 10 on the past layer needs to be specially processed. For example, when placing components on the top layer L1, the past layer at the corresponding position of the bottom layer L8 needs to be deleted; similarly, when placing components on the bottom layer L8, the past layer at the corresponding position of the top layer L1 needs to be deleted. This method ensures that the DIP hole will not be blocked by the solder paste on the other side when the components are placed in the furnace at the factory end, resulting in the inability to place the Type-c connector 9 on the different side.

[0061] The first group of Type-c pads and the second group of Type-c pads can achieve circuit connection through multiple sub-layers. In other words, whether the Type-c connector 9 is placed from the upper side or the lower side of the PCB board structure, the circuit layout of the PCB board structure on multiple sub-layers (component layout, surface routing combined with via connection, etc., vias can include through holes and blind holes, etc.) can be used to achieve the circuit connection required by the Type-c connector 9.

[0062] It should be noted that in this application, there is no restriction on the number of sub-layers, nor is there any restriction on the circuit layout on the PCB board structure. As long as the Typec connector 9 is placed on the top layer L1 or the bottom layer L8, normal circuit connection can be achieved through the first group of Typec pads and the corresponding circuit layout or the second group of Typec pads and the corresponding circuit layout.

[0063] The present application is provided with a first row of Typec pads 1 and a third row of Typec pads 3 corresponding to each other on the top layer L1 and the bottom layer L8 of the PCB board structure, and a second row of Typec pads 2 and a fourth row of Typec pads 4 corresponding to each other on the top layer L1 and the bottom layer L8, respectively. The Typec pads of the first row of Typec pads 1 and the Typec pads of the third row of Typec pads 3 are arranged alternately along the arrangement direction, and the Typec pads of the second row of Typec pads 2 and the Typec pads of the fourth row of Typec pads 4 are arranged alternately along the arrangement direction; moreover, the arrangement directions of the first row of Typec pads 1 and the third row of Typec pads 3 are opposite, and the arrangement directions of the second row of Typec pads 2 and the fourth row of Typec pads 4 are opposite. In addition, the DIP holes 10 provided in the PCB board structure can allow the pins of the same Typec connector 9 to be inserted from its upper side and from its lower side. When the Typec connector 9 is placed from the upper side, it is soldered to the first group of Typec pads, and when it is placed from the lower side, it is soldered to the second group of Typec pads. The first group of Typec pads and the second group of Typec pads can be connected to each other through multiple sublayers. By means of the above-mentioned technical means, the present application can selectively place the Type-c connector 9 at the corresponding position of the top layer L1 or bottom layer L8 of the same PCB board structure. In other words, the present application can meet the needs of different development projects and place the Type-c connector 9 at the top layer L1 or bottom layer L8 of the same PCB board structure, without having to develop different PCB board structures according to different development projects. On the basis of being able to selectively place the components on the upper side or the lower side, combined with the corresponding wiring settings of the multiple sub-layers of the PCB board structure, the line connection of the Type-c connector 9 placed on the upper side or the Type-c connector 9 placed on the lower side can be achieved.

[0064] In some embodiments, the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad in the first row of Type-c pads 1 are respectively connected to two pairs of first high-speed traces H1 on the top layer L1 trace. The two pairs of first high-speed traces H1 are respectively routed from relatively close DIP holes 10 and adjacent GND pads in the second row of Type-c pads 2 to the inner side of the second row of Type-c pads 2; each GND pad in the first row of Type-c pads 1 and the second row of Type-c pads 2 is independently grounded. The RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad in the third row of Type-c pads 3 are respectively connected to two pairs of third high-speed traces H3 on the bottom layer L8 trace. The two pairs of third high-speed traces H3 are respectively routed from relatively close DIP holes 10 and adjacent GND pads in the fourth row of Type-c pads 4 to the inner side of the fourth row of Type-c pads 4; each GND pad in the third row of Type-c pads 3 and the fourth row of Type-c pads 4 is independently grounded.

[0065] It's important to note that the "RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad are each connected to the two pairs of first high-speed traces H1 on the top layer L1" does not restrict first high-speed trace H1 to routing only on the top layer L1. It can also be routed on both the top layer L1 and the bottom layer L8, with the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad each connected to the portion of first high-speed trace H1 on the top layer L1. Similarly, the "RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad are each connected to the two pairs of third high-speed traces H3 on the bottom layer L8" does not restrict third high-speed trace H3 to routing only on the bottom layer L8. It can also be routed on both the top layer L1 and the bottom layer L8, with the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad each connected to the portion of third high-speed trace H3 on the bottom layer L8.

[0066] Because the existing routing method for the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad all uses through-holes to change layers for routing, and adjacent GND pads are connected to the same ground plate for grounding, when the first group of Type-C pads is provided on the top layer L1 of the PCB structure and the second group of Type-C pads is provided on the bottom layer L8, the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad located outside the top layer L1 and the bottom layer L8 cannot be routed. In this application, the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad on the top layer L1 are connected to two pairs of first high-speed traces H1 and are respectively routed from the relatively close DIP hole 10 and the adjacent GND pads in the second row of Typec pads 2 to the inner side of the second row of Typec pads 2, and each GND pad in the first row of Typec pads 1 and the second row of Typec pads 2 are independently grounded; the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad on the bottom layer L8 are connected to the two pairs of first high-speed traces H1 and are respectively routed from the relatively close DIP hole 10 and the adjacent GND pads in the second row of Typec pads 2 to the inner side of the second row of Typec pads 2, and each GND pad in the first row of Typec pads 1 and the second row of Typec pads 2 are independently ground The pads and TX2-pads connect two pairs of third high-speed traces H3 and are respectively routed from the relatively close DIP holes 10 and the adjacent GND pads in the fourth row of Typec pads 4 to the inner side of the fourth row of Typec pads 4, and each GND pad in the third row of Typec pads 3 and the fourth row of Typec pads 4 is independently grounded; thereby, the RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad of the bottom layer L8 and the top layer L1 of this application can all be routed at high speed.

[0067] Specifically, multiple sublayers include a first GND layer L2 adjacent to the top layer L1 and a second GND layer L7 adjacent to the bottom layer L8; the top layer L1 is provided with grounding plates G on both sides of the first group of Typec pads and the bottom layer L8 is provided with grounding plates G on both sides of the second group of Typec pads, and the DIP holes 10 on both sides are connected to the grounding plates G of the top layer L1 and the bottom layer L8 and the first GND layer L2 and the second GND layer L7; the GND pads in the first row of Typec pads 1 and the GND pads in the third row of Typec pads 3 are respectively connected to adjacent grounding plates G; the GND pads in the second row of Typec pads 2 and the adjacent GND pads in the fourth row of Typec pads 4 are respectively connected to the top and bottom of the same grounding through-hole K1 through wiring, and the grounding through-hole K1 is connected to the first GND layer L2 and the second GND layer L7. Through the above technical means, under the premise of achieving grounding of each GND pad, it is beneficial to limit the number of openings. It is understandable that the method of grounding each GND pad in the present application is not limited to the above method, as long as the purpose of grounding each GND pad can be achieved. For example, the GND pad can also be grounded by drilling a blind hole.

[0068] It should be noted that the definition of a GND layer in this application does not imply that there are no other structures on the same layer. In addition, the PCB structure may include other GND layers in addition to the first GND layer L2 and the second GND layer L7, and this application does not limit this.

[0069] Specifically, multiple sublayers include a first GND layer L2 adjacent to the top layer L1 and a second GND layer L7 adjacent to the bottom layer L8; the RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad in the second row of Typec pads 2 are respectively connected to two pairs of second high-speed traces H2 of the top layer L1; the RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad in the fourth row of Typec pads 4 are respectively connected to two pairs of fourth high-speed traces H4 of the bottom layer L8; the top layer L1 is provided with corresponding resistors, capacitors, and electrostatic protection devices on the paths of the two pairs of first high-speed traces H1 and the two pairs of second high-speed traces H2, and the top layer L1 is also provided with a first chip X1, two pairs of first high-speed traces H1 and two pairs of second high-speed traces H2 are respectively connected to the first chip X1; the bottom layer L8 is respectively provided with corresponding resistors, capacitors and electrostatic protection devices on the paths of two pairs of third high-speed traces H3 and two pairs of fourth high-speed traces H4. The bottom layer L8 is also provided with a second chip X2, and the two pairs of third high-speed traces H3 and two pairs of fourth high-speed traces H4 are respectively connected to the second chip X2; the high-speed traces are completely routed on the top layer L1 or the bottom layer L8, or the high-speed traces are simultaneously routed on the top layer L1 and the bottom layer L8 and connected through the high-speed line through hole K2 (that is, for each high-speed trace, it can be routed only on the top layer L1 or the bottom layer L8 as needed, or it can be routed on the top layer L1 and the bottom layer L8 at the same time).

[0070] Through the above technical means, the line connection of all RX pads and TX pads of the top layer L1 and all RX pads and TX pads of the bottom layer L8 is realized. In addition, since the high-speed lines are completely routed on the top layer L1 or the bottom layer L8, or the high-speed lines are routed on the top layer L1 and the bottom layer L8 at the same time and connected through at least one high-speed line through hole K2, the reliable transmission of high-speed signals can be guaranteed.

[0071] It's important to note that the phrase "RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad are connected to the two pairs of second high-speed traces H2 on the top layer L1" doesn't restrict H2 to routing only on the top layer L1. It can also route both on the top layer L1 and the bottom layer L8, with the RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad connected to the portion of the second high-speed trace H2 on the top layer L1. Similarly, the phrase "RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad are connected to the two pairs of fourth high-speed traces H4 on the bottom layer L8" doesn't restrict H4 to routing only on the bottom layer L8. It can also route both on the top layer L1 and the bottom layer L8, with the RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad connected to the portion of the fourth high-speed trace H4 on the bottom layer L8.

[0072] In a specific example, the top layer L1 is provided with a ground resistor R1, a capacitor C, an electrostatic protection device E, a zero-ohm resistor R0, etc. (to achieve jumper connection) along the paths of two pairs of first high-speed traces H1 and two pairs of second high-speed traces H2. In this example, one pair of first high-speed traces H1 and two pairs of second high-speed traces H2 are routed entirely on the top layer L1. The other pair of first high-speed traces H1 is routed to the bottom layer L8 through high-speed line vias K2, and then through another high-speed line via K2 back to the top layer L1, and ultimately connected to the first chip X1.

[0073] On the bottom layer L8, ground resistors R1, capacitors C, electrostatic protection devices E, and zero-ohm resistors R0 are provided along the paths of the two pairs of third high-speed traces H3 and the two pairs of fourth high-speed traces H4 (to achieve jumper connections). In this example, the two pairs of third high-speed traces H3 and the two pairs of fourth high-speed traces H4 are routed to the top layer L1 through high-speed line vias K2, then return to the bottom layer L8 through another high-speed line via K2, and ultimately connect to the second chip X2.

[0074] It is understandable that this application does not limit the routing method of high-speed wiring, the setting of chips and other devices, etc. Technical personnel in this field can adopt various different methods as long as normal functions can be achieved through line connection.

[0075] In some embodiments, the multiple sub-layers include a VBUS layer.

[0076] The VBUS pads in the first row of Typec pads 1 are respectively connected to the adjacent VBUS pads in the second row of Typec pads 2 through the first VBUS traces V1, and the VBUS pads in the second row of Typec pads 2 are connected to the first VBUS connecting piece P1 arranged on the top layer L1.

[0077] The VBUS pads in the third row of Typec pads 3 are respectively connected to the adjacent VBUS pads in the fourth row of Typec pads 4 through the second VBUS traces V2, and the VBUS pads in the fourth row of Typec pads 4 are connected to the second VBUS connecting piece P2 arranged on the bottom layer L8.

[0078] A first VBUS through hole K3 is provided at the position corresponding to the adjacent first VBUS trace V1 and the second VBUS trace V2 (that is, the first VBUS trace V1 and the second VBUS trace have upper and lower facing parts to set a common first VBUS through hole K3), and the adjacent first VBUS trace V1 and the second VBUS trace V2 are connected to the VBUS layer through the first VBUS through hole K3.

[0079] A second VBUS through hole K4 is provided at the position corresponding to the adjacent first VBUS connecting piece P1 and the second VBUS connecting piece P2 (that is, there are upper and lower opposite parts of the first VBUS connecting piece P1 and the second VBUS connecting piece P2 to set a common second VBUS through hole K4), and the adjacent first VBUS connecting piece P1 and the second VBUS connecting piece P2 are connected to the VBUS layer through the second VBUS through hole K4.

[0080] The first VBUS connecting piece P1 and the second VBUS connecting piece P2 are respectively connected to the VBUS capacitor Cv, and the VBUS capacitor Cv is grounded (the grounding method is not shown). Regarding the specific method of grounding the VBUS capacitor Cv, this application does not limit it, as long as grounding can be achieved. For example, the VBUS capacitor Cv connected to the first VBUS connecting piece P1 and the VBUS capacitor Cv connected to the second VBUS connecting piece P2 can be respectively connected to a trace, and the traces of the top layer L1 and the bottom layer L8 have a portion that is directly opposite to each other and a through hole is set at this position to connect to the GND layer through the through hole.

[0081] Through the above technical means, the present application can realize the line connection of all VBUS pads of the top layer L1 and the bottom layer L8, and basically will not affect the line setting of other pads.

[0082] It should be noted that the definition of the VBUS layer in this application does not mean that there are no other structures on the same layer. In addition, in addition to the VBUS layer, this application can also set up VBUS supplementary structures in other layers as needed, and the two can be connected through through holes.

[0083] In some embodiments, at least two middle sub-layers of the plurality of sub-layers located between the top layer L1 and the bottom layer L8 are provided with windings.

[0084] The DN pads in the first row of Typec pads 1 are connected to the DN pads in the second row of Typec pads 2 through the DN traces provided on the top layer L1, so that the two DN pads can share the traces, thereby saving space.

[0085] The DP pad in the third row of Typec pads 3 is connected to the DP pad in the fourth row of Typec pads 4 through the DP trace provided on the bottom layer L8, so that the two DP pads can share the trace, which saves space.

[0086] One of the SBU2 pads in the first row of Typec pads 1 and the CC2 pads in the third row of Typec pads 3 is connected to the first through-hole K5 in the spacing area between the first row of Typec pads 1 and the second row of Typec pads 2 and between the third row of Typec pads 3 and the fourth row of Typec pads 4 through the first trace 11 and is connected to the corresponding winding of the corresponding middle sub-layer through the first through-hole K5. The other is provided with a first blind hole K6 at the location where it is connected to the corresponding winding of the corresponding middle sub-layer through the first blind hole K6. Through this technical means, the adjacent SBU2 pads in the first row of Typec pads 1 and the CC2 pads in the third row of Typec pads 3 can both be wired out, and then line connection can be performed.

[0087] Specifically, a first blind hole K6 is provided at the position of the SBU2 pad in the first row of Typec pads 1 and is connected to the corresponding winding of the corresponding middle sub-layer through the first blind hole K6. The CC2 pad in the third row of Typec pads 3 is connected to the first through-hole K5 through the first trace 11 and is connected to the corresponding winding of the corresponding middle sub-layer through the first through-hole K5.

[0088] One of the DP pads in the first row of Type-c pads 1 and the DN pads in the third row of Type-c pads 3 is connected to the second through-hole K7 located in the spacing area through the second trace 12 and is connected to the corresponding winding of the corresponding middle sub-layer through the second through-hole K7. The other is located at a second blind hole K8 and is connected to the corresponding winding of the corresponding middle sub-layer through the second blind hole K8. Through this technical means, the DP pads in the adjacent first row of Type-c pads 1 and the DN pads in the adjacent third row of Type-c pads 3 can both be wired out, and thus line connection can be made.

[0089] Specifically, the DP pad in the first row of Typec pads 1 is connected to the second through-hole K7 through the second trace 12 and is connected to the corresponding winding of the corresponding middle sub-layer through the second through-hole K7. The DN pad in the third row of Typec pads 3 is located at a second blind hole K8 and is connected to the corresponding winding of the corresponding middle sub-layer through the second blind hole K8.

[0090] One of the CC2 pads in the first row of Type-C pads 1 and the SBU2 pads in the third row of Type-C pads 3 is connected to the third through-hole K9 located in the spacing area through the third trace 13 and is connected to the corresponding winding of the corresponding middle sub-layer through the third through-hole K9. The other is located at a third blind hole K10 and is connected to the corresponding winding of the corresponding middle sub-layer through the third blind hole K10. Through this technical means, the CC2 pads in the adjacent first row of Type-C pads 1 and the SBU2 pads in the adjacent third row of Type-C pads 3 can both be wired out, and thus line connection can be made.

[0091] Specifically, the CC2 pad in the first row of Typec pads 1 is connected to the third through-hole K9 through the third trace 13 and is connected to the corresponding winding of the corresponding middle sub-layer through the third through-hole K9. The SBU2 pad in the third row of Typec pads 3 is located at a third blind hole K10 and is connected to the corresponding winding of the corresponding middle sub-layer through the third blind hole K10.

[0092] Through the above-mentioned setting, the present application can realize the simultaneous output of the SBU2 pads, DN pads, DP pads and CC2 pads of the first row of Typec pads 1 located on the top layer L1 and the SBU2 pads, DN pads, DP pads and CC2 pads of the third row of Typec pads 3 located on the bottom layer L8, and then perform line connections respectively, so as to facilitate the realization of the double-sided Typec connector 9 of the present application.

[0093] In some embodiments, one of the top layer L1 and the bottom layer L8 is provided with a first OVP protection chip O; the first OVP protection chip O is connected to the first group of zero-ohm resistors R0 through different routing lines located on the same layer, and the routing lines corresponding to the SBU pads and CC pads of one of the first group of Typec pads and the second group of Typec pads are connected to the first OVP protection chip O through the first group of zero-ohm resistors R0, thereby realizing the line connection of the corresponding SBU pads and CC pads.

[0094] Through holes K11 are respectively provided at the locations of different routings between the first OVP protection chip O and the first group of zero-ohm resistors R0, and a second group of zero-ohm resistors R0 is provided on the other of the top layer L1 and the bottom layer L8. Routings are connected between the second group of zero-ohm resistors R0 and the through holes K11, and the routings corresponding to the SBU pads and CC pads of the other of the first group of Typec pads and the second group of Typec pads are connected to the second group of zero-ohm resistors R0, thereby realizing the line connection of the corresponding SBU pads and CC pads to the first OVP protection chip O.

[0095] Through the above technical means, the SBU pads and CC pads in the first group of Type-c pads and the second group of Type-c pads can be connected to the same OVP protection chip O, without the need to set up OVP protection chips O for the first group of Type-c pads and the second group of Type-c pads respectively. Of course, the present application can also set up corresponding OVP protection chips O for the first group of Type-c pads and the second group of Type-c pads respectively.

[0096] Specifically, to facilitate routing, each SBU pad and CC pad is routed through a layer-changing method using vias and is ultimately connected to the first set of zero-ohm resistors R0 or the second set of zero-ohm resistors R0.

[0097] In a specific example, the first OVP protection chip O is set on the bottom layer L8, and the wiring corresponding to the SBU pad and CC pad in the second group of Typec pads is connected to the first group of zero-ohm resistors R0, but it is not limited to this, as long as the wiring can be completed.

[0098] In some embodiments, the plurality of sublayers include a first GND layer L2 adjacent to the top layer L1, a second GND layer L7 adjacent to the bottom layer L8, and a plurality of intermediate sublayers located between the first GND layer L2 and the second GND layer L7. The plurality of intermediate sublayers include a VBUS layer. At least some of the plurality of intermediate sublayers are provided with SBU1 windings, SBU2 windings, CC1 windings, CC2 windings, DP windings, and DN windings for connecting the SBU pads and CC pads in the first group of Type-c pads and the second group of Type-c pads. In order to facilitate routing, vias can be provided for layer switching. The first GND layer L2 is hollowed out at the location of at least some of the devices on the high-speed routing path on the corresponding top layer L1, and a reference GND is provided for the intermediate sublayer adjacent to the first GND layer L2 among the plurality of intermediate sublayers. The second GND layer L7 is hollowed out at the location of at least some of the devices on the high-speed routing path on the corresponding bottom layer L8, and a reference GND is provided for the intermediate sublayer adjacent to the second GND layer L7 among the plurality of intermediate sublayers.

[0099] It should be noted that "at least part of the multiple intermediate sublayers are provided with SBU1 winding, SBU2 winding, CC1 winding, CC2 winding, DP winding and DN winding" means that any one of the SBU1 winding, SBU2 winding, CC1 winding, CC2 winding, DP winding and DN winding is provided in at least part of the multiple intermediate sublayers, and does not limit at least part of the intermediate sublayers to be provided with SBU1 winding, SBU2 winding, CC1 winding, CC2 winding, DP winding and DN winding at the same time.

[0100] By using at least some of the multiple intermediate sublayers to set up SBU1 windings, SBU2 windings, CC1 windings, CC2 windings, DP windings, and DN windings, it is convenient to achieve circuit connections between the SBU pads and CC pads in the first group of Type-C pads and the second group of Type-C pads. At the same time, by hollowing out the corresponding positions of the first GND layer L2 and the second GND layer L7, and setting reference GNDs on the intermediate sublayers adjacent to the first GND layer L2 and the second GND layer L7, respectively, it is conducive to the reliable transmission of high-speed signals.

[0101] Please combine Figures 1 to 13 The following describes the PCB board structure in the specific example of this application to facilitate a clearer understanding of this application, but it should not be used to limit this application.

[0102] In this example, the PCB board structure includes eight sub-layers, namely L1, L2, L3, L4, L5, L6, L7, and L8. Among them, the L1 layer is the top layer mentioned above; the L2 layer is the first GND layer, and the positions of the ground resistor R1, capacitor C, electrostatic protection device E and zero-ohm resistor R0 on the high-speed routing path corresponding to the L1 layer are hollowed out to reduce parasitic capacitance; the L3 layer is provided with SBU winding, CC winding, DN winding and DP winding, and the L3 layer is also provided with a reference GND of the related devices of the L1 layer for interlayer reference: the L4 layer is provided with SBU winding and CC winding; the L5 layer is the VBUS layer; the L6 layer is provided with a complementary structure of VBUS to be able to transmit a specified current, and the L6 layer is also provided with a reference GND of the related devices of the L8 layer for interlayer reference: the L7 layer is the second GND layer L7, and the positions of the ground resistor R1, capacitor C, electrostatic protection device E and zero-ohm resistor R0 on the high-speed routing path corresponding to the L8 layer are hollowed out to reduce parasitic capacitance; the L8 layer is the above-mentioned bottom layer L8.

[0103] Among them, the SBU2 pad in the first row of Typec pads 1 is connected to the SBU2 winding of the L3 layer through the blind hole K6, and the end of the SBU2 winding of the L3 layer away from the blind hole K6 is connected to the SBU2 routing of the L1 layer through the through hole K12. The SBU2 routing is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the through hole K11 through the SBU2 routing and connected to the corresponding SBU2 routing of the bottom layer L8 through the through hole K11. The SBU2 routing is connected to the OVP protection chip O, thereby realizing the line connection of the SBU2 pad in the first row of Typec pads 1.

[0104] The DN pads in the first row of Type-C pads 1 and the DN pads in the second row of Type-C pads 2 are connected via a DN trace to a shared trace for circuit connection. This DN trace is routed through via K13 to the DN routing on the L3 layer to facilitate circuit connection of the DN pads. Further connections for the DN routing are known to those skilled in the art and are not shown in the figure and will not be further described here.

[0105] The DP pads in the first row of Typec pads 1 are connected to the DP windings on the L3 layer through the through-hole K7, and the DP windings are connected to the DP traces on the L1 layer through the through-hole K14, and can then share some traces with the DP pads in the second row of Typec pads 2. The DP pads in the second row of Typec pads 2 are connected to the DP traces, which are connected to another DP winding on the L3 layer through the through-hole K15 and are connected through the DP windings. The further connection of the DP windings is known to those skilled in the art, is not shown in the figure, and will not be further described here.

[0106] The CC2 pad in the first row of Typec pads 1 is connected to the CC2 winding of the L4 layer through the through-hole K9, and the CC2 winding is connected to the CC2 trace of the L1 layer through the through-hole K16. The CC2 trace is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the corresponding through-hole K11 through the CC2 trace and connected to the corresponding CC2 trace of the bottom layer L8 through the through-hole K11. The CC2 trace is connected to the OVP protection chip O, thereby realizing the line connection of the CC2 pad in the first row of Typec pads 1.

[0107] The CC1 pad in the second row of Typec pads 2 is connected to the CC1 winding of the L3 layer through the through-hole K18, and the CC1 winding is connected to the CC1 trace of the L1 layer through the through-hole K19. The CC1 trace is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the corresponding through-hole K11 through the CC1 trace and is connected to the corresponding CC1 trace of the bottom layer L8 through the through-hole K11. The CC1 trace is connected to the OVP protection chip O, thereby realizing the line connection of the CC1 pad in the second row of Typec pads 2.

[0108] The SBU1 pad in the second row of Typec pads 2 is connected to the corresponding SBU1 winding of the L4 layer through the through-hole K21, and the SBU1 winding is connected to the SBU1 routing of the L1 layer through the through-hole K22. The SBU1 routing is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the corresponding through-hole K11 through the SBU1 routing and connected to the corresponding SBU1 routing of the bottom layer L8 through the through-hole K11. The SBU1 routing is connected to the OVP protection chip O, thereby realizing the line connection of the SBU1 pad in the second row of Typec pads 2.

[0109] The SBU2 pad in the third row of Typec pads 3 is connected to the SBU2 winding of the L6 layer through a blind via K10, and the SBU2 winding is connected to the SBU2 winding of the L4 layer through a buried via K24. The SBU2 winding of the L4 layer is connected to the SBU2 routing of the L8 layer through a through-hole K25. The SBU2 routing is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the OVP protection chip O through the SBU2 routing, thereby realizing the line connection of the SBU2 pad in the third row of Typec pads 3.

[0110] The DN pads in the third row of Type-C pads 3 are connected to the DN routing on the L6 layer via blind via K8. This DN routing is connected to the DN trace on the L8 layer via through-hole K26. The DN pads in the fourth row of Type-C pads 4 are also routed through this DN routing, allowing the two DN pads to share a routing. This DN routing is connected to the L3 layer via through-hole K27. On the L3 layer, through-hole K27 can be connected to through-hole K13 via a flying wire (not shown), and can then share the DN routing with the DN pads on the top layer L1.

[0111] The DP pads in the third row of Type-C pads 3 and the DP pads in the fourth row of Type-C pads 4 are connected via a DP trace to share a common trace. This DP trace can be connected to the L3 layer through via K28. On the L3 layer, via K28 can be connected to via K15 via a flying wire (not shown), and can then share the DP trace with the DP pads on the top layer L1.

[0112] The CC2 pad in the third row of Typec pads 3 is connected to the CC2 winding of the L3 layer through the through-hole K5, and the CC2 winding is connected to the CC2 trace of the L8 layer through the through-hole K29. The CC2 trace is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the OVP protection chip O through the CC2 trace, thereby realizing the line connection of the CC2 pad in the third row of Typec pads 3.

[0113] The CC1 pad in the fourth row of Typec pads 4 is connected to the CC1 winding of the L4 layer through the through-hole K30, and the CC1 winding is connected to the CC1 trace of the L8 layer through the through-hole K31. The CC1 trace is connected to the zero-ohm resistor R0, and the zero-ohm resistor R0 is connected to the OVP protection chip O through the CC1 trace, thereby realizing the line connection of the CC1 pad in the fourth row of Typec pads 4.

[0114] The SBU1 pad in the fourth row of Typec pads 4 is connected to another SBU1 winding on the L4 layer through a through-hole K32. The SBU1 winding is connected to the SBU1 routing on the L8 layer through a through-hole K33. The SBU1 routing is connected to the zero-ohm resistor R0. The zero-ohm resistor R0 is connected to the OVP protection chip O through the SBU1 routing, thereby realizing the line connection of the SBU1 pad in the fourth row of Typec pads 4.

[0115] It should be noted that the PCB board structure of the present application is not limited to the above-mentioned eight-layer structure and wiring method. As long as wiring can be performed to achieve line connection between the pads of the top layer L1 and the pads of the bottom layer L8, the number of sub-layers can be increased or decreased as needed, the order of the sub-layers is not fixed, and the wiring method can be freely changed.

[0116] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.

Claims

1. A PCB board structure for mounting a Type C connector, characterized in that: The PCB board structure is a stacked structure, including multiple sublayers, and the multiple sublayers include a top layer and a bottom layer. The top layer is provided with a first group of Typec pads, and the bottom layer is provided with a second group of Typec pads. The first group of Typec pads includes a first row of Typec pads located on the outside and a second row of Typec pads located on the inside. The second group of Typec pads includes a third row of Typec pads located on the outside and a fourth row of Typec pads located on the inside. The first row of Typec pads and the third row of Typec pads correspond to each other up and down, and the Typec pads of the first row of Typec pads and the Typec pads of the third row of Typec pads are alternately arranged along the arrangement direction. The second row of Typec pads and the fourth row of Typec pads are alternately arranged. The Typec pads in the first and second rows correspond to each other up and down, and the Typec pads in the second row and the Typec pads in the fourth row are alternately arranged along the arrangement direction; the arrangement directions of the first row of Typec pads and the third row of Typec pads are opposite, and the arrangement directions of the second row of Typec pads and the fourth row of Typec pads are opposite; DIP holes are respectively provided on both sides of the first group of Typec pads and the second group of Typec pads, and each DIP hole can be used for the pins of the same Typec connector to be inserted from the upper side and from the lower side. When the Typec connector is placed from the upper side, it is welded to the first group of Typec pads, and when it is placed from the lower side, it is welded to the second group of Typec pads.

2. The PCB board structure according to claim 1, characterized in that: The RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad in the first row of Type-c pads are respectively connected to two pairs of first high-speed traces on the top layer, and the two pairs of first high-speed traces are respectively routed from the relatively close DIP holes and the adjacent GND pads in the second row of Type-c pads to the inner side of the second row of Type-c pads; Each GND pad in the first row of Type-C pads and the second row of Type-C pads is independently grounded; The RX1+ pad, RX1- pad, TX2+ pad, and TX2- pad in the third row of Type-c pads are respectively connected to two pairs of third high-speed traces of the bottom layer, and the two pairs of third high-speed traces are respectively routed from the relatively close DIP holes and the adjacent GND pads in the fourth row of Type-c pads to the inner side of the fourth row of Type-c pads; Each GND pad in the third row of Type-C pads and the fourth row of Type-C pads is independently grounded.

3. The PCB board structure according to claim 2, characterized in that: The plurality of sub-layers include a first GND layer adjacent to the top layer and a second GND layer adjacent to the bottom layer; Grounding plates are provided on both sides of the first group of Type-C pads on the top layer and on both sides of the second group of Type-C pads on the bottom layer, and the DIP holes on both sides of the top layer and the bottom layer are connected to the grounding plates of the top layer and the bottom layer and the first GND layer and the second GND layer; The GND pads in the first row of Type-C pads and the GND pads in the third row of Type-C pads are respectively connected to the adjacent ground plates; The GND pads in the second row of Typec pads and the adjacent GND pads in the fourth row of Typec pads are respectively connected to the top and bottom of the same ground via through traces, and the ground via is connected to the first GND layer and the second GND layer.

4. The PCB board structure according to claim 2, characterized in that: The plurality of sub-layers include a first GND layer adjacent to the top layer and a second GND layer adjacent to the bottom layer; The RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad in the second row of TypeC pads are respectively connected to two pairs of second high-speed traces on the top layer; The RX2+ pad, RX2- pad, TX1+ pad, and TX1- pad in the fourth row of TypeC pads are respectively connected to two pairs of fourth high-speed traces of the bottom layer; The top layer is provided with resistors, capacitors, and electrostatic protection devices on the paths of the two pairs of the first high-speed routing lines and the two pairs of the second high-speed routing lines, respectively. The top layer is also provided with a first chip, and the two pairs of the first high-speed routing lines and the two pairs of the second high-speed routing lines are respectively connected to the first chip; The bottom layer is provided with resistors, capacitors, and electrostatic protection devices on the paths of the two pairs of the third high-speed routing lines and the two pairs of the fourth high-speed routing lines, respectively. The bottom layer is also provided with a second chip, and the two pairs of the third high-speed routing lines and the two pairs of the fourth high-speed routing lines are respectively connected to the second chip; The high-speed lines are completely routed on the top layer or the bottom layer, or the high-speed lines are simultaneously routed on the top layer and the bottom layer and connected through high-speed line vias.

5. The PCB board structure according to claim 1, characterized in that: The plurality of sub-layers include a VBUS layer; The VBUS pads in the first row of Type-C pads are respectively connected to adjacent VBUS pads in the second row of Type-C pads through first VBUS traces, and the VBUS pads in the second row of Type-C pads are connected to a first VBUS connection sheet arranged on the top layer; The VBUS pads in the third row of Type-C pads are respectively connected to the adjacent VBUS pads in the fourth row of Type-C pads through second VBUS traces, and the VBUS pads in the fourth row of Type-C pads are connected to the second VBUS connection sheet arranged on the bottom layer; A first VBUS through-hole is provided at a position corresponding to the adjacent first VBUS line and the second VBUS line, and the adjacent first VBUS line and the second VBUS line are connected to the VBUS layer through the first VBUS through-hole; A second VBUS through-hole is provided at a position corresponding to the adjacent first VBUS connecting piece and the second VBUS connecting piece, and the adjacent first VBUS connecting piece and the second VBUS connecting piece are connected to the VBUS layer through the second VBUS through-hole; The first VBUS connecting piece and the second VBUS connecting piece are respectively connected to VBUS capacitors, and the VBUS capacitors are grounded.

6. The PCB board structure according to claim 1, characterized in that: At least two middle sub-layers of the plurality of sub-layers located between the top layer and the bottom layer are provided with windings; The DN pads in the first row of Type-C pads are connected to the DN pads in the second row of Type-C pads through a DN trace provided on the top layer; The DP pads in the third row of Type-C pads are connected to the DP pads in the fourth row of Type-C pads through DP traces provided on the bottom layer; One of the SBU2 pad in the first row of Type-C pads and the CC2 pad in the third row of Type-C pads is connected to a first through-hole in the spacing area between the first row of Type-C pads and the second row of Type-C pads and between the third row of Type-C pads and the fourth row of Type-C pads through a first trace, and is connected to a corresponding winding of the corresponding middle sub-layer through the first through-hole, and the other is provided with a first blind hole at its location and is connected to a corresponding winding of the corresponding middle sub-layer through the first blind hole; One of the DP pad in the first row of Type-C pads and the DN pad in the third row of Type-C pads is connected to a second through-hole located in the spacing area through a second trace and is connected to a corresponding winding of the corresponding middle sub-layer through the second through-hole, and the other is provided with a second blind hole at its location and is connected to a corresponding winding of the corresponding middle sub-layer through the second blind hole; One of the CC2 pad in the first row of Typec pads and the SBU2 pad in the third row of Typec pads is connected to the third through hole located in the spacing area through a third trace and is connected to the corresponding winding of the corresponding middle sublayer through the third through hole, and the other is provided with a third blind hole at its location and is connected to the corresponding winding of the corresponding middle sublayer through the third blind hole.

7. The PCB structure according to claim 1, wherein: One of the top layer and the bottom layer is provided with a first OVP protection chip; The first OVP protection chip is respectively connected to the first group of zero-ohm resistors through different traces located on the same layer as the first group of Type-C pads, and the traces corresponding to the SBU pad and the CC pad of one of the first group of Type-C pads and the second group of Type-C pads are connected to the first OVP protection chip through the first group of zero-ohm resistors; Through holes are respectively provided at the locations of the different routings located between the first OVP protection chip and the first group of zero-ohm resistors, and a second group of zero-ohm resistors is provided on the other of the top layer and the bottom layer. Routes are connected between the second group of zero-ohm resistors and the corresponding through holes, and the routings corresponding to the SBU pads and CC pads of the other of the first group of Typec pads and the second group of Typec pads are connected to the corresponding second group of zero-ohm resistors.

8. The PCB structure according to claim 1, wherein: The multiple sublayers include a first GND layer adjacent to the top layer, a second GND layer adjacent to the bottom layer, and a plurality of intermediate sublayers located between the first GND layer and the second GND layer, the plurality of intermediate sublayers including a VBUS layer, and at least part of the plurality of intermediate sublayers are provided with SBU1 windings, SBU2 windings, CC1 windings, CC2 windings, DP windings, and DN windings for performing line connections between corresponding pads in the first group of Type-c pads and the second group of Type-c pads; The first GND layer is hollowed out at positions corresponding to at least part of the devices on the high-speed line on the top layer, and a reference GND is set on an intermediate sublayer adjacent to the first GND layer among the multiple intermediate sublayers; The second GND layer is hollowed out at positions corresponding to at least some devices on the high-speed line on the bottom layer, and a reference GND is set on an intermediate sublayer adjacent to the second GND layer among the multiple intermediate sublayers.

9. A combination of a PCB board structure and a Type C connector, characterized in that: It comprises a PCB board structure and a Type C connector as described in any one of claims 1 to 8, and the Type C connector is selectively placed on the upper side or the lower side of the PCB board structure.

10. An electronic device, characterized in that: It comprises a PCB board structure as described in claim 9 and a Type C connector combination.

Images