Circuit layout optimization method, device and related products

Abstract

The present application discloses a circuit layout optimization method, device and related products, which include a parsing step to determine the devices, wiring, graphics and the connection relationship between each other on the original circuit layout; an abstraction step to abstract the original circuit layout into device parameter units, wiring parameter units, graphic parameter units and the connection relationship between parameter units; and a parameter adjustment step to adjust the layout features of at least one of the device parameter units, the wiring parameter units and the graphic parameter units to obtain an optimized circuit layout and reduce the time-consuming cost of circuit layout design.

Description

Technical Field

[0001] The present application belongs to the field of circuit design technology, and in particular, relates to a circuit layout optimization method, device and related products. Background Art

[0002] In the design of circuit layout, it is necessary to perform multiple iterations to adjust the devices, connections, graphics, etc. in the circuit layout to achieve all design goals. Since each iteration takes several hours to several days, the time-consuming cost of circuit layout design is relatively high. Summary of the invention

[0003] The present application provides a circuit layout optimization method, device and related products to overcome or alleviate the defects of the prior art.

[0004] A method for optimizing a circuit layout, comprising:

[0005] Parsing step to determine the devices, wiring, graphics and the connection relationship between them on the original circuit layout;

[0006] An abstraction step is to abstract the original circuit layout into device parameter units, wiring parameter units, graphic parameter units, and connection relationships between parameter units;

[0007] The parameter adjustment step is used to adjust the layout characteristics of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit to obtain an optimized circuit layout.

[0008] A circuit layout optimization device, comprising:

[0009] A parsing unit, which is used to: parse the original circuit layout to determine the layout elements thereon, wherein the layout elements include devices, wirings, graphics and connection relationships between each other on the original circuit layout;

[0010] An abstraction unit is used to: abstract the layout element into a parameterized unit set, the parameterized unit set includes a device parameter unit, a wiring parameter unit, a graphic parameter unit, and a connection relationship between parameter units, the device parameter unit has a device input parameter, the wiring parameter unit has a wiring input parameter, and the graphic parameter unit has a graphic input parameter;

[0011] A parameter adjustment and optimization unit, which is used to adjust at least one of the device input parameter, wiring input parameter, and graphic input parameter based on the connection relationship of the parameter unit components and the mapping relationship between the result index and at least one of the device input parameter, wiring input parameter, and graphic input parameter, so as to adjust the layout feature of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit accordingly, so as to obtain an optimized circuit layout;

[0012] An index calculation unit, which is used to calculate the result index of the optimized circuit layout and compare it with the design index to determine whether the optimized circuit layout needs to be re-optimized;

[0013] If yes, jump to the parameter adjustment step and re-execute the index calculation step until the re-optimization of the optimized circuit layout is completed;

[0014] If not, the re-optimization of the optimized circuit layout is terminated.

[0015] A computer storage medium having a computer executable program stored thereon, wherein the computer executable program is run to implement any method described in any of the application embodiments.

[0016] An electronic device, characterized in that the electronic device includes a memory and a processor, the memory is used to store a computer executable program, and the processor is used to run the computer executable program to implement any method described in the application embodiment.

[0017] A computer program product, characterized in that a computer executable program is stored thereon, and the computer executable program is run to implement any method described in the embodiments of the present application.

[0018] In the technical solution provided in the present application, a parsing step is used to determine the devices, wiring, graphics and the connection relationships between them on the original circuit layout; an abstraction step is used to abstract the original circuit layout into device parameter units, wiring parameter units, graphic parameter units, and the connection relationships between parameter units; a parameter adjustment step is used to adjust the layout features of at least one of the device parameter units, the wiring parameter units, and the graphic parameter units to obtain an optimized circuit layout and reduce the time-consuming cost of circuit layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic flow chart of a circuit layout optimization method according to an embodiment of the present application.

[0020] Figure 2 A schematic diagram of the structure of a circuit layout optimization device according to an embodiment of the present application.

[0021] Figure 3A The present invention is a schematic diagram of applying the above technical solution of the embodiment of the present application to the original circuit of a single-stage GOA circuit layout.

[0022] Figure 3B This is a schematic diagram of the original circuit layout of a single-stage GOA circuit layout.

[0023] Figure 3C Schematic diagram for parameterizing a single-stage GOA circuit board.

[0024] Figure 3D FIG. 1 is a wiring diagram of a single-stage GOA circuit layout.

[0025] Figure 3E This is a schematic diagram of the change in device position within a single-stage GOA circuit layout after parameter adjustment. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0027] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0028] Figure 1 FIG. 1 is a flow chart of a method for optimizing a circuit layout according to an embodiment of the present application. Figure 1 As shown, it includes:

[0029] S101, a parsing step, which includes: parsing the original circuit layout to determine the layout elements thereon, wherein the layout elements include devices, wirings, graphics and connection relationships between each other on the original circuit layout;

[0030] For example, a description file of the original circuit layout is used to determine the layout elements thereon.

[0031] S102, an abstraction step, comprising: abstracting the layout element into a parameterized unit set, the parameterized unit set comprising a device parameter unit, a wiring parameter unit, a graphic parameter unit, and a connection relationship between parameter units, the device parameter unit having a device input parameter, the wiring parameter unit having a wiring input parameter, and the graphic parameter unit having a graphic input parameter;

[0032] Exemplarily, the layout elements may be abstracted into parameterized units by performing parameterized programming on the abstraction.

[0033] Alternatively, for the connection relationship between parameters, a connection relationship description file may be parsed to obtain the connection relationship between parameters. The connection relationship description file may be, for example, a schematic or a netlist.

[0034] S103, a parameter adjustment step, comprising adjusting at least one of the device input parameter, the wiring input parameter, and the graphic input parameter based on the connection relationship of the parameter unit components and the mapping relationship between the result index and at least one of the device input parameter, the wiring input parameter, and the graphic input parameter, so as to adjust the layout feature of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit accordingly, so as to obtain an optimized circuit layout;

[0035] Correspondingly adjusting at least one of the device input parameters, wiring input parameters, and graphic input parameters, changing the parameter unit position, shape, and relative position relationship, etc., to correspondingly adjust the layout features of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit.

[0036] For example, the unit connection relationship between the two devices is kept unchanged, and the device input parameters are adjusted so that the relative position relationship of the two devices changes, but the connection line still connects the corresponding ports of the two devices. The wiring is re-routed through the wiring algorithm, so that the shape of the connection line changes.

[0037] Exemplarily, the mapping relationship between the result indicator and at least one of the device input parameter, wiring input parameter, and graphic input parameter can be obtained by collecting historical data and performing analysis.

[0038] The device input parameters include, but are not limited to: device electrical parameters, device offset or offset angle relative to a reference, device position parameters, device shape parameters, and parameters of graphics contained in the device.

[0039] The wiring input parameters include but are not limited to minimum line width, maximum line width, minimum spacing, maximum spacing, spacing between different metal layers, and nested boundary distance between different metal layer graphics.

[0040] The graphic input parameters include but are not limited to position parameters, shape parameters, angle parameters, chamfer parameters, offset and angle relative to a reference object, etc.

[0041] S104, an index calculation step, which includes calculating the result index of the optimized circuit layout and comparing it with the design index to determine whether the optimized circuit layout needs to be re-optimized;

[0042] If yes, jump to the parameter adjustment step and re-execute the index calculation step until the re-optimization of the optimized circuit layout is completed;

[0043] If not, the re-optimization of the optimized circuit layout is terminated.

[0044] In step S104, the result index of the optimized circuit layout may be calculated by an index calculator.

[0045] Optionally, the method further comprises: an initial layout optimization step, which comprises: adjusting initial layout features of the device parameter unit, the wiring parameter unit, and the graphic parameter unit on the original circuit layout;

[0046] By adjusting the initialization layout features, when executing the solution of the embodiment of the present application, the initialization layout features are as close as possible to the optimized layout features, thereby shortening the processing time of layout optimization, quickly realizing layout optimization, and ensuring that the result indicators meet the requirements of the design goals.

[0047] The parameter adjustment step includes, based on the connection relationship of the parameter unit components, according to the mapping relationship between the result index and at least one of the device input parameters, wiring input parameters, and graphic input parameters, taking the initial layout features as a reference, correspondingly adjusting at least one of the device input parameters, wiring input parameters, and graphic input parameters, so as to correspondingly adjust the layout features of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit, so as to obtain an optimized circuit layout.

[0048] Exemplarily, a parameterized router and a parameterized layout device can adjust the layout features of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit according to at least one of the device input parameters, the wiring input parameters, and the graphic input parameters to achieve device generation, layout, and wiring generation.

[0049] For example, for devices, the relative position relationship between devices (also known as floorplan) can be adjusted through the above-mentioned input parameter adjustment, so that after the layout is optimized, the result indicators of the optimized circuit layout can meet the requirements of the design indicators (or the feasible domain of the result indicators) as a whole.

[0050] Optionally, in the parameter adjustment step, based on the artificial intelligence model, at least one of the device input parameters, wiring input parameters, and graphic input parameters is adjusted accordingly according to the mapping relationship between the result indicator and at least one of the device input parameters, wiring input parameters, and graphic input parameters.

[0051] Since all parameter units have a large number of input parameters (i.e., input parameters), more than 100 are common, so the parameter search space is very large. Assuming that there are n input parameters for all parameter units, each parameter has a value range on a continuous domain, and assuming that m samples are taken within the value range when determining each parameter, then the search space complexity of parameterized layout generation is m.n Assuming that a panel module circuit has only 50 input parameters and each parameter is sampled 1000 times, then the search space also reaches 1000. 50 Since each search consumes a lot of time and computing resources including calculation indicators, it is not feasible to manually search one by one in such a huge space to find feasible solutions. Therefore, an artificial intelligence model is established to fit the mapping relationship between input parameters and result indicators, thereby improving search efficiency.

[0052] Exemplarily, the mapping relationship between the result index and at least one of the device input parameter, wiring input parameter, and graphic input parameter can be obtained by collecting historical data and using these historical data as training sample data to train the artificial intelligence model, so that the artificial intelligence model has model parameters that meet the requirements, so that when executing the scheme of the present application, at least one of the device input parameter, wiring input parameter, and graphic input parameter is input, and the result index can be quickly determined. Or, based on the way that the result index is closest to the design index, based on the determined result index, according to the mapping relationship, the corresponding at least one of the device input parameter, wiring input parameter, and graphic input parameter is determined.

[0053] Artificial intelligence models are generally implemented through a neural network, with input parameters as the input of the neural network and result indicators as the output, and a large number of weights in the network are trained. After training, the weights tend to be stable. At this time, the neural network reflects the functional relationship between the input parameters and result indicators reflected by countless samples.

[0054] The historical data collected here can be collected offline or online. When collecting online, that is, when executing the solution of the embodiment of the present application, the mapping relationship between the result index and at least one of the device input parameter, wiring input parameter, and graphic input parameter is added to the training sample data as new historical data.

[0055] Exemplarily, a series of input parameters can be automatically generated based on the parameter changer to form an automatically changing parameter value combination, which is added to the above training sample. Furthermore, a value is randomly selected for each parameter each time to form an input parameter value list, corresponding to a result indicator list, which together form a training sample.

[0056] If the artificial intelligence model is not used, in order to adjust the layout design, each time the above parameters are manually modified, DRC, RC extraction, simulation, waveform drawing, and indicator extraction must be run, which takes an average of 15 minutes.

[0057] Since a large number of samples are required, an excellent parameter transformer is needed. However, simple random sampling has the problem of low sample quality. Therefore, sampling methods are generally carefully designed to improve sample quality.

[0058] Target indicators include compliance with design rules. Design rules include: process geometry rules, such as minimum line width and line spacing. Target indicators also include layout geometry and electrical performance indicators, such as the peak voltage of the output signal and the charging rate of key pixels in the driven pixel array.

[0059] The result indicators of the designed layout can be automatically checked or calculated by EDA tools such as geometric rule checking tools, parasitic resistance and capacitance calculation tools, simulation tools, and waveform display tools. If all the layout result indicators reach the target indicator range at the same time, it means that the layout design has met the design requirements.

[0060] Specifically, for example, the optimized layout is checked for rationality (including DRC check, i.e., the geometric rule check required during production) and parasitic resistance and capacitance are extracted, and some resistance and capacitance are obtained as indicators. Then simulation and circuit waveform drawing are performed to obtain result indicators. Therefore, the result indicators include but are not limited to geometry, correctness, electrical, area size, power consumption, etc.

[0061] Optionally, in the parameter adjustment step, the initial layout features are used as a reference to further determine the direction of parameter adjustment according to the initial layout features, so as to correspondingly adjust at least one of the device input parameters, wiring input parameters, and graphic input parameters.

[0062] For example, if a capacitor is stretched laterally to make it larger, the direction of parameter adjustment is: in the direction of larger capacitance value, larger lateral size of the capacitor, etc. Otherwise, the search for small capacitance value is reduced.

[0063] Optionally, the method further comprises: a layout feature saving step, which comprises storing the optimized layout features of the optimized circuit layout into a layout feature table;

[0064] In the index calculation step, the optimized layout feature is obtained from the layout feature table, so as to calculate the result index of the optimized circuit layout according to the optimized layout feature.

[0065] Optionally, the original circuit layout is a GOA (Gate On Array) driving module.

[0066] The above technical solution provided in the embodiment of the present application can be applied to the GOA driver module, including but not limited to the central control screen of the vehicle, the watch screen, the smart phone screen, the LCD or OLED TV screen, etc. The GOA driver module can be specifically located within the non-luminous area border on the left or right side of the screen.

[0067] Figure 2 Schematic diagram of the structure of a circuit layout optimization device according to an embodiment of the present application. Figure 2As shown, it includes:

[0068] The parsing unit 201 is used to: parse the original circuit layout to determine the layout elements thereon, wherein the layout elements include devices, wirings, graphics and connection relationships between each other on the original circuit layout;

[0069] An abstraction unit 202 is used to abstract the layout element into a parameterized unit set, wherein the parameterized unit set includes a device parameter unit, a wiring parameter unit, a graphic parameter unit, and a connection relationship between parameter units. The device parameter unit has a device input parameter, the wiring parameter unit has a wiring input parameter, and the graphic parameter unit has a graphic input parameter;

[0070] A parameter adjustment and optimization unit 203, which is used to adjust at least one of the device input parameter, wiring input parameter, and graphic input parameter based on the connection relationship of the parameter unit components and the mapping relationship between the result index and at least one of the device input parameter, wiring input parameter, and graphic input parameter, so as to adjust the layout feature of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit accordingly, so as to obtain an optimized circuit layout;

[0071] An index calculation unit 204 is used to calculate the result index of the optimized circuit layout and compare it with the design index to determine whether the optimized circuit layout needs to be re-optimized;

[0072] If yes, jump to the parameter adjustment step and re-execute the index calculation step until the re-optimization of the optimized circuit layout is completed;

[0073] If not, the re-optimization of the optimized circuit layout is terminated.

[0074] The embodiments of the present application also provide a computer storage medium, on which a computer executable program is stored, and the computer executable program is executed to implement any method described in the embodiments of the present application.

[0075] An embodiment of the present application further provides an electronic device, which includes a memory and a processor, wherein the memory is used to store a computer executable program, and the processor is used to run the computer executable program to implement any method described in the embodiment of the present application.

[0076] The embodiments of the present application also provide a computer program product having a computer executable program stored thereon, wherein the computer executable program is executed to implement any of the methods described in the embodiments of the present application.

[0077] Figure 3AA schematic diagram of an original circuit for applying the above technical solution of an embodiment of the present application to a single-stage GOA circuit layout includes devices M0, M1, M2, and M3. Figure 3B This is a schematic diagram of the original circuit layout of a single-stage GOA circuit layout, in which all levels are displayed without module names. Figure 3C Schematic diagram of parameterizing a single-level GOA circuit board, unit view and routing unit content after all layout elements are abstracted into parameterized units. Figure 3D FIG. 1 is a wiring diagram of a single-stage GOA circuit layout. Figure 3E This is a schematic diagram of the change in device position in a single-stage GOA circuit layout after parameter adjustment, before and after changing the relative position relationship of two or more devices (see M0 and M3 in the figure, etc.).

[0078] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for optimizing a circuit layout, characterized in that: include: Parsing step to determine the devices, wiring, graphics and the connection relationship between them on the original circuit layout; An abstraction step is to abstract the original circuit layout into device parameter units, wiring parameter units, graphic parameter units, and connection relationships between parameter units; A parameter adjustment step, for adjusting the layout characteristics of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit to obtain an optimized circuit layout; Wherein, in the parameter adjustment step, based on the artificial intelligence model, at least one of the device input parameter, wiring input parameter, and graphic input parameter is correspondingly adjusted according to the mapping relationship between the result index and at least one of the device input parameter, wiring input parameter, and graphic input parameter; Wherein, the method further comprises: a layout feature saving step, which comprises storing the optimized layout features of the optimized circuit layout into a layout feature table; In the index calculation step, the optimized layout feature is obtained from the layout feature table, so as to calculate the result index of the optimized circuit layout according to the optimized layout feature; Among them, the artificial intelligence model is implemented through a neural network, with input parameters as the input of the neural network and result indicators as the output. A large number of weights in the network are trained. After the training is completed, the weights tend to be stable. At this time, the neural network reflects the functional relationship between the input parameters and result indicators reflected by the sample. During execution, at least one of the device input parameters, wiring input parameters, and graphic input parameters is input to quickly determine the result indicators.

2. The method according to claim 1, characterized in that The method further comprises: an initial layout optimization step to determine initial layout features; The parameter adjustment step is specifically used to adjust the layout characteristics of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit accordingly with reference to the initial layout characteristics, so as to obtain an optimized circuit layout.

3. The method according to claim 2, characterized in that In the parameter adjustment step, the initial layout feature is used as a reference to further determine the direction of parameter adjustment according to the initial layout feature, so as to correspondingly adjust at least one of the device input parameter, wiring input parameter, and graphic input parameter.

4. The method according to any one of claims 1 to 3, characterized in that: The original circuit layout is a GOA driver module.

5. A circuit layout optimization device, characterized in that: include: A parsing unit, which is used to: parse the original circuit layout to determine the layout elements thereon, wherein the layout elements include devices, wirings, graphics and connection relationships between each other on the original circuit layout; An abstract unit, which is used to: abstract the layout element into a parameterized unit set, the parameterized unit set includes a device parameter unit, a wiring parameter unit, a graphic parameter unit, and a connection relationship between parameter units, the device parameter unit has a device input parameter, the wiring parameter unit has a wiring input parameter, and the graphic parameter unit has a graphic input parameter; A parameter adjustment optimization unit, which is used to adjust at least one of the device input parameters, wiring input parameters, and graphic input parameters based on the component connection relationship of the parameter unit and according to the mapping relationship between the result index and at least one of the device input parameters, wiring input parameters, and graphic input parameters, so as to adjust the layout characteristics of at least one of the device parameter unit, the wiring parameter unit, and the graphic parameter unit accordingly, so as to obtain an optimized circuit layout; An index calculation unit, which is used to calculate the result index of the optimized circuit layout and compare it with the design index to determine whether the optimized circuit layout needs to be re-optimized; If yes, jump to the parameter adjustment step and re-execute the index calculation step until the re-optimization of the optimized circuit layout is completed; If not, then the re-optimization of the optimized circuit layout is terminated; Wherein, in the parameter adjustment step, based on the artificial intelligence model, at least one of the device input parameter, wiring input parameter, and graphic input parameter is correspondingly adjusted according to the mapping relationship between the result indicator and at least one of the device input parameter, wiring input parameter, and graphic input parameter; Among them, it also includes: a layout feature saving step, which includes storing the optimized layout features of the optimized circuit layout into a layout feature table; In the index calculation step, the optimized layout feature is obtained from the layout feature table, so as to calculate the result index of the optimized circuit layout according to the optimized layout feature; Among them, the artificial intelligence model is implemented through a neural network, with input parameters as the input of the neural network and result indicators as the output. A large number of weights in the network are trained. After the training is completed, the weights tend to be stable. At this time, the neural network reflects the functional relationship between the input parameters and result indicators reflected by the sample. During execution, at least one of the device input parameters, wiring input parameters, and graphic input parameters is input to quickly determine the result indicators.

6. A computer storage medium, characterized in that: The computer storage medium stores a computer executable program, and the computer executable program is run to implement the method according to any one of claims 1 to 4.

7. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory is used to store a computer executable program, and the processor is used to run the computer executable program to implement any one of the methods of claims 1-4.

8. A computer program product, characterized in that A computer executable program is stored thereon, and the computer executable program is run to implement the method according to any one of claims 1 to 4.

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