Method for automatically checking connection of ip module traces after synthesis of ip module
By classifying the layout hierarchically and setting configuration files, the system automatically checks the IP module connection traces, solving the problems of low inspection efficiency and error susceptibility in existing technologies. This achieves efficient and accurate IP module connection trace inspection and is applicable to multi-process platforms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-28
- Publication Date
- 2026-03-31
AI Technical Summary
Existing technologies struggle to efficiently and accurately inspect the interconnect traces of synthesized IP modules, especially in deep submicron integrated circuit chip processes, where they suffer from low inspection efficiency and are prone to errors.
The effective layers of the layout are divided into boundary layer, front-end layer and back-end layer. Corresponding configuration files are established. By calculating the top-level metal interconnects and performing contact and non-contact calculations, the contact between the PIN pattern and the metal interconnects is checked, thus achieving automated inspection.
It enables efficient and accurate automatic inspection of IP module connection wiring on various process platforms, shortening the running time and improving the accuracy of inspection results.
Smart Images
Figure CN115809636B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor integrated circuit manufacturing process, and more particularly to a method for automatically checking the wiring of connected IP modules after synthesizing intellectual property (IP) modules. Background Technology
[0002] As deep submicron integrated circuit chip manufacturing processes become increasingly complex, the number of mask layers and GDS (Geometric Schematic Data) layers involved is also increasing. It's very common for IP cores to be synthesized from customer chip layout data. Typically, IP cores are provided by IP vendors or the design team at the foundry (FAB), and the IP synthesis is performed at the FAB. After synthesizing IP from customer GDS layout data, it's necessary to check for any issues with the traces connecting the IP cores.
[0003] like Figure 1A The diagram shown is the existing IP module layout; IP module 101 will be integrated into the customer's layout as a whole. Figure 1A The PIN output method is that the PIN is output inside the IP core, i.e., the boundary of IP module 101. Figure 1A The area indicated by the dashed circle 102 is the region where the PIN pattern is formed, located inside the boundary of IP module 101. For example... Figure 1B As shown, is Figure 1A Enlarged view of the PIN graphic area; Figure 1B The image shows the metal wiring 103 and the PIN pattern 104 of the IP module 101.
[0004] Because the PIN pattern 104 of IP module 101 is located inside the boundary of IP module 101, the customer needs to correctly route and connect the PIN pattern 104 of IP module 101 on the layout for the IP function to work properly. And for... Figure 1A The common scenario shown here, where the PIN is located inside the IP boundary, requires the customer to route a trace inside the IP to make the PIN connection.
[0005] Because there are other different layers and multiple layers of metal traces inside the IP, it is generally difficult to inspect such connections visually, which is inefficient and prone to errors.
[0006] The current common method is to use a program to check the IP PIN connection, but the applicable processes and levels of the current method are relatively limited and cannot be expanded. The running time and accuracy also need to be further improved. Summary of the Invention
[0007] The technical problem to be solved by the present invention is a method for automatically checking the wiring of connected IP modules after synthesizing IP modules. It can achieve efficient and accurate automatic checking of the IP module connection wiring in the layout, can be extended to various process platforms, has a shorter running time and more accurate results.
[0008] To solve the above-mentioned technical problems, the method for automatically checking the wiring of the connected IP module after synthesizing the IP module provided by the present invention includes the following steps:
[0009] Step 1: Divide the effective layers of the layout into three categories: boundary layers, frontend layers, and backend layers.
[0010] The boundary hierarchy refers to the graphic layers within the IP module that cover the entire IP module area.
[0011] The patterns of each layer included in the back-end layer are the metal interconnect patterns of each layer in the back-end process outside the boundary layer.
[0012] The graphics of each layer included in the front-end layer are graphics of each front-end process layer outside the boundary layer and the back-end layer.
[0013] Step 2: Establish corresponding configuration files according to different processes. The configuration files include the parameters of each layer of the boundary layer, the back-end layer, and the front-end layer.
[0014] Step 3: Provide a layout with IP module synthesis, detect the process used in the layout data, and select the corresponding configuration file according to the name of the process used.
[0015] Step 4: Calculate the top-level metal interconnects based on the configuration file.
[0016] Step 5: Calculate whether any graphics in the front-end layer enter the IP module area corresponding to the boundary layer.
[0017] Step 6: Calculate whether the PIN pattern of the IP module in the boundary layer will come into contact with the metal interconnects in the back-end layer.
[0018] Step 7: Inspect the metal interconnects in the IP module area that enters the boundary layer in the back-end layer.
[0019] A further improvement is that the aforementioned front-end processes in each layer are used to fabricate semiconductor devices on a semiconductor substrate.
[0020] A further improvement is that the back-end process is used to fabricate the metal interconnect patterns of each layer of the semiconductor device.
[0021] A further improvement is that, in step two, the parameters of each layer of the configuration file include the layer number.
[0022] A further improvement is that, in step four, the top layer metal includes various metals of different thicknesses, and the top layer metal interconnects are obtained by performing an OR operation on the interconnects of the various metals of different thicknesses.
[0023] A further improvement is that the calculation in step five is achieved by performing a bitwise AND operation on the graphics in the front-end layer and the IP module region corresponding to the boundary layer.
[0024] A further improvement is that, in step five, if the calculation results find that a graphic in the front-end layer has entered the IP module area corresponding to the boundary layer, then the graphic in the front-end layer that has entered the IP module area corresponding to the boundary layer will be reported as an error.
[0025] A further improvement is that the calculation in step six is implemented using both contact and non-contact operations.
[0026] A further improvement is that in step six, if the calculation structure shows that the PIN pattern is not in contact with the corresponding metal connection, it indicates that the PIN pattern is floating and an error is reported for the floating PIN pattern.
[0027] A further improvement is that the inspection results in step seven include:
[0028] The first outcome is that the metal interconnect does not contact the PIN pattern.
[0029] The second result is that the metal interconnect is tangent to the PIN pattern.
[0030] The third result is that the metal interconnects intersect with the PIN pattern and the metal interconnects are all inside the PIN pattern.
[0031] The fourth result is that the metal interconnect intersects with the PIN pattern, but a portion of the metal interconnect is located outside the PIN pattern.
[0032] A further improvement is that the first result is obtained through contactless calculation, and a routing error is reported when the result in step seven is the first result.
[0033] A further improvement is that the second result is obtained through a contact operation, wherein the metal wire contacts the edge of the PIN pattern.
[0034] A further improvement is that the third result is obtained by combining a contact operation with an inclusion operation.
[0035] A further improvement is that the fourth result is obtained by a contact operation plus a NOT ENCLOSURE operation, and an error is reported when the result in step seven is the fourth result.
[0036] A further improvement is that the map data described in step three is in GDS format.
[0037] This invention categorizes the effective layers of the layout and sets corresponding configuration files based on the process settings of the layout data. This allows for efficient and accurate automatic inspection of IP module connections across various process platforms. By selecting the configuration file corresponding to the process and performing corresponding calculations based on the boundary layers, front-end layers, and back-end layers formed by the layout classification, this invention can significantly shorten runtime and improve the accuracy of inspection results. Therefore, this invention enables efficient and accurate automatic inspection of IP module connection traces on the layout, can be extended to various process platforms, has a shorter runtime, and provides more accurate results. Attached Figure Description
[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0039] Figure 1A This is the layout of the existing IP modules;
[0040] Figure 1B yes Figure 1A Enlarged view of the PIN graphic area;
[0041] Figure 2 This is a flowchart of a method for automatically checking the wiring of the connected IP modules after synthesizing the IP modules according to an embodiment of the present invention;
[0042] Figure 3A This is an overall layout diagram of the method for automatically checking the wiring of the connected IP modules after synthesizing the IP modules according to an embodiment of the present invention;
[0043] Figure 3B This is an enlarged view of the PIN pattern area of the IP module in the method for automatically checking the wiring of the connected IP module after synthesizing the IP module according to an embodiment of the present invention;
[0044] Figure 4 This is the configuration file in the method for automatically checking the wiring of the connected IP modules after synthesizing the IP modules according to the embodiments of the present invention;
[0045] Figures 5A-5D This is a graphic representation of the layout area corresponding to various errors detected in the method for automatically checking the wiring of the connected IP modules after synthesizing the IP modules in this embodiment of the invention. Detailed Implementation
[0046] like Figure 2The diagram shown is a flowchart of a method for automatically checking the wiring of the IP module after synthesizing the IP module according to an embodiment of the present invention; as shown... Figure 3A The diagram shown is an overall layout of the method for automatically checking the wiring of the IP module after synthesizing the IP module according to an embodiment of the present invention; as shown Figure 3B The image shown is an enlarged view of the PIN pattern 204 area of the IP module in the method for automatically checking the wiring of the connected IP module after synthesizing the IP module according to an embodiment of the present invention; as shown Figure 4 The image shown is a configuration file used in the method for automatically checking the wiring connecting the IP module after synthesizing the IP module according to an embodiment of the present invention; as shown... Figures 5A to 5D The diagram shown is a graphic representation of area 201 of the layout when various errors are detected in the method for automatically checking the wiring of the connected IP module after synthesizing the IP module according to an embodiment of the present invention.
[0047] The method for automatically checking the wiring connecting the IP module after synthesizing the IP module according to the embodiments of the present invention includes the following steps:
[0048] Step 1, such as Figure 3A As shown, the effective layers of the layout 201 are divided into three categories: boundary layer, front layer, and back layer.
[0049] The boundary hierarchy refers to the graphic layers within the IP module that cover the entire IP module area.
[0050] The patterns of each layer included in the back-end layer are the metal interconnect patterns of each layer in the back-end process outside the boundary layer.
[0051] The graphics of each layer included in the front-end layer are graphics of each front-end process layer outside the boundary layer and the back-end layer.
[0052] In this embodiment of the invention, the front-end processes described in each layer are used to fabricate semiconductor devices on a semiconductor substrate.
[0053] The back-end process is used to fabricate the metal interconnect patterns of each layer of the semiconductor device. The metal interconnect patterns in the back-end process include metal wires for electrical connection and vias between the metal wires.
[0054] Step 2, as follows Figure 4 As shown, corresponding configuration files are established according to different processes. The configuration files include parameters of each layer of the boundary layer, the back-end layer, and the front-end layer.
[0055] Figure 4 The configuration file mentioned above is displayed in the image. Figure 4In the configuration file, dashed box 302 shows the parameters of the boundary layer, dashed box 303 shows the parameters of each layer of the subsequent layer, and dashed box 304 shows the parameters of each layer of the preceding layer. The parameters of the configuration file differ for different processes, allowing the method of this embodiment to be extended to various different processes.
[0056] The parameters of each layer of the configuration file include the layer number.
[0057] Step 3: Provide layout 201 with IP module synthesis, that is, in Figure 3A The IP module is synthesized in the IP module region 202, and the layout of the IP module can be referenced. Figure 1A As shown.
[0058] like Figure 3B The image shows an enlarged view of the PIN pattern 204 area of the IP module. The PIN pattern 204 is formed in the boundary area indicated by the dashed circle 301, but is located inside the IP module. The PIN pattern 204 is connected to the metal interconnect 206 of the IP module. The metal interconnect 206 is a metal interconnect.
[0059] The process used in the layout 201 data is detected, and the corresponding configuration file is selected according to the name of the process used.
[0060] In this embodiment of the invention, when the automatic inspection program is running, the configuration file corresponding to the input process will be called according to the input process. That is, according to the process name selected by the customer for synthesizing IP data, the corresponding process configuration file is retrieved from the process library, which includes the boundary layer (containing the entire IP area), backend layers (containing metal interconnects and vias between interconnects), and frontend layers (i.e., other layers that cannot extend into the IP except for the boundary layer and the backend layer).
[0061] Next, the layer numbers corresponding to the boundary, backend layers, and frontend layers are read from the configuration file.
[0062] The layout 201 data of the synthesized IP module adopts GDS format data.
[0063] Step 4: Calculate the top-level metal interconnect 206 according to the configuration file.
[0064] In this embodiment of the invention, the top layer metal includes a variety of metals of different thicknesses, and the top layer metal interconnection 206 is obtained by performing an OR operation on the interconnection 206 of the various metals of different thicknesses.
[0065] In this embodiment of the invention, based on the total number of metal layers used in this customer data analysis, the required metal layers are determined, such as 3 layers. These 3 metal layers are M1, M2, and M3. Since the top layer metal may use different metal thickness layers, for ease of processing, the different thickness layers are added together (OR operation) to obtain the top layer metal layer. For example, the top layer metal could be MT+MTT10K+MTT25K+MTT40K, where "+" represents the OR operation. That is, the metal connection 206 corresponding to MT, MTT10K, MTT25K, and MTT40K are all part of the top layer metal.
[0066] Step 5: Calculate whether any graphics in the front-end layer enter the IP module region 202 corresponding to the boundary layer.
[0067] In this embodiment of the invention, the calculation in step five is achieved by performing an AND operation on the graphics in the front-end layer and the IP module region 202 corresponding to the boundary layer.
[0068] If the calculation results show that a graphic in the front-end layer has entered the IP module region 202 corresponding to the boundary layer, then the graphic in the front-end layer that has entered the IP module region 202 corresponding to the boundary layer will be reported as an error.
[0069] That is, in step five, a bitwise AND operation is performed between the front-end layer of the customer data area and the boundary area of the IP cell. If a graphic is found after the calculation, an error is reported for that graphic. Figure 5A As shown, the left side of line AA is the IP region, i.e., within the IP module region 202, and the right side is outside the IP region. Figure 205 represents the polysilicon pattern of the front-end layer. It can be seen that figure 205 will move from the right side of line AA to the left side, i.e., it will enter the IP region. Whether figure 205 will enter the IP region can be determined by performing a bitwise AND operation between figure 205 and the IP region. If it is confirmed that figure 205 will enter the IP region, an error will be reported.
[0070] Step 6: Calculate whether the PIN pattern 204 of the IP module in the boundary layer will contact the metal interconnect 206 in the back-end layer.
[0071] In this embodiment of the invention, the calculation in step six is implemented using contact (TOUCH) and no-touch (NO TOUCH) operations. In step six, if the calculation structure shows that the PIN pattern 204 is not in contact with the corresponding metal connection 206, it indicates that the PIN pattern 204 is floating and an error is reported for the floating PIN pattern 204.
[0072] That is, in step six, the PIN pattern 204 in the IP area is checked. If it is in contact with the corresponding metal layer pattern outside the IP, it indicates that the PIN is connected; if not, it indicates that the PIN is floating and an error is reported for the PIN, which is achieved through TOUCH and NO TOUCH operations, such as... Figure 5B As shown, the PIN pattern 204 in the dashed coil 306 is not in contact with any metal wire 206, so the PIN pattern 204 is suspended.
[0073] Step 7: Inspect the metal interconnects 206 in the IP module region 202 that enters the boundary layer in the back-end layer.
[0074] In this embodiment of the invention, the inspection result of step seven includes:
[0075] The first result is that the metal trace 206 does not contact the PIN pattern 204. This first result is obtained through a contactless operation. In step seven, if the result is the first result, a routing error is reported. That is, if the metal trace 206 is found to be not in contact with the PIN pattern 204 through the NOTOUCH operation, a routing error is reported. Figure 5C As shown, the metal trace 206 in the dashed coil 309 does not contact the PIN pattern 204, so a routing error will occur.
[0076] The second result is that the metal trace 206 is tangent to the PIN pattern 204. This second result is obtained through contact calculation; the metal trace 206 contacts the edge of the PIN pattern 204, which is normal. That is, when the trace, i.e., the metal trace 206, just touches the edge of the PIN pattern 204, the metal trace 206 is tangent to the PIN pattern 204, and the connection is OK; if… Figure 5B As shown, the PIN pattern 204 in the dashed coil 308 is tangent to any metal connection 206, so the connection is OK there.
[0077] The third result is that the metal connection 206 intersects with the PIN pattern 204, and all metal connections 206 are inside the PIN pattern 204. This third result is obtained through contact and inclusion operations, and the connection in this case is correct. That is, if the metal connection 206 intersects with the PIN pattern 204, and all metal connections 206 are inside the PIN pattern 204 (i.e., an inclusion relationship), then it is OK. Figure 5B The connections at points 305 and 307 of the middle dotted coil are correct.
[0078] The fourth result is that the metal connection 206 intersects with the PIN pattern 204, but a portion of the metal connection 206 lies outside the PIN pattern 204. This fourth result is obtained through a contact operation plus a non-inclusion operation. In step seven, if the result is the fourth result, an error message is displayed indicating that the pattern has exceeded its boundaries. That is, the metal connection 206 intersects with the PIN pattern 204, but some areas of the metal connection 206 extend beyond the area of the PIN pattern 204, exhibiting a non-inclusion relationship. This can be obtained through a NOT ENCLOSURE operation, and in this case, an error message is displayed indicating that the pattern has exceeded its boundaries. Figure 5D As shown, if a portion of the trace 310 of the metal interconnect 206 extends beyond the PIN pattern 204, an error message will be displayed indicating that the trace has exceeded the pattern.
[0079] This invention, through classifying the effective layers of layout 201 and setting corresponding configuration files based on the process settings of layout 201 data, enables efficient and accurate automatic inspection of IP module wiring on various process platforms. By selecting the configuration file corresponding to the process and performing corresponding calculations based on the boundary layers, front-end layers, and back-end layers formed by the layout 201 classification, this invention can significantly shorten the running time and improve the accuracy of the inspection results. Therefore, this invention can achieve efficient and accurate automatic inspection of IP module connection wiring in layout 201, can be extended to various process platforms, has a shorter running time, and provides more accurate results.
[0080] For customer layout data with PIN-based outputs within the composite IP boundary, the following needs to be checked:
[0081] 1. No front-end layout layers unrelated to the back-end metal interconnects should extend into the IP area;
[0082] 2. The back-end metal wiring of the customer's layout extends into the IP area but is not connected to the IP pin;
[0083] 3. The IP's PIN is not connected to the customer's metal wire, causing the PIN to float.
[0084] 4. The customer's back-end metal connection is connected to the IP PIN, and then connected to other areas or metal wiring.
[0085] Clearly, the embodiments of the present invention can detect the above four points. Therefore, the embodiments of the present invention provide a highly efficient and accurate automatic inspection method for IP connections and traces after IP synthesis using the common IP boundary pin-out method. The method of the embodiments of the present invention differs from previous methods that use visual inspection or simple processes with long processing times. The method of the embodiments of the present invention can be extended to various process platforms, has a shorter processing time, and provides more accurate results.
[0086] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for automatically checking connection of IP module traces after synthesis of an IP module, characterized by, The method comprises the following steps: Step one, divide the effective levels of the layout into three categories, which are boundary level, front-end level and back-end level; The boundary level is the level of the IP module covering the whole IP module region; The back-end level includes the metal interconnection patterns in the back-end process outside the boundary level; the metal interconnection patterns include metal lines for electrical connection and vias between the metal lines; The front-end level includes the patterns of the front-end process outside the boundary level and the back-end level; Step two, establish the corresponding configuration file according to different processes, which includes the parameters of the levels of the boundary level, the back-end level and the front-end level; The parameters of the levels of the configuration file include the level number; Step three, provide the layout after IP module synthesis, detect the process of the layout data, and select the corresponding configuration file according to the name of the process; Step four, calculate the top metal line according to the configuration file; The top metal includes multiple metals with different thicknesses, and the top metal line is obtained by calculation of the metal lines with different thicknesses; Step five, calculate whether there is a pattern in the front-end level entering the IP module region corresponding to the boundary level; Step six, calculate whether the PIN pattern of the IP module in the boundary level will contact the metal line in the back-end level; Step seven, check the metal line in the back-end level entering the IP module region of the boundary level.
2. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 1, characterized in that: The front-end process of each level is used to manufacture semiconductor devices on a semiconductor substrate.
3. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 2, characterized in that: The back-end process is used to manufacture the metal interconnection patterns of each level of the semiconductor device.
4. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 1, characterized in that: The calculation of step five is realized by the AND operation of the pattern in the front-end level and the IP module region corresponding to the boundary level.
5. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 4, characterized in that: In step five, if the calculation result shows that there is a pattern in the front-end level entering the IP module region corresponding to the boundary level, the pattern of the front-end level entering the IP module region corresponding to the boundary level is reported as an error.
6. The method of claim 1, wherein the method of automatically checking the connection of the IP module pins after the synthesis of the IP module is characterized by: The calculation of step six is realized by contact operation and non-contact operation.
7. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 6, characterized in that: In step six, if the calculation result shows that the PIN pattern does not contact the corresponding metal line, it means that the PIN pattern is floating, and the floating PIN pattern is reported as an error.
8. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 1, characterized in that: The checking result of step seven includes: The first result is that the metal line does not contact the PIN pattern; The second result is that the metal line is tangent to the PIN pattern; The third result is that the metal line intersects the PIN pattern and the metal line is inside the PIN pattern; The fourth result is that the metal line intersects the PIN pattern, but part of the metal line is outside the PIN pattern.
9. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 8, characterized in that: The first result is obtained by non-contact operation, and the wiring error is reported when the checking result in step seven is the first result.
10. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 8, characterized in that: The second result is obtained by contact operation, and the metal line contacts the edge of the PIN pattern.
11. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 8, characterized in that: The third result is obtained by contact operation plus inclusion operation.
12. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 8, characterized in that: The fourth result is obtained by contact operation plus non-inclusion operation, and the out-of-graph error is reported when the checking result in step seven is the fourth result.
13. The method for automatically checking the wiring of the connected IP module after synthesizing the IP module as described in claim 1, characterized in that: The layout data in step three is in GDS format.
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