Through-Silicon Via Crack Detection Circuit, Detection Method and Memory

Abstract

An embodiment of the present application discloses a through-silicon via crack detection circuit, a detection method, and a memory. Among them, the through-silicon via crack detection circuit includes: a crack detection line disposed around the through-silicon via; the through-silicon via penetrates through M interconnected metal layers; the number of the crack detection lines is M - 1, and the M - 1 crack detection lines are respectively located in each of the M metal layers except the top metal layer; the M is a positive integer greater than 1; a first contact located on the top metal layer and at a first position connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers; and a second contact located on the top metal layer and at a second position connected to the M - 1 crack detection lines; wherein, according to the resistance between the first contact and the second contact, it is determined whether there is a crack around the through-silicon via.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a through-silicon via crack detection circuit, a detection method, and a memory. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits has been continuously reduced, and the device interconnection density has been continuously increased. The traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, the vertical interconnection stacked packaging method based on the through-silicon via (TSV) technology, with its key technical advantages of short-distance interconnection and high-density integration, has gradually led the trend of the development of packaging technology. However, cracks generated by large-sized TSVs can affect the performance of semiconductor devices.

[0003] Therefore, in the related art, there is an urgent need for a detection circuit and a detection method that can effectively measure whether there are cracks around the through-silicon via.

[0004] Content of the Application

[0005] To solve the related technical problems, embodiments of the present application provide a through-silicon via crack detection circuit, a detection method, and a memory.

[0006] Embodiments of the present application provide a through-silicon via crack detection circuit, including:

[0007] A crack detection line disposed around the through-silicon via; the through-silicon via penetrates through M interconnected metal layers; the number of the crack detection lines is M - 1, and the M - 1 crack detection lines are respectively located in each of the M metal layers except the top metal layer; M is a positive integer greater than 1;

[0008] A first contact located on the top metal layer and at a first position connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers; and

[0009] A second contact located on the top metal layer and at a second position connected to the M - 1 crack detection lines; wherein, whether there are cracks around the through-silicon via is determined according to the resistance between the first contact and the second contact.

[0010] In the above solution, M≥3; each of the M - 1 crack detection lines is connected in series.

[0011] In the above solution, the bottom metal layer in the M metal layers is connected to the crack detection line located in the bottom metal layer;

[0012] The through-silicon via crack detection circuit further includes a connecting component; the M-1 crack detection lines all have notches, and the tail end of the adjacent i-th crack detection line among the M-1 crack detection lines is connected to the head end of the (i + 1)-th crack detection line through the connecting component, so that each of the M-1 crack detection lines is connected in series; i is a positive integer, and 1 ≤ i ≤ M - 2.

[0013] In the above solution, the cross-sectional shapes of the M-1 crack detection lines are all regular polygons; the centers of symmetry of the M-1 crack detection lines coincide with the center of symmetry of the through-silicon via.

[0014] In the above solution, the projections of the M-1 regular polygons where the M-1 crack detection lines are located on a preset plane overlap or do not overlap; the preset plane is perpendicular to the extending direction of the through-silicon via.

[0015] In the above solution, the cross-sectional shapes of the M-1 crack detection lines are all squares, and the projections of the M-1 squares on a preset plane overlap.

[0016] In the above solution, the cross-sectional shapes of the M-1 crack detection lines are all octagons, and the projections of the M-1 octagons on a preset plane overlap.

[0017] In the above solution, the cross-sectional shapes of the M-1 crack detection lines are all squares, and there is a misalignment of N degrees between the projections of any two of the M-1 squares on a preset plane; N = 360° / (M - 1).

[0018] In the above solution, the material of the crack detection line is the same as the material of the corresponding metal layer.

[0019] In the above solution, the through-silicon via includes an analog through-silicon via.

[0020] An embodiment of the present application further provides a memory, including:

[0021] A substrate;

[0022] A functional layer covering the substrate;

[0023] A memory array located in the functional layer;

[0024] M interconnected metal layers located on the functional layer; the top metal layer among the M interconnected metal layers is used to connect to external devices; M is a positive integer greater than 1;

[0025] A through-silicon via penetrating the substrate and the M interconnected metal layers;

[0026] The through-silicon via crack detection circuit provided by the embodiment of the present application.

[0027] In the above solution, M = 4; the materials of the 4 interconnected metal layers are tungsten, copper, copper, and aluminum from bottom to top; the materials of the 3 crack detection lines are tungsten, copper, and copper from bottom to top.

[0028] In the above solution, the bottom metal layer among the 4 metal layers is connected to the crack detection line located in the bottom metal layer, and each of the 3 crack detection lines is connected in series; the cross-sectional shapes of the 3 crack detection lines are all octagons; the symmetry centers of the 3 crack detection lines all coincide with the symmetry center of the through-silicon via; the projections of the 3 octagons overlap in a preset plane; the preset plane is perpendicular to the extending direction of the through-silicon via.

[0029] In the above solution, the bottom metal layer among the 4 metal layers is connected to the crack detection line located in the bottom metal layer, and each of the 3 crack detection lines is connected in series; the cross-sectional shapes of the 3 crack detection lines are all squares; the symmetry centers of the 3 crack detection lines all coincide with the symmetry center of the through-silicon via; there is a 120° misalignment in the projections of any two of the 3 squares in a preset plane; the preset plane is perpendicular to the extending direction of the through-silicon via.

[0030] In the above solution, the through-silicon via includes an analog through-silicon via.

[0031] A plurality of memory chip regions and scribe lanes located between the plurality of memory chip regions are formed on the substrate.

[0032] The analog through-silicon via and the through-silicon via crack detection circuit are both disposed in the scribe lane.

[0033] In the above solution, the memory includes a dynamic random access memory.

[0034] An embodiment of the present application further provides a method for detecting cracks in a through-silicon via, which is applied to testing the through-silicon via crack detection circuit provided by the embodiment of the present application. The detection method includes:

[0035] Providing current to the first contact of the through-silicon via crack detection circuit.

[0036] Measuring the voltage difference between the first contact and the second contact.

[0037] Determining the resistance between the first contact and the second contact through the voltage difference.

[0038] When the resistance is greater than a preset threshold, it is determined that there are cracks around the through-silicon via.

[0039] Embodiments of the present application provide a through-silicon via crack detection circuit, a detection method, and a memory. Among them, the through-silicon via crack detection circuit includes: a crack detection line disposed around the through-silicon via; the through-silicon via penetrates through M interconnected metal layers; the number of the crack detection lines is M - 1, and the M - 1 crack detection lines are respectively located in each of the M metal layers except the top metal layer; M is a positive integer greater than 1; a first contact located on the top metal layer and at a first position connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers; and a second contact located on the top metal layer and at a second position connected to the M - 1 crack detection lines; wherein, according to the resistance between the first contact and the second contact, it is determined whether there is a crack around the through-silicon via. In the embodiments of the present application, by setting a crack detection line around the through-silicon via in the metal layer, and setting a first contact and a second contact on the top metal layer, and the first contact is connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers, and the second contact is connected to the M - 1 crack detection lines. It can be understood that when a crack appears in the through-silicon via and the crack extends to the crack detection line disposed around the through-silicon via, the resistance at the crack test line will change, and thus the resistance between the first contact and the second contact will also change. Based on this, according to the resistance between the first contact and the second contact, it can be determined whether there is a crack around the through-silicon via, that is, the through-silicon via crack detection circuit provided by the embodiments of the present application can effectively judge whether there is a crack. Description of the Drawings

[0040] Figure 1 It is a schematic diagram of the relationship curve between the energy release rate and the crack length of the crack opening outward and the crack opening inward beside the through-silicon via provided by the embodiments of the present application;

[0041] Figure 2 It is a schematic diagram of the composition of a through-silicon via crack detection circuit provided by the embodiments of the present application;

[0042] Figure 3a It is a schematic diagram of the structure of a through-silicon via crack detection circuit provided by the embodiments of the present application;

[0043] Figure 3b It is a schematic cross-sectional view of a through-silicon via crack detection circuit provided by the embodiments of the present application;

[0044] Figure 4 It is an equivalent circuit schematic diagram of a through-silicon via crack detection circuit provided by the embodiments of the present application;

[0045] Figure 5 It is a schematic diagram of the structure of another through-silicon via crack detection circuit provided by the embodiments of the present application;

[0046] Figure 6 This is a schematic structural diagram of another through-silicon via crack detection circuit provided by an embodiment of the present application;

[0047] Figure 7 This is a schematic diagram of the implementation process of a through-silicon via crack detection method provided by an embodiment of the present application. Detailed implementation manners

[0048] Hereinafter, the exemplary embodiments disclosed in the present application will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that a more thorough understanding of the present application can be obtained and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0049] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present application, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0050] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0051] It should be understood that spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience in describing the relationship of one element or feature shown in the drawings to other elements or features. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms are intended to also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, then an element or feature described as "under other elements" or "beneath" or "under" will be oriented "over" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0053] It should be noted that: "First", "Second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0054] In order to more fully understand the features and technical content of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration purposes only and are not used to limit the embodiments of the present application.

[0055] Figure 1 It is a schematic diagram of the relationship curve between the energy release rate and the crack length of the cracks opening outward and inward beside the through-silicon via provided for the embodiments of the present application. In practical applications, whether there are cracks around the through-silicon via can be detected by a through-silicon via crack detection circuit.

[0056] The embodiments of the present application provide a through-silicon via crack detection circuit. Figure 2 It is a schematic diagram of the structural composition of a through-silicon via crack detection circuit provided for the embodiments of the present application. As Figure 2 shown, the through-silicon via crack detection circuit 20 includes:

[0057] Crack detection lines 201, disposed around the through-silicon via; the through-silicon via penetrates through M interconnected metal layers; the number of the crack detection lines includes M - 1, and the M - 1 crack detection lines are respectively located in each of the M metal layers except the top metal layer; M is a positive integer greater than 1;

[0058] A first contact 202, located on the top metal layer and at a first position connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers; and

[0059] A second contact 203, located on the top metal layer and at a second position connected to the M - 1 crack detection lines; wherein, whether there are cracks around the through-silicon via is determined according to the resistance between the first contact and the second contact.

[0060] The crack detection circuit in the embodiments of the present application is mainly used to detect whether there are cracks beside the through - silicon via. The through - silicon via crack detection circuit in the embodiments of the present application can be arranged beside the real through - silicon via, or beside the simulated through - silicon via located in the scribe line.

[0061] Here, the through - silicon via penetrates through multiple interconnected metal layers. It should be noted that each of the multiple interconnected metal layers is not a continuous metal layer, but a layer formed by many dispersed metal lines. The interconnected metal layers can be understood as metal lines that are electrically connected among multiple metal layers.

[0062] Here, the crack detection line is arranged in the metal layer and can be made of the same material as the metal lines in the metal layer. The crack detection line needs to be arranged around the through - silicon via, and the distance at which the crack detection line is arranged around the through - silicon via should be determined according to empirical values. The shape of the crack detection line is not limited. The crack detection line can be in a closed shape or an open shape. The number of crack detection lines is one less than the number of metal layers, that is, one crack detection line is arranged in each of the other metal layers except the top metal layer.

[0063] Here, the first contact and the second contact are located at different positions on the top - surface metal layer, and the first contact is electrically connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers; the second contact is electrically connected to the M - 1 crack detection lines.

[0064] In the embodiments of the present application, there can be various situations for the connection manner between the second contact and multiple crack detections. For example, each of the multiple crack detection lines is connected in series or in parallel and then connected to the second contact.

[0065] It can be understood that when cracks appear around the through - silicon via, the cracks spread to some of the crack detection lines, and the cracks divide these crack detection lines. The resistance of these crack detection lines changes before and after being divided by the cracks. In the embodiments of the present application, through the first contact and the second contact, at least one of the multiple crack detection lines can be connected to the test circuit in the form of resistance, so that it can be detected whether the resistance of the crack detection line changes through the first contact and the second contact, and further determine whether there are cracks around the through - silicon via.

[0066] At the same time, multiple - layer crack detection lines are designed in the through - silicon via crack detection circuit of the embodiments of the present application. When the resistance of one crack detection line changes, the through - silicon via crack detection circuit of the embodiments of the present application can identify it, so as to judge the situation of the cracks. Therefore, the through - silicon via crack detection circuit provided by the embodiments of the present application has high sensitivity.

[0067] In some embodiments, M≥3; each of the M - 1 crack detection lines is connected in series.

[0068] Here, each of the multiple crack detection lines is connected in series and then connected to the second contact. One implementation of the series connection is that each of the M - 1 crack detection lines has a notch, and any two adjacent crack detection lines are connected head - to - tail at the notch; another implementation of the series connection is that each of the M - 1 crack detection lines is closed, and any one crack detection line is connected to the other two adjacent crack detection lines at different positions. Compared with the latter implementation, in the former implementation of the series connection, when the crack causes a change in resistance, the change in resistance is more obvious.

[0069] Based on this, in some embodiments, the bottom metal layer among the M metal layers is connected to the crack detection line located in the bottom metal layer;

[0070] The through - silicon via crack detection circuit further includes a connection component; each of the M - 1 crack detection lines has a notch, and the tail end of the i - th adjacent crack detection line among the M - 1 crack detection lines is connected to the head end of the (i + 1) - th crack detection line through the connection component, so that each of the M - 1 crack detection lines is connected in series; i is a positive integer, and 1≤i≤M - 2.

[0071] Figure 3a FIG. is a schematic structural diagram of a through - silicon via crack detection circuit provided by an embodiment of the present application. It should be noted that, Figure 3a The left side in FIG. is a top - view schematic diagram of the through - silicon via crack detection circuit, Figure 3a and the right side in FIG. is a three - dimensional schematic diagram corresponding to the through - silicon via crack detection circuit on the left side. Figure 3b is a cross - sectional schematic diagram of the through - silicon via crack detection circuit corresponding to Figure 3a .

[0072] Exemplarily, as shown in Figure 3a , M = 4, that is, there are 4 metal layers: M0, M1, M2, M3, and M3 is the top metal layer. One crack detection line is respectively arranged in M0, M1, and M2; the first contact is connected to the head end of the crack detection line located in the bottom metal layer M0 through 4 interconnected metal layers; all three crack detection lines are provided with notches. The tail end of the crack detection line in M0 is connected to the head end of the crack detection line in M1, and the tail end of the crack detection line in M1 is connected to the head end of the crack detection line in M2; the tail end of the crack detection line in M2 is connected to the second contact through the top metal layer. It should be noted that the head end and the tail end here are different ends of the notch of the crack detection line.

[0073] In practical applications, when the distance between the two crack detection lines (i.e., two metal layers) that the connecting component needs to connect is relatively close, such as M1 and M2, the connecting component may include conductive posts filled in vias, such as copper posts; when the distance between the two crack detection lines (i.e., two metal layers) that the connecting component needs to connect is relatively far, such as M0 and M1, M2 and M3, the connecting component may include contacts, and the conductive material of the contacts may be tungsten.

[0074] It should be noted that Figure 3a In order to show the notches of each through-silicon via crack detection line, the size of the notches is shown in a relatively large size. It should be understood that in practical applications, the notch size of each crack detection line is very small, and the notch size only needs to be able to distinguish the connecting components connecting adjacent two layers of crack detection lines.

[0075] Figure 4 This is an equivalent circuit schematic diagram of a through-silicon via crack detection circuit provided by an embodiment of the present application. Figure 4 R0 in can be regarded as the resistance corresponding to the crack detection line in the M0 metal layer, R1 can be regarded as the resistance corresponding to the crack detection line in the M1 metal layer, and R2 can be regarded as the resistance corresponding to the crack detection line in the M2 metal layer.

[0076] In practical applications, the shape of the crack detection lines in the embodiment of the present application is not limited. When the cross-sectional shapes of the M-1 crack detection lines are all regular polygons, and the symmetry centers of the M-1 crack detection lines all coincide with the symmetry center of the through-silicon via, it is more conducive to simplifying and unifying the production manufacturing process.

[0077] Based on this, in some embodiments, the cross-sectional shapes of the M-1 crack detection lines are all regular polygons; the symmetry centers of the M-1 crack detection lines all coincide with the symmetry center of the through-silicon via.

[0078] Here, the cross-sectional shapes of the M-1 crack detection lines may include equilateral triangles, squares, regular pentagons, regular hexagons, etc. In some embodiments, the cross-sectional shapes of the M-1 crack detection lines may also include circles.

[0079] In practical applications, the relative positional relationship between the M-1 crack detection lines in the embodiment of the present application is not restricted.

[0080] In some embodiments, the projections of the M-1 regular polygons where the M-1 crack detection lines are located on a preset plane overlap or do not overlap; the preset plane is perpendicular to the extension direction of the through-silicon via.

[0081] Here, the projections of the M-1 regular polygons where the M-1 crack detection lines are located on the preset plane may overlap (as shown in Figure 3a the situation shown); the projections of the M-1 regular polygons where the M-1 crack detection lines are located on the preset plane may also not overlap, that is, there is a misalignment between the M-1 crack detection lines.

[0082] In some embodiments, the cross-sectional shapes of the M-1 crack detection lines are all squares, and the projections of the M-1 squares on the preset plane overlap.

[0083] Here, the solution where the cross-sectional shape of the crack detection line is a square and the projections on the preset plane overlap can still be understood with reference to Figure 3a the example shown.

[0084] It can be seen that in the above solution, all the crack detection lines are connected between the first contact and the second contact of the measurement point in series. In this way, when the impedance of the crack detection line in any layer changes, it can be simply and conveniently measured through the first contact and the second contact. Compared with only setting one layer of crack detection lines, or the measurement points being connected to the crack detection lines in parallel, the above solution can measure a wider range of crack thicknesses, and when cracks appear, the change in the measured resistance value is greater.

[0085] In the above solution where the cross-sectional shape of the crack detection line is a square and the projections on the preset plane overlap, the crack measurement lines formed in M0, M1, and M2 are all squares aligned around the TSV, and as shown in Figure 3a the through-silicon via, the distance (L1) from the through-silicon via to the four sides of the square is closer than the distance (L2) to the four corners of the square. Based on this, when performing crack testing, when a crack occurs at the diagonal position, if the crack does not extend long enough, it may not be measurable, that is, the crack generated at the diagonal position is difficult to truly reflect.

[0086] Based on the above situation, in the embodiments provided below in this application, the crack measurement lines formed in M0, M1, and M2 are improved to be octagons aligned or squares arranged in a staggered manner, so that the distances from the through-silicon via to eight directions or twelve directions are all relatively close, thereby reducing the possibility of cracks generated at the diagonal position being missed, that is, improving the sensitivity of crack measurement.

[0087] It can be understood that in practical applications, the projected shape of the cross-section of the M-1 crack detection lines can be regular polygons aligned, and the more sides there are, the closer the distances from the through-silicon via to more directions are, thereby reducing the possibility of cracks generated at the diagonal position being missed. However, in practical applications, as the number of sides increases, the complexity of the exposure process will be greatly improved. Therefore, in practical applications, the number of sides of the regular polygon can be weighed and selected according to the actual situation.

[0088] In some embodiments, the cross-sectional shapes of the M - 1 crack detection lines are all octagons, and the projections of the M - 1 octagons overlap in a preset plane.

[0089] Figure 5 FIG. is a schematic diagram of a through - silicon via of another through - silicon via crack detection circuit provided by an embodiment of the present application. It should be noted that, Figure 5 The left side in FIG. is a top - view schematic diagram of the through - silicon via crack detection circuit, Figure 5 and the right side in FIG. is a three - dimensional schematic diagram corresponding to the through - silicon via crack detection circuit on the left side.

[0090] Exemplarily, as Figure 5 shown, M = 4, that is, there are 4 metal layers: M0, M1, M2, M3, and M3 is the top metal layer. A crack detection line is respectively provided in M0, M1, and M2. The cross - sectional shapes of the 3 crack detection lines are all octagons, and the projections of the 3 crack detection lines in the preset plane overlap; the first contact is connected to the head end of the crack detection line in the bottom metal layer M0 through 4 interconnected metal layers; notches are provided in all three crack detection lines. The tail end of the crack detection line in M0 is connected to the head end of the crack detection line in M1, and the tail end of the crack detection line in M1 is connected to the head end of the crack detection line in M2; the tail end of the crack detection line in M2 is connected to the second contact through the top metal layer. It should be noted that the head end and the tail end here are different ends of the notch of the crack detection line.

[0091] It can be understood that in this embodiment, by changing the cross - sectional shape of the crack detection line, that is, using octagonal wiring to optimize the distance distribution between the detection line and the through - silicon via, the crack effect can be better reflected in eight directions; at the same time, when the octagon where the cross - section of the crack detection line is located can be exactly covered by the square where the cross - section of the crack detection line in the previous embodiment is located, compared with the square, the octagon can further reduce the distance between the inflection point of the crack detection line and the through - silicon via, so that the crack detection line can better reflect the crack effect in the inflection point direction.

[0092] It can be understood that in practical applications, the projection shapes of the cross - sections of the M - 1 crack detection lines can be misaligned (shifted) polygons, and the misalignment angles between different crack detections can be the same or different.

[0093] In some embodiments, the cross - sectional shapes of the M - 1 crack detection lines are all squares, and there is a misalignment of N degrees between the projections of any two of the M - 1 squares in a preset plane; N = 360° / (M - 1).

[0094] Figure 6This is another structural schematic diagram of a through - silicon - via crack detection circuit provided by an embodiment of the present application. It should be noted that, Figure 6 The left side in [figure] is a top - view schematic diagram of the through - silicon - via crack detection circuit, Figure 6 and the right side in [figure] is a three - dimensional schematic diagram corresponding to the through - silicon - via crack detection circuit on the left side.

[0095] Exemplarily, as Figure 6 shown, M = 4, that is, there are 4 metal layers: M0, M1, M2, M3, and M3 is the top metal layer. A crack detection line is respectively arranged in M0, M1, and M2. The cross - sectional shapes of the 3 crack detection lines are all regular polygons, and the projections of the 3 crack detection lines in a preset plane have a 120 - degree misalignment; the first contact is connected to the head end of the crack detection line in the bottom metal layer M0 through 4 interconnected metal layers; notches are provided on all three crack detection lines. The tail end of the crack detection line in M0 is connected to the head end of the crack detection line in M1, and the tail end of the crack detection line in M1 is connected to the head end of the crack detection line in M2; the tail end of the crack detection line in M2 is connected to the second contact through the top metal layer. It should be noted that the head end and the tail end here are respectively different ends of the notch of the crack detection line.

[0096] It should be noted that, for Figure 6 the square scheme with misalignment shown in [figure], the crack measurement lines in each of the layers M0, M1, and M2 are still square. However, considering that the through - silicon - via is very large in actual applications, the distance between M0, M1, and M2 is not particularly large. When a crack occurs around the through - silicon - via, it is very likely that the crack extends to the crack detection lines in multiple metal layers in the direction along the through - silicon - via. That is to say, the crack may be at the diagonal of the crack detection line in a certain metal layer, but the crack simultaneously extends to the edges of the crack detection lines in the upper and lower metal layers adjacent to this metal layer. At this time, even if the crack cannot extend to the diagonal of the crack detection line in this metal layer, as long as the crack can extend to the edges of the crack detection lines in the adjacent upper and lower metal layers, it can still be detected. Based on this, setting the crack detection lines in different metal layers with misalignment can also improve the sensitivity of crack measurement.

[0097] It should be noted that, Figure 3a 、 Figure 3b 、 Figure 4 、 Figure 5 、 Figure 6 P1 in [figure] is the probe placed on the first contact, and P2 is the probe placed on the second contact.

[0098] It can be understood that in this implementation, the cross-sectional shape of the crack detection line remains unchanged, i.e., a square is still used, and only the wiring direction of the crack detection line in each layer is changed, so as to optimize the distance distribution between the crack detection line and the through-silicon via, so that the crack effect can be better reflected in twelve directions.

[0099] Based on the above through-silicon via crack detection circuit, an embodiment of the present application further provides a through-silicon via crack detection method, and this detection is applied to test the through-silicon via crack detection circuit provided in the embodiment of the present application, as Figure 7 shown, the detection method includes:

[0100] Step 701: Provide current to the first contact of the through-silicon via crack detection circuit;

[0101] Step 702: Measure the voltage difference between the first contact and the second contact;

[0102] Step 703: Determine the resistance between the first contact and the second contact through the voltage difference;

[0103] Step 704: When the resistance is greater than a preset threshold, determine that there is a crack around the through-silicon via.

[0104] In practical applications, after the design of the above through-silicon via crack detection circuit is determined, when there is no crack around the through-silicon via, the resistance between the first contact and the second contact is within a certain range; when there is a crack around the through-silicon via, the crack detection lines reached by the crack expansion are broken, and the resistance of these crack detection lines becomes larger, and finally the resistance measured through the first contact and the second contact becomes larger.

[0105] Here, the preset threshold can be adjusted according to the actual through-silicon via crack detection circuit.

[0106] Based on the above through-silicon via crack detection circuit, an embodiment of the present application further provides a memory, including:

[0107] A substrate;

[0108] A functional layer covering the substrate;

[0109] A memory array located in the functional layer;

[0110] M interconnected metal layers located on the functional layer; the top metal layer of the M interconnected metal layers is used to connect to external devices; M is a positive integer greater than 1;

[0111] Through-silicon vias penetrating the substrate and the M interconnected metal layers; and

[0112] The through-silicon via crack detection circuit provided in the embodiment of the present application.

[0113] Here, the functional layer can be understood as various thin film layers on the substrate for forming a memory storage array or ensuring the normal operation of the storage array.

[0114] In some embodiments, M = 4; the materials of the 4 interconnected metal layers are tungsten, copper, copper, and aluminum from bottom to top; the materials of the 3 crack detection lines are tungsten, copper, and copper from bottom to top.

[0115] In some embodiments, the bottom metal layer among the 4 metal layers is connected to the crack detection line located in the bottom metal layer, and each of the 3 crack detection lines is connected in series; the cross-sectional shapes of the 3 crack detection lines are all octagons; the symmetry centers of the 3 crack detection lines coincide with the symmetry center of the through-silicon via; the projections of the 3 octagons overlap in a preset plane; the preset plane is perpendicular to the extension direction of the through-silicon via.

[0116] In some embodiments, the bottom metal layer among the 4 metal layers is connected to the crack detection line located in the bottom metal layer, and each of the 3 crack detection lines is connected in series; the cross-sectional shapes of the 3 crack detection lines are all squares; the symmetry centers of the 3 crack detection lines coincide with the symmetry center of the through-silicon via; there is a 120° misalignment in the projections of any two of the 3 squares in a preset plane; the preset plane is perpendicular to the extension direction of the through-silicon via.

[0117] In some embodiments, the through-silicon via includes an analog through-silicon via.

[0118] A plurality of memory chip regions and scribing lanes located between the plurality of memory chip regions are formed on the substrate.

[0119] The analog through-silicon via and the through-silicon via crack detection circuit are both disposed in the scribing lane.

[0120] Here, the through-silicon via includes an analog through-silicon via, and the analog through-silicon via and the through-silicon via crack detection circuit, which is a kind of test circuit, are both disposed in the scribing lane to reduce the impact on other normal working circuits of the memory.

[0121] In some embodiments, the memory includes a dynamic random access memory.

[0122] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitude of the serial numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0123] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0124] As mentioned above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A through-silicon via crack detection circuit, characterized in that Including: A crack detection line disposed around the through-silicon via; The through-silicon via penetrates through M interconnected metal layers; the number of the crack detection lines is M - 1, and the M - 1 crack detection lines are respectively located in each of the M metal layers except the top metal layer; The M is a positive integer greater than 1; A first contact located on the top metal layer and at a first position connected to at least one of the M - 1 crack detection lines through the M interconnected metal layers; And A second contact located on the top metal layer and at a second position connected to the M - 1 crack detection lines; wherein, whether there is a crack around the through-silicon via is determined according to the resistance between the first contact and the second contact; wherein, The projected shape of the M - 1 crack detection lines in a preset plane is a staggered polygon, and the staggered angles between different crack detection lines are the same or different; the preset plane is perpendicular to the extension direction of the through-silicon via.

2. The through-silicon via crack detection circuit according to claim 1, characterized in that, The M ≥ 3; each of the M - 1 crack detection lines is connected in series.

3. The through-silicon via crack detection circuit according to claim 2, characterized in that The bottom metal layer in the M metal layers is connected to the crack detection line located in the bottom metal layer; The through-silicon via crack detection circuit further includes a connection component; the M - 1 crack detection lines all have notches, and the tail end of the adjacent i-th crack detection line in the M - 1 crack detection lines is connected to the head end of the (i + 1)-th crack detection line through the connection component, so that each of the M - 1 crack detection lines is connected in series; the i is a positive integer, and 1 ≤ i ≤ M - 2.

4. The through-silicon via crack detection circuit according to claim 1, wherein The cross-sectional shapes of the M - 1 crack detection lines are all regular polygons; the symmetry centers of the M - 1 crack detection lines all coincide with the symmetry center of the through-silicon via.

5. The through-silicon via crack detection circuit according to claim 4, characterized in that, The cross-sectional shapes of the M - 1 crack detection lines are all squares.

6. The through-silicon via crack detection circuit according to claim 4, wherein The cross-sectional shapes of the M - 1 crack detection lines are all octagons.

7. The through-silicon via crack detection circuit according to claim 4, wherein The cross-sectional shapes of the M - 1 crack detection lines are all squares, and any two of the M - 1 squares have a stagger of N degrees in the projection in the preset plane; the N = 360° / (M - 1).

8. The through-silicon via crack detection circuit according to claim 1, characterized in that The material of the crack detection line is the same as the material of the corresponding metal layer.

9. The through-silicon via crack detection circuit according to claim 1, wherein The through-silicon via includes an analog through-silicon via.

10. A memory, characterized in that, Including: A substrate; A functional layer covering the substrate; A memory array located in the functional layer; M interconnected metal layers located on the functional layer; the top metal layer in the M interconnected metal layers is used to connect to an external device; the M is a positive integer greater than 1; A through-silicon via penetrating through the substrate and the M interconnected metal layers; The through-silicon via crack detection circuit according to any one of claims 1 to 9.

11. The memory according to claim 10, characterized in that, The M = 4; the materials of the 4 interconnected metal layers from bottom to top are tungsten, copper, copper, and aluminum in sequence; the materials of the 3 crack detection lines from bottom to top are tungsten, copper, and copper in sequence.

12. The memory according to claim 11, wherein The bottom metal layer among the four metal layers is connected to the crack detection lines located in the bottom metal layer, and each of the three crack detection lines is connected in series; the cross-sectional shapes of the three crack detection lines are all octagons; the symmetry centers of the three crack detection lines coincide with the symmetry center of the through-silicon via.

13. The memory according to claim 11, characterized in that, The bottom metal layer among the four metal layers is connected to the crack detection lines located in the bottom metal layer, and each of the three crack detection lines is connected in series; the cross-sectional shapes of the three crack detection lines are all squares; the symmetry centers of the three crack detection lines coincide with the symmetry center of the through-silicon via; there is a 120° misalignment in the projection of any two of the three squares on the preset plane.

14. The memory according to claim 10, wherein The through-silicon via includes an analog through-silicon via. A plurality of memory chip regions and saw streets located between the plurality of memory chip regions are formed on the substrate. The analog through-silicon via and the through-silicon via crack detection circuit are both disposed in the saw street.

15. The memory according to claim 10, wherein The memory includes a dynamic random access memory.

16. A method for detecting through-silicon via cracks, characterized in that, Applied to test the through-silicon via crack detection circuit according to any one of claims 1 to 9, the detection method includes: Providing a current to a first contact of the through-silicon via crack detection circuit. Measuring the voltage difference between the first contact and the second contact. Determining the resistance between the first contact and the second contact through the voltage difference. When the resistance is greater than a preset threshold, determining that there are cracks around the through-silicon via.

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