storage device

Abstract

Embodiments provide a storage device capable of improving characteristics of the storage device. The storage device of the embodiments includes a first wiring provided above a substrate in a first direction perpendicular to a first surface of the substrate, a second wiring provided between the substrate and the first wiring, and a storage unit provided between the first wiring and the second wiring, including a switching element and a magnetoresistance effect element arranged in the first direction. The magnetoresistance effect element includes a first electrode, a second electrode provided above the first electrode in the first direction, a non-magnetic layer provided between the first electrode and the second electrode, a first magnetic layer provided between the first electrode and the non-magnetic layer, a second magnetic layer provided between the second electrode and the non-magnetic layer, and a first layer provided between the second electrode and the second magnetic layer. The first layer contains at least one selected from magnesium, a transition metal, and a lanthanoid and oxygen. A first dimension of the first layer in the first direction is 1.1 times or more and 2 times or less of a second dimension of the non-magnetic layer in the first direction.

Description

[0001] This application claims priority to Japanese Patent Application No. 2021-149447 (Filing date: September 14, 2021) and U.S. Patent Application No. 17 / 550,194 (Filing date: December 14, 2021). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0002] Embodiments of the present application relate to a storage device. BACKGROUND

[0003] A storage device using a variable resistance element (for example, a magnetoresistive effect element) as a storage element is known. In order to improve the characteristics of the storage device, research and development of various technologies related to the storage device are being advanced. SUMMARY

[0004] A technical problem to be solved by the present application is to provide a storage device capable of improving the characteristics of the storage device.

[0005] The storage device of the embodiment includes a first wiring provided above a substrate in a first direction perpendicular to a first surface of the substrate, a second wiring provided between the substrate and the first wiring, and a storage unit provided between the first wiring and the second wiring, including a switching element and a magnetoresistive effect element arranged in the first direction. The magnetoresistive effect element includes a first electrode, a second electrode provided above the first electrode in the first direction, a non-magnetic layer provided between the first electrode and the second electrode, a first magnetic layer provided between the first electrode and the non-magnetic layer, a second magnetic layer provided between the second electrode and the non-magnetic layer, and a first layer provided between the second electrode and the second magnetic layer. The first layer contains at least one selected from magnesium, a transition metal, and a lanthanoid element and oxygen. A first dimension of the first layer in the first direction is 1.1 times or more and 2 times or less of a second dimension of the non-magnetic layer in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram showing a structure example of the storage device of the first embodiment.

[0007] Figure 2 is a diagram showing a structure example of a storage unit array of the storage device of the first embodiment.

[0008] Figure 3 is a bird's-eye view showing a structure example of a storage unit array of the storage device of the first embodiment.

[0009] Figure 4is a cross-sectional view showing a structure example of a memory cell array of the storage device of the first embodiment.

[0010] Figure 5 is a cross-sectional view showing a structure example of a memory cell array of the storage device of the first embodiment.

[0011] Figure 6 is a cross-sectional view showing a structure example of a memory cell of the storage device of the first embodiment.

[0012] Figure 7 is a diagram for explaining a structure example of a memory element of the storage device of the first embodiment.

[0013] Figure 8 is a cross-sectional view for explaining a comparative example of the storage device of the first embodiment.

[0014] Figure 9 is a cross-sectional view showing a structure example of a memory cell of the storage device of the second embodiment.

[0015] Figure 10 is a cross-sectional view showing a structure example of a memory cell of the storage device of the third embodiment.

[0016] Figure 11 is a cross-sectional view showing a structure example of a memory cell of the storage device of the fourth embodiment.

[0017] Explanation of Reference Numerals

[0018] 100: storage device; 1: memory element; 2: selector; 11, 13: magnetic layer; 12: tunnel barrier layer; 14: shift cancel layer; 16: base layer; 17: cap layer. DETAILED DESCRIPTION

[0019] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same reference numerals are assigned to elements having the same function and structure.

[0020] In each of the following embodiments, with respect to a plurality of constituent elements that are the same (for example, a circuit, a wiring, various voltages, and signals, and the like), a number / English character for distinguishing is sometimes assigned at the end of a reference numeral. In a case where the constituent elements that are assigned the reference numeral with the number / English character for distinguishing at the end are not distinguished from each other, a description (reference numeral) in which the number / English character at the end is omitted is used.

[0021] [EMBODIMENT]

[0022] Reference Figures 1-11 The storage device of the embodiment will be described.

[0023] (1) First Embodiment

[0024] Reference Figures 1-8 The storage device of the first embodiment will be described.

[0025] [a] Configuration Example

[0026] Reference Figures 1-7 The configuration example of the storage device of the embodiment will be described.

[0027] (a-1) Overall Configuration

[0028] Figure 1 is a view showing the configuration example of the storage device of the present embodiment.

[0029] As shown in Figure 1 , the storage device 100 of the present embodiment is connected to a device (hereinafter referred to as an external device) 900 outside the storage device 100.

[0030] The external device 900 transmits a command CMD, an address ADR, and a control signal CNT to the storage device 100. Data DT is transferred between the storage device 100 and the external device 900. The external device 900 transmits data to be written into the storage device 100 (hereinafter referred to as write data) to the storage device 100 at the time of a write operation. The external device 900 accepts data read from the storage device 100 (hereinafter referred to as read data) from the storage device 100 at the time of a read operation.

[0031] The storage device 100 of the present embodiment includes a storage unit array 110, a row control circuit 120, a column control circuit 130, a write circuit 140, a read circuit 150, a voltage generation circuit 160, an input / output circuit 170, and a control circuit 180.

[0032] The storage unit array 110 includes a plurality of storage units MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0033] Each of the plurality of storage units MC is associated with each of a plurality of rows and a plurality of columns within the storage unit array 110. Each storage unit MC is connected to a corresponding one of the plurality of word lines WL. Each storage unit MC is connected to a corresponding one of the plurality of bit lines BL.

[0034] The row control circuit 120 is connected with the memory cell array 110 via the word lines WL. The row control circuit 120 accepts a row address (or a decoded result of the row address) of the memory cell array 110 in the address ADR. The row control circuit 120 controls the plurality of word lines WL based on the decoded result of the row address. Thereby, the row control circuit 120 sets each of the plurality of word lines WL (a plurality of rows) to a selected state or a non-selected state. In the following, the word line WL set to the selected state is referred to as a selected word line WL, and the word line WL other than the selected word line WL is referred to as a non-selected word line WL.

[0035] The column control circuit 130 is connected with the memory cell array 110 via the bit lines BL. The column control circuit 130 accepts a column address (or a decoded result of the column address) of the memory cell array 110 in the address ADR. The column control circuit 130 controls the plurality of bit lines BL based on the decoded result of the column address. Thereby, the column control circuit 130 sets each of the plurality of bit lines BL (a plurality of columns) to a selected state or a non-selected state. In the following, the bit line BL set to the selected state is referred to as a selected bit line BL, and the bit line BL other than the selected bit line BL is referred to as a non-selected bit line BL.

[0036] The write circuit 140 performs data write to the memory cell MC. The write circuit 140 supplies a voltage (or a current) for data write to each of the selected word line WL and the selected bit line BL. Thereby, a certain write voltage (or a write current) is supplied to the selected memory cell MC. The write circuit 140 can supply a certain voltage of a plurality of write voltages corresponding to the write data to the selected memory cell MC. For example, the plurality of write voltages each have a polarity (bias direction) corresponding to the write data. For example, the write circuit 140 includes a write driver (not shown), a write sink (not shown), and the like.

[0037] The read circuit 150 performs data read from the memory cell MC. The read circuit 150 amplifies a signal output from the selected memory cell MC to the selected bit line BL. The read circuit 150 discriminates data in the memory cell MC based on the amplified signal. For example, the read circuit 150 includes a preamplifier (not shown), a sense amplifier (not shown), a read driver (not shown), a read sink (not shown), and the like.

[0038] The voltage generation circuit 160 generates voltages used for various operations of the memory cell array 110 using a power supply voltage supplied from the external device 900. For example, the voltage generation circuit 160 generates various voltages used in a write operation. The voltage generation circuit 160 outputs the generated voltages to the write circuit 140. For example, the voltage generation circuit 160 generates various voltages used in a read operation. The voltage generation circuit 160 outputs the generated voltages to the read circuit 150.

[0039] The input / output circuit 170 functions as an interface circuit of various signals ADR, CMD, CNT, DT between the memory device 100 and the external device 900. The input / output circuit 170 transfers the address ADR from the external device 900 to the control circuit 180. The input / output circuit 170 transfers the command CMD from the external device 900 to the control circuit 180. The input / output circuit 170 transfers various control signals CNT between the external device 900 and the control circuit 180. The input / output circuit 170 transfers the write data DT from the external device 900 to the write circuit 140. The input / output circuit 170 transfers the data DT from the read circuit 150 to the external device 900 as read data.

[0040] The control circuit (also referred to as a sequencer, a state machine, an internal controller) 180 decodes the command CMD. The control circuit 180 controls the operations of the row control circuit 120, the column control circuit 130, the write circuit 140, the read circuit 150, the voltage generation circuit 160, and the input / output circuit 170 in the memory device 100 on the basis of the decoding result of the command CMD and the control signal CNT. The control circuit 180 decodes the address ADR. The control circuit 180 sends the decoding result of the address ADR to the row control circuit 120 and the column control circuit 130, and the like. For example, the control circuit 180 includes a register circuit (not shown) that temporarily stores the command CMD and the address ADR. Furthermore, the register circuit, a circuit (command decoder) for decoding the command CMD, and a circuit (address decoder) for decoding the address ADR can be provided in the memory device 100 outside the control circuit 180.

[0041] (a-2) Memory cell array

[0042] Reference Figures 2-5 The structure example of the memory cell array in the memory device of the present embodiment will be described.

[0043] Figure 2 is an equivalent circuit diagram showing the structure example of the memory cell array of the memory device of the present embodiment.

[0044] As Figure 2As shown, a plurality of memory cells MC are arranged in a matrix form within the memory cell array 110. Each memory cell MC is connected to a corresponding one of a plurality of bit lines BL (BL<0>, BL<1>,..., BL<i-1>) and a corresponding one of a plurality of word lines WL (WL<0>, WL<1>,..., WL<j-1>). i and j are integers of 2 or more.

[0045] Each memory cell MC includes a storage element 1 and a selector 2.

[0046] The storage element 1 is, for example, a variable resistance element. The resistance state of the storage element 1 changes to one of a plurality of resistance states (for example, a low resistance state and a high resistance state) in accordance with a voltage (or a current) supplied thereto. The storage element 1 is capable of storing data by associating the resistance state of the element 1 with the data (for example, "0" data and "1" data).

[0047] The selector 2 functions as a selection element of the memory cell MC. The selector 2 has a function of controlling the supply of a voltage (or a current) to the storage element 1 at the time of data writing to and reading from the corresponding storage element 1.

[0048] The selector 2 is, for example, a two-terminal type switching element. For example, in a case where a voltage applied across the two terminals of the switching element 2 as the selector 2 is less than a threshold voltage of the switching element 2, the switching element 2 changes to an off state (a high resistance state, an electrically non-conductive state). In a case where the voltage applied across the two terminals of the switching element 2 is equal to or more than the threshold voltage of the switching element 2, the switching element 2 changes to an on state (a low resistance state, an electrically conductive state). The two-terminal type switching element 2 can have the above-described function regardless of the polarity (for example, a positive polarity and a negative polarity) of the voltage applied thereto.

[0049] The switching element 2 is capable of switching whether a current flows or does not flow in the memory cell MC in accordance with the magnitude of the voltage applied to the memory cell MC, regardless of the polarity of the voltage applied in the memory cell MC (the direction of the current flowing in the memory cell MC).

[0050] In addition to this, the switching element 2 can further include at least one or more elements selected from boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), and antimony (Sb).

[0051] Further, as the two-terminal type switching element 2 of the selector 2, for example, an insulator containing a dopant (impurity) can also be included. The dopant added to the insulator is an impurity that contributes to electric conduction in the insulator. One example of the insulator used in the switching element 2 is silicon oxide. In the case where the material of the switching element 2 is silicon oxide, the dopant added to the silicon oxide is phosphorus or arsenic. Further, the kind of the dopant added to the silicon oxide of the switching element 2 is not limited to the above example.

[0052] Figures 3-5 is a diagram for describing a configuration example of a memory cell array 110 of the storage device 100 of the present embodiment. Figure 3 is a bird's-eye view for describing a configuration example of the memory cell array 110. Figure 4 is a schematic cross-sectional view showing a cross-sectional configuration of the memory cell array 110 along the Y direction (Y axis). Figure 5 is a schematic cross-sectional view showing a cross-sectional configuration of the memory cell array 110 along the X direction (X axis).

[0053] As shown in Figures 3-5 , the memory cell array 110 is provided on the upper surface of the substrate 90.

[0054] The X direction is a direction parallel to the upper surface of the substrate 90. The Y direction is a direction parallel to the upper surface of the substrate 90 and intersecting the X direction. In the following, a plane parallel to the upper surface of the substrate 90 is referred to as an X-Y plane. A direction (axis) perpendicular to the X-Y plane is set as the Z direction (Z axis). A plane parallel to a plane constituted by the X direction and the Z direction is referred to as an X-Z plane. A plane parallel to a plane constituted by the Y direction and the Z direction is referred to as a Y-Z plane.

[0055] A plurality of wirings (conductive layers) 50 is provided above the upper surface of the substrate 90 in the Z direction across the insulating layer 91 on the substrate 90. The plurality of wirings 50 is arranged along the X direction. Each wiring 50 extends along the Y direction. The plurality of wirings 50 each functions as, for example, a bit line BL.

[0056] A plurality of wirings (conductive layers) 51 is provided above the plurality of wirings 50 in the Z direction. The plurality of wirings 51 is arranged along the Y direction. Each wiring 51 extends along the X direction. The plurality of wirings 51 each functions as, for example, a word line WL.

[0057] A plurality of memory cells MC is provided between the plurality of wirings 50 and the plurality of wirings 51. The plurality of memory cells MC arranged in the Y direction is provided on one wiring 50 in the Z direction. The plurality of memory cells MC arranged in the Y direction is connected to a common bit line BL.

[0058] The plurality of memory cells MC arranged in the Y direction is provided on one wiring 50 in the Z direction. The plurality of memory cells MC arranged in the Y direction is connected to a common bit line BL.

[0059] The plurality of memory cells MC arranged in the X direction are provided under one wiring 51 in the Z direction. The plurality of memory cells MC arranged in the X direction are connected to a common word line WL.

[0060] A space having a certain size (interval) in the Y direction is provided between the two memory cells MC arranged in the Y direction. A space having a certain size (interval) in the X direction is provided between the two memory cells MC arranged in the X direction. The interval in the Y direction between the memory cells MC is substantially the same as the interval in the X direction between the memory cells MC. However, the interval in the Y direction between the memory cells MC can be different from the interval in the X direction between the memory cells MC.

[0061] For example, in the case of the circuit structure of the memory cell array 110 having Figure 2 The selector 2 is provided under the memory element 1 in the Z direction. The selector 2 is provided between the memory element 1 and the wiring 50. The memory element 1 is provided between the wiring 51 and the selector 2.

[0062] In this way, each memory cell MC is a laminate of the memory element 1 and the selector 2. With this memory cell MC, the memory cell array 110 has a laminated structure.

[0063] Further, the memory cell MC sometimes has a tapered cross-sectional shape depending on the process (for example, etching method) used in the formation of the memory cell array 110.

[0064] Examples in which the insulating layer 91 is provided between the plurality of wirings 50 and the substrate 90 are shown in Figure 4 and Figure 5 In the case where the substrate 90 is a semiconductor substrate, one or more field effect transistors (not shown) can be provided on the semiconductor region of the upper surface of the substrate 90. The field effect transistors are covered with the insulating layer 91. The field effect transistors on the substrate 90 are constituent elements of the circuit of the row control circuit 120 or the like. The field effect transistors are connected to the memory cell array 110 via contact plugs (not shown) and wirings (not shown) in the insulating layer 91. In this way, a circuit for controlling the operation of the memory cell array 110 can be provided under the memory cell array 110 in the Z direction. Further, if the substrate 90 is an insulating substrate, the plurality of wirings 50 can be provided directly on the upper surface of the substrate 90 without the insulating layer 91.

[0065] The circuit structure and configuration of the laminated memory cell array 110 are not limited to Figures 2-5The example shown illustrates this. Based on the connection relationship between storage element 1 and selector 2 relative to bit line BL and word line WL, the circuit structure and configuration of the memory cell array 110 can be appropriately modified. For example, it can have... Figure 2 The construction of the memory cell array 110 with the circuit structure is not limited to Figures 3-5 For example, selector 2 can also be positioned above storage element 1 in the Z direction. In this case, wiring 51 is used as bit line BL, and wiring 50 is used as word line WL.

[0066] (a-3) Storage unit

[0067] Figure 6 This is a cross-sectional view schematically showing a structural example of the storage unit MC in the storage device 100 of this embodiment.

[0068] like Figure 6 As shown, in the storage cell MC of the stacked structure, storage element 1 and selector 2 are arranged in the Z direction. As described above, storage element 1 is positioned on selector 2 in the Z direction.

[0069] For example, the variable resistor element as storage element 1 is a magnetoresistive element. In this case, the storage device 100 of this embodiment is a magnetic memory such as MRAM (Magnetoresistive random access memory).

[0070] <Example of selector structure>

[0071] like Figure 6 As shown, when the selector 2 is a two-terminal switching element, the selector 2 includes at least a variable resistance layer (hereinafter referred to as the selector layer or switch layer) 20 and two electrodes (conductive layers) 21A and 21B. The selector layer 20 is disposed between the two electrodes 21A and 21B in the Z direction. The selector layer 20 is, for example, a variable resistance layer. The selector layer 20 including the variable resistance layer can have multiple resistance states (resistance values).

[0072] exist Figure 6 In this example, electrode 21A (hereinafter also referred to as the lower electrode) is disposed below the selector layer 20 in the Z direction, and electrode 21B (hereinafter also referred to as the upper electrode) is disposed above the selector layer 20 in the Z direction. For example, electrode 21A is disposed between wiring 50 and selector layer 20. Electrode 21B is disposed between selector layer 20 and magnetoresistive element 1.

[0073] Selector 2 is connected to wiring 50 via electrode 21A. Selector 2 is connected to magnetoresistive element 1 via electrode 21B.

[0074] According to the voltage applied to the selector 2 (the memory cell MC), the resistance state of the selector layer 20 becomes a high resistance state (non-conduction state) or a low resistance state (conduction state). In the case where the resistance state of the selector layer 20 is the high resistance state, the selector 2 is off. In the case where the resistance state of the selector layer 20 is the low resistance state, the selector 2 is on.

[0075] In the case where the memory cell MC is set to the selection state, the selector 2 is on, and thus the resistance state of the selector layer 20 becomes the low resistance state. In this case, the selector 2 supplies the voltage (or the current) to the memory element 1. In the case where the memory cell MC is set to the non-selection state, the selector 2 is off, and thus the resistance state of the selector layer 20 becomes the high resistance state. In this case, the selector 2 cuts off the voltage (or the current) to the memory element 1.

[0076] Further, depending on the material of the selector layer 20, the change in the resistance state of the selector layer 20 sometimes also depends on the current (for example, the magnitude of the current) flowing in the selector 2 (the memory cell MC).

[0077] <Structure Example of Magnetic Resistance Effect Element>

[0078] The magnetic resistance effect element 1 includes two magnetic layers 11, 13 and a non-magnetic layer 12. The non-magnetic layer 12 is provided between the two magnetic layers 11, 13 in the Z direction. In the example of Fig. 1, the magnetic layer 11, the non-magnetic layer 12, and the magnetic layer 13 are arranged in this order in the Z direction from the wiring (for example, the bit line) 50 side toward the wiring (for example, the word line) 51 side. Figure 6

[0079] The two magnetic layers 11, 13 and the non-magnetic layer 12 form a magnetic tunnel junction. In the following, the magnetic resistance effect element 1 including the magnetic tunnel junction is referred to as an MTJ element 1. The non-magnetic layer 12 in the MTJ element 1 is referred to as a tunnel barrier layer.

[0080] The magnetic layers 11, 13 are, for example, ferromagnetic layers containing cobalt (Co), iron (Fe), and / or boron (B), or the like. The magnetic layers 11, 13 can be either single-layer films (for example, alloy films) or multi-layer films (for example, artificial lattice films). The tunnel barrier layer 12 is, for example, an insulating layer (for example, a magnesium oxide layer) containing oxygen and magnesium. The tunnel barrier layer 12 can be either a single-layer film or a multi-layer film. Further, the tunnel barrier layer 12 can also contain elements other than oxygen and magnesium.

[0081] In the present embodiment, the MTJ element 1 is a magnetic resistance effect element of the perpendicular magnetization type.

[0082] ​For example, each magnetic layer 11 and 13 has perpendicular magnetic anisotropy. The easy magnetization axis of each magnetic layer 11 and 13 is perpendicular to the surface (film) of the magnetic layers 11 and 13. Each magnetic layer 11 and 13 has magnetization perpendicular to the surface of the magnetic layers 11 and 13. The magnetization direction of each magnetic layer 11 and 13 is parallel to the alignment direction (Z direction) of the magnetic layers 11 and 13.

[0083] The magnetization direction of one of the two magnetic layers 11 and 13 is variable, while the magnetization direction of the other magnetic layer remains constant. The MTJ element 1 can have multiple resistance states (resistance values) depending on the relative relationship (magnetization arrangement) between the magnetization directions of one magnetic layer and the other magnetic layer.

[0084] exist Figure 6 In this example, the magnetization direction of magnetic layer 13 is variable. The magnetization direction of magnetic layer 11 remains constant (fixed state). Hereinafter, magnetic layer 13 with variable magnetization direction is referred to as a storage layer. Hereinafter, magnetic layer 11 with constant magnetization direction (fixed state) is referred to as a reference layer. Furthermore, storage layer 13 is sometimes also referred to as a free layer, a magnetized free layer, or a magnetized variable layer. Reference layer 11 is sometimes also referred to as a pinned layer, a pinned layer, a magnetized constant layer, or a magnetized fixed layer.

[0085] Furthermore, according to the circuit structure of the memory cell array 110, the following situation also exists: the reference layer is disposed above the tunnel barrier layer 12 in the Z direction, and the memory layer is disposed below the tunnel barrier layer 12 in the Z direction.

[0086] In this embodiment, "the magnetization direction of the reference layer (magnetic layer) remains unchanged" or "the magnetization direction of the reference layer (magnetic layer) is fixed" means that when a current or voltage for changing the magnetization direction of the storage layer 13 is supplied to the MTJ element 1, the magnetization direction of the reference layer 11 will not change before or after the supply of the current or voltage, depending on the supplied current or voltage.

[0087] In a case where the magnetization direction of the storage layer 13 is the same as the magnetization direction of the reference layer 11 (in a case where the magnetization alignment state of the MTJ element 1 is a parallel alignment state), the resistance state of the MTJ element 1 is a first resistance state. In a case where the magnetization direction of the storage layer 13 is different from the magnetization direction of the reference layer 11 (in a case where the magnetization alignment state of the MTJ element 1 is an anti-parallel alignment state), the resistance state of the MTJ element 1 is a second resistance state different from the first resistance state. The resistance value of the MTJ element 1 in the second resistance state (anti-parallel alignment state) is higher than the resistance value of the MTJ element 1 in the first resistance state (parallel alignment state). In the following, with respect to the magnetization alignment state of the MTJ element 1, the parallel alignment state is also described as a P state, and the anti-parallel alignment state is also described as an AP state.

[0088] For example, the MTJ element 1 includes two electrodes (conductive layers) 19A, 19B. The magnetic layers 11, 13 and the tunnel barrier layer 12 are provided between the two electrodes 19A, 19B in the Z direction. The reference layer 11 is provided between the electrode 19A and the tunnel barrier layer 12. The storage layer 13 is provided between the electrode 19B and the tunnel barrier layer 12.

[0089] For example, the offset canceling layer 14 can also be provided within the MTJ element 1. In this case, the offset canceling layer 14 is provided between the reference layer 11 and the electrode 19A. The offset canceling layer 14 is a magnetic layer for moderating the influence of the leakage magnetic field of the reference layer 11. In a case where the MTJ element 1 includes the offset canceling layer 14, the non-magnetic layer 15 is provided between the offset canceling layer 14 and the reference layer 11. The non-magnetic layer 15 is, for example, a metal layer such as a ruthenium layer. The offset canceling layer 14 is antiferromagnetically coupled with the reference layer 11 via the non-magnetic layer 15. Thereby, the stack including the reference layer 11 and the offset canceling layer 14 forms a SAF (Synthetic antiferromagnetic) configuration. In the SAF configuration, the magnetization direction of the offset canceling layer 14 becomes opposite to the magnetization direction of the reference layer 11. By the SAF configuration, the magnetization direction of the reference layer 11 can more stably become a fixed state. Further, the set of the two magnetic layers 11, 14 and the non-magnetic layer 15 forming the SAF configuration is also sometimes referred to as the reference layer.

[0090] For example, the non-magnetic layer (hereinafter referred to as a base layer) 16 can also be provided between the offset canceling layer 14 and the electrode 19A. The base layer 16 is a layer for improving the characteristics (for example, crystallinity and magnetic characteristics) of the magnetic layer (here, the offset canceling layer 14) in contact with the base layer 16.

[0091] The base layer 16 is a non-magnetic layer (for example, a conductive compound layer). Further, the base layer 16 can also be regarded as a constituent element of the lower electrode 19A.

[0092] In the present embodiment, the MTJ element 1 includes a cap layer 17.

[0093] The cap layer 17 is provided between the magnetic layer (here, the storage layer) 13 and the upper electrode 19B. The cap layer 17 is a non-magnetic layer. The cap layer 17 is a layer for improving the characteristics (for example, crystallinity and magnetic characteristics) of the magnetic layer (here, the storage layer 13) in contact with the cap layer 17.

[0094] In the present embodiment, the material of the cap layer 17 is the same as the material of the tunnel barrier layer 12. In the case where the material of the tunnel barrier layer 12 contains oxygen and magnesium, the material of the cap layer 17 contains oxygen and magnesium. In the case where the tunnel barrier layer 12 is a magnesium oxide layer, the cap layer 17 is a magnesium oxide layer. For example, the composition of the magnesium oxide used in the cap layer 17 is substantially the same as the composition of the magnesium oxide used in the tunnel barrier layer 12. However, the composition of the magnesium oxide used in the cap layer 17 is sometimes different from the composition of the magnesium oxide used in the tunnel barrier layer 12. Furthermore, the cap layer 17 can also contain elements other than oxygen and magnesium, like the tunnel barrier layer 12.

[0095] For example, the storage unit MC has a size H1 in the Z direction. The size H1 of the storage unit MC corresponds to the size between the upper surface of the wiring 50 (the bottom surface of the electrode 21A of the selector 2) and the bottom surface of the wiring 51 (the upper surface of the upper electrode 19B of the MTJ element 1).

[0096] In the MRAM of the present embodiment, the cap layer 17 is used as a built-in resistor (BIR) in the storage unit MC in addition to the function of improving the characteristics of the magnetic layer 13.

[0097] The cap layer (hereinafter also referred to as BIR cap layer) 17 as a built-in resistor prevents the storage unit MC from being damaged due to excessive current flowing in the storage unit MC.

[0098] The resistance R0 of the tunnel barrier layer 12 and the resistance R1 of the cap layer 17 vary in correspondence with the film thickness t0 of the tunnel barrier layer 12 and the film thickness t1 of the cap layer 17.

[0099] In the present embodiment, the film thickness t1 of the cap layer 17 is thicker than the film thickness t0 of the tunnel barrier layer 12.

[0100] Thus, in the case where the material of the cap layer 17 is the same as the material of the tunnel barrier layer 12, the resistance R1 of the cap layer 17 becomes higher than the resistance R0 of the tunnel barrier layer 12.

[0101] For example, in order to function as an internal resistance element, the resistance Rl of the cap layer 17 is preferably 2 times or more the resistance R0 of the tunnel barrier layer 12. As a result, the MRAM 100 of the present embodiment can suppress the flow of an excessive current in the memory cell MC that can cause damage (e.g., insulation damage of the tunnel barrier layer) of the MTJ element 1.

[0102] Figure 7 is a graph showing the relationship between the film thickness ratio of the tunnel barrier layer and the cap layer and the resistance ratio of the tunnel barrier layer and the cap layer.

[0103] In Figure 7 , the horizontal axis of the graph indicates the ratio (tl / t0) of the film thickness tl of the cap layer 17 to the film thickness t0 of the tunnel barrier layer 12, and the vertical axis of the graph indicates the ratio (Rl / R0) of the resistance Rl of the cap layer 17 to the resistance R0 of the tunnel barrier layer 12. The vertical axis of the graph is indicated by a Log scale.

[0104] In the present embodiment, the resistance R0 of the tunnel barrier layer 12 and the resistance Rl of the cap layer 17 are evaluated based on the resistance area product. In the following, the value of the resistance area product is denoted as an RA value.

[0105] In Figure 7 , the material of the cap layer 17 is the same as the material of the tunnel barrier layer 12. The tunnel barrier layer 12 and the cap layer 17 are magnesium oxide layers.

[0106] As Figure 7 indicated, in the case where the ratio (tl / t0) of the film thickness tl of the cap layer 17 to the film thickness t0 of the tunnel barrier layer 12 is 1.1, the ratio (Rl / R0) of the RA value of the cap layer 17 to the RA value of the tunnel barrier layer 12 becomes 2 or more.

[0107] That is, in the case where the film thickness tl of the cap layer 17 is 1.1 times the film thickness t0 of the tunnel barrier layer 12, the RA value Rl of the cap layer 17 becomes 2 times the RA value R0 of the tunnel barrier layer 12.

[0108] In order for the desired operation of the memory cell MC, the film thickness tl of the BIR cap layer 17 is 2.0 times or less the film thickness t0 of the tunnel barrier layer 12. In this case, the resistance Rl of the BIR cap layer 17 is 100 times or less the resistance R0 of the tunnel barrier layer 12.

[0109] However, in consideration of the load of the supply of voltage or current for the write operation and the read operation of the memory cell MC and the operation (for example, the supply ability of voltage or current) of the write circuit 140 and the read circuit 150, the RA ratio (R1 / R0) of the BIR cap layer 17 with respect to the tunnel barrier layer 12 is preferably 10 or less. Thus, the film thickness t1 of the cap layer 17 is more preferably 1.5 times or less of the film thickness t0 of the tunnel barrier layer 12. In this case, the resistance R1 of the BIR cap layer 17 is 10 times or less of the resistance R0 of the tunnel barrier layer 12. For example, the film thickness t1 of the cap layer 17 is 1.3 times or less or 1.4 times or less of the film thickness t0 of the tunnel barrier layer 12. In this case, the resistance R1 of the BIR cap layer 17 is 5 times or less of the resistance R0 of the tunnel barrier layer 12.

[0110] Thus, even if the cap layer 17 is used as the internal resistance element (BIR), no adverse effect on the various operations of the memory cell MC occurs.

[0111] Further, depending on the structure of the memory cell array and the memory cell, the resistance (RA value) of the cap layer 17 as the internal resistance element is sometimes 100 times or more of the resistance value of the tunnel barrier layer 12. In this case, the film thickness t1 of the cap layer 17 can be set to be 2 times or more of the film thickness t0 of the tunnel barrier layer 12.

[0112] The operation of the MRAM 100 of the present embodiment is performed based on the known write operation and the known read operation. For example, at the time of the write operation, a desired write current is supplied to the memory cell MC by the supply of voltage or current to the word line WL and the bit line BL. For example, at the time of the read operation, a desired read current is supplied to the memory cell MC by the supply of voltage or current to the word line WL and the bit line BL.

[0113] In addition, the MRAM 100 of the present embodiment is formed using a known manufacturing method. Thus, in the present embodiment, the description of the manufacturing method of the MRAM 100 of the present embodiment is omitted.

[0114] However, as described above, in the present embodiment, the film thickness t0 of the tunnel barrier layer 12 and the film thickness t1 of the cap layer 17 are controlled so that the film thickness t1 of the cap layer 17 of the MTJ element 1 is 1.1 times or more (and 2 times or less) of the film thickness t0 of the tunnel barrier layer 12 of the MTJ element 1.

[0115] [b] SUMMARY

[0116] In a storage device (for example, an MRAM) having a stacked memory cell array, constituent members (for example, a wiring) within the memory cell array have a parasitic capacitance.

[0117] In the operation of the storage unit in the selected state, the selector is in the off state in the storage unit in the non-selected state. The wiring connected to the storage unit in the non-selected state is charged by the current or voltage supplied to the wiring.

[0118] In the case where the storage unit connected to the wiring in the charged state is selected as the operation target, in order to set the selector to the on state, a voltage equal to or higher than the threshold voltage (or current) of the selector is applied to the wiring.

[0119] In the case where the selector becomes the on state, the wiring in the charged state is discharged. Thereby, in addition to the current (write current or read current) for the predetermined operation of the storage unit, the discharge current of the wiring is also supplied to the storage unit.

[0120] In the following, the total current of the current for the operation of the storage unit and the discharge current is referred to as an overshoot current.

[0121] The overshoot current flows in the storage unit that becomes the selected state. In the case where the magnitude of the overshoot current exceeds the allowable value related to the current of the storage element (for example, the tunnel barrier layer of the MTJ element) in the storage unit, the storage element (for example, the tunnel barrier layer) can be damaged.

[0122] In consideration of the characteristic unevenness of the element, sometimes an internal resistance element is provided in each storage unit in order to suppress the damage of the storage element caused by the overshoot current.

[0123] In the case where the internal resistance element is provided in the storage unit, the size of the storage unit in the Z direction (the height of the storage unit) becomes higher by an amount corresponding to the size of the internal resistance element in the Z direction.

[0124] In order to improve the storage density of the storage unit array, the size of the space between the adjacent storage units has a tendency to be reduced.

[0125] For example, the aspect ratio of the storage unit in the storage unit array is defined by the ratio of the height of the storage unit to the size of the space between the adjacent storage units (the interval between the storage units).

[0126] In the case where the size of the space between the adjacent storage units in the storage unit array is set to a certain value, the aspect ratio of the storage unit including the internal resistance element becomes larger than the aspect ratio of the storage unit not including the internal resistance element.

[0127] Figure 8 is a drawing for explaining a comparative example of the MRAM of the present embodiment.

[0128] Figure 8(a) shows a structure of a memory cell array of an MRAM of a comparative example.

[0129] In Figure 8 In (a) of the comparative example, each memory cell MCZ includes an internal resistance element 8Z. The internal resistance element 8Z is an element independent of the MTJ element 1Z and the selector 2. For example, the internal resistance element 8Z includes a resistance layer 80 and at least one electrode 81. The resistance layer (a layer including at least one of a silicon oxide layer and a silicon nitride layer) 80 is provided between the wiring 50 and the electrode 21A of the selector 2. The electrode 81 is provided between the resistance layer 80 and the wiring 50. Further, there are also cases where an electrode (a conductive layer) of the internal resistance element 8Z is provided between the resistance layer 80 and the electrode 21A.

[0130] In Figure 8 In the MRAM of the comparative example of (a), the film thickness t1Z of the cap layer 17Z is thinner than the film thickness t0 of the tunnel barrier layer 12. For example, the film thickness t1Z of the cap layer 17Z is 0.6 times or less of the film thickness t0 of the tunnel barrier layer 12. Thus, the resistance (RA value) of the cap layer 17Z is smaller than the resistance of the tunnel barrier layer 12.

[0131] The dimension tBIR in the Z direction of the internal resistance element 8Z is larger than the film thickness t0 of the tunnel barrier layer 12. For example, the dimension tBIR is larger than the total thickness of the film thickness t0 and the film thickness t1Z. In general, the dimension tBIR is sufficiently larger than 1.1 times (and 2 times) of the film thickness t0.

[0132] The dimension in the Z direction of the memory cell MCZ is "HZ". The dimension of the space between the adjacent memory cells MCZ is "DZ". The aspect ratio of the memory cell MCZ is "HZ / DZ".

[0133] When the aspect ratio is high, the margin (for example, a processing margin) related to the space for separation between the memory cells MCZ becomes small. As a result, due to the poor separation between the memory cells MCZ, short-circuiting of the adjacent memory cells can occur.

[0134] In order to completely separate the adjacent memory cells MCZ, it is also possible to increase the interval between the memory cells MCZ. However, this can cause a decrease in the storage density of the memory cell array or an increase in the chip size of the MRAM.

[0135] In addition, when the aspect ratio of the memory cell MCZ is large, there is a tendency that the difficulty in forming the memory cell MCZ and the memory cell array (for example, the difficulty in etching) becomes high.

[0136] Figure 8 (b) shows a structure of a memory cell array in the MRAM of the present embodiment.

[0137] As described above, in the present embodiment, the cap layer 17 of each memory cell MC has a function as an internal resistance element (BIR).

[0138] As Figure 8 The dimension of the memory cell MC in the Z direction is "H1" as shown in (b) of FIG. 7. The dimension (interval) of the space between the adjacent memory cells MC is "D1". In the present embodiment, the aspect ratio of the memory cell MC is "H1 / D1".

[0139] Even if the film thickness t1 of the cap layer 17 becomes larger than the film thickness t1Z of the cap layer 17Z of the comparative example, the film thickness t1 is about 1.1 to 2 times the film thickness t0. Further, in the present embodiment, the internal resistance element (element 8Z of (a) of FIG. 7) which is separately provided from the MTJ element 1 and the selector 2 is not provided. Figure 8

[0140] Thus, in the present embodiment, the dimension H1 of the memory cell MC becomes smaller than the dimension HZ of the memory cell MCZ of the comparative example.

[0141] Therefore, in the case where the interval D1 in the MRAM of the present embodiment is equal to the interval DZ in the MRAM of the comparative example, the aspect ratio (H1 / D1) of the memory cell MC becomes smaller than the aspect ratio (HZ / DZ) of the memory cell MCZ.

[0142] Therefore, the MRAM 100 of the present embodiment can suppress the decrease in the storage density of the memory cell array 110 and the increase in the chip size of the MRAM 100.

[0143] As described above, the cap layer 17 of the MRAM 100 of the present embodiment is used as the internal resistance element of the memory cell MC. Thus, the MRAM 100 of the present embodiment can suppress the damage of the MTJ element caused by the excessive overshoot current.

[0144] Further, for the MTJ element 1 as the storage element, in order to suppress the unevenness of the characteristics of the element, the formation process is formed using a formation process which is controlled relatively well.

[0145] Thus, in the case where the cap layer 17 as the constituent member of the MTJ element 1 is used as the internal resistance element, the unevenness of the resistance of the cap layer 17 as the internal resistance element is suppressed. As a result, the MRAM 100 of the present embodiment can suppress the unevenness of the characteristics of the memory cell MC including the internal resistance element with respect to the plurality of memory cells MC within the memory cell array 110.

[0146] ​In addition, in the case where the film thickness of the tunnel barrier layer 12 and the magnesium oxide layer as the cap layer 17 in contact with the storage layer 13 is increased as in the present embodiment, the influence of DMI (Dzyaloshinskii-Moriya Interaction) in the MTJ element 1 becomes large. As a result, the MRAM 100 of the present embodiment can reduce the magnitude of the magnetization reversal threshold current (Ic) of the MTJ element 1.

[0147] As described above, the storage device of the present embodiment can improve the characteristics of the storage device.

[0148] (2) Second Embodiment

[0149] Reference Figure 9 The storage device of the second embodiment will be described.

[0150] Figure 9 is a schematic cross-sectional view showing a structure example of a storage unit of the storage device of the present embodiment.

[0151] In Figure 9 In the storage unit MC shown in FIG. 1, the material of the cap layer 17A is different from the material of the tunnel barrier layer 12.

[0152] For example, a metal oxide is used as the material of the cap layer 17A.

[0153] The metal oxide used in the cap layer 17A contains at least one selected from tantalum (Ta), cobalt (Co), nickel (Ni), iron (Fe), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), gallium (Ga), molybdenum (Mo), zirconium (Zr), ruthenium (Ru), niobium (Nb), tungsten (W), hafnium (Hf), lanthanum (La), and lutetium (Lu).

[0154] For example, the cap layer 17A is a layer containing a transition metal and oxygen, a layer containing a lanthanoid and oxygen, or a layer containing a transition metal, a lanthanoid, and oxygen. As one example, the cap layer 17A is a transition metal oxide layer or a lanthanoid oxide layer. Further, the cap layer 17A can contain magnesium in addition to the transition metal, the lanthanoid, and oxygen.

[0155] The band gap of the transition metal oxide and the lanthanoid oxide has a relatively small band gap. However, the lattice constant of the transition metal oxide and the lanthanoid oxide is larger than the lattice constant of the magnesium oxide. Therefore, by controlling the film thickness of the transition metal oxide layer and the lanthanoid oxide layer, the resistance (RA value) R1A of the cap layer 17A containing the transition metal oxide and the lanthanoid oxide can be controlled.

[0156] In the case where the cap layer 17A is a transition metal oxide layer or a lanthanoid oxide layer, the film thickness t1A of the transition metal oxide layer 17A or the lanthanoid oxide layer 17A is thicker than the film thickness tO of the tunnel barrier layer 12 using magnesium oxide. Thus, the layer 17A containing the transition metal oxide or the lanthanoid oxide functions as a cap layer and functions as an internal resistance element.

[0157] In the present embodiment, the film thickness t1A of the cap layer 17A containing the transition metal oxide or the lanthanoid oxide has a size of 1.1 times or more and 2 times or less (for example, 1.5 times or less) of the film thickness tO of the tunnel barrier layer 12 containing magnesium oxide.

[0158] Thus, the resistance (for example, the RA value) R2 of the cap layer 17A containing the transition metal oxide layer or the lanthanoid oxide layer becomes 2 times or more of the resistance of the tunnel barrier layer 12. For example, the resistance R2 of the cap layer 17A is 100 times or less, and more preferably 10 times or less, of the resistance R0 of the tunnel barrier layer 12.

[0159] Further, an oxide layer (for example, a metal oxide layer) using an element other than the above-described exemplified elements can be used as the cap layer 17A functioning as an internal resistance element. In addition, the cap layer 17A can be a laminated film in which two or more of a magnesium oxide layer, a transition metal oxide layer, and a lanthanoid oxide layer are stacked in the Z direction.

[0160] Thus, the cap layer 17A containing the transition metal oxide or the lanthanoid oxide has the resistance desired for the internal resistance element described above.

[0161] As a result, the storage device of the present embodiment can obtain substantially the same effects as the storage device of the above-described embodiment.

[0162] (3) Third Embodiment

[0163] Reference Signs Figure 10 The storage device of the third embodiment will be described.

[0164] Figure 10 is a schematic cross-sectional view showing a structure example of a storage unit of the storage device of the present embodiment.

[0165] In Figure 10 In the storage unit MC shown in FIG. 8, the offset elimination layer 14A has a function as an internal resistance within the storage unit MC.

[0166] The resistance (e.g., RA value) R3 of the offset canceling layer 14A is higher than the resistance R0 of the tunnel barrier layer 12. As described above, the resistance of the internal resistance element is preferably 2 times or more the resistance R0 of the tunnel barrier layer 12. Thus, for example, the RA value R3 of the offset canceling layer 14A is set to be 2 times or more the RA value R0 of the tunnel barrier layer 12. For example, the RA value R3 of the offset canceling layer 14A is set to be 100 times or less, and more preferably 10 times or less, the RA value R0 of the tunnel barrier layer 12.

[0167] The film thickness of the offset canceling layer 14A and the material of the offset canceling layer 14A are controlled so that the RA value R3 of the offset canceling layer 14A becomes higher than the RA value R0 of the tunnel barrier layer 12 while the magnetic layer 14A maintains the function as the offset canceling layer 14A. In this case, the film thickness and the material of the reference layer 11 and the film thickness and the material of the nonmagnetic layer 15 can also be controlled together with the film thickness and the material of the offset canceling layer 14A.

[0168] For example, in the present embodiment, the film thickness tIX of the cap layer 17X is thinner than the film thickness tO of the tunnel barrier layer 12. Thus, the resistance (RA value) RIX of the cap layer 17X is lower than the resistance (RA value) R0 of the tunnel barrier layer 12.

[0169] Further, it is also possible that both the cap layer (e.g., the cap layer of the first embodiment or the second embodiment) and the offset canceling layer 14A are used as the internal resistance element.

[0170] The storage device of the present embodiment can obtain the same effects as the above-described embodiments.

[0171] (4) Fourth Embodiment

[0172] Reference Figure 11 The storage device of the fourth embodiment will be described.

[0173] Figure 11 is a schematic cross-sectional view showing a structure example of a storage unit of the storage device of the present embodiment.

[0174] In Figure 11 In the example of FIG. 17, the base layer 16A is used as the internal resistance element.

[0175] In this case, the resistance (e.g., RA value) R4 of the base layer 16A is higher than the resistance R0 of the tunnel barrier layer 12. For example, the resistance R4 of the base layer 16A is 2 times or more and 100 times or less (more preferably 10 times or less) the resistance R0 of the tunnel barrier layer 12.

[0176] The RA value of the base layer (hereinafter also referred to as BIR base layer) 16A as an internal resistance element is set to be higher than the RA value of the tunnel barrier layer 12 by controlling the material of the base layer 16A and the film thickness of the base layer 16A and the like.

[0177] For example, the BIR base layer 16A includes a layer (hereinafter referred to as resistance layer) 60 formed of the same material as the material of the tunnel barrier layer 12 (for example, a material containing oxygen and magnesium). The film thickness t2 of the resistance layer (for example, a magnesium oxide layer) 60 is thicker than the film thickness tO of the tunnel barrier layer (for example, a magnesium oxide layer) 12. In this case, as described above, the film thickness t2 of the resistance layer 60 has a thickness of 1.1 times or more and 2.0 times or less (for example, 1.5 times or less) of the film thickness tO of the tunnel barrier layer 12. Figure 7 As illustrated, the film thickness t2 of the resistance layer 60 has a thickness of 1.1 times or more and 2.0 times or less (for example, 1.5 times or less) of the film thickness tO of the tunnel barrier layer 12.

[0178] Further, the material of the resistance layer 60 can also be the material containing a transition metal and oxygen (for example, a transition metal oxide) or the material containing a lanthanoid and oxygen (for example, a lanthanoid oxide) described above. In the case where the resistance layer 60 is a transition metal oxide layer or a lanthanoid oxide layer, the film thickness t2 of this resistance layer 60 is 1.1 times or more and 2.0 times or less (for example, 1.5 times or less) of the film thickness tO of the tunnel barrier layer 12.

[0179] The entirety of the base layer 16A can also be a layer formed of the same material as the material of the tunnel barrier layer 12. In addition, the entirety of the base layer 16A can also be a layer formed of a transition metal oxide or a lanthanoid oxide.

[0180] In the present embodiment, the film thickness tIX of the cap layer 17X is thinner than the film thickness tO of the tunnel barrier layer 12. Thus, the resistance (RA value) of the cap layer 17X is lower than the resistance (RA value) of the tunnel barrier layer 12.

[0181] Further, a configuration in which both the cap layer (for example, the cap layer of the first embodiment or the second embodiment) as an internal resistance element and the base layer 16A as an internal resistance element are used can also be applied.

[0182] As in the present embodiment, even in the case where the base layer 16A of the MTJ element 1 has a function as an internal resistance element, the same effects as those of the above-described embodiments can be obtained.

[0183] (5) Others

[0184] In the above-described embodiments, the MRAM is exemplified as the storage device 100 of the present embodiment. However, the storage device of the present embodiment can also be a storage device other than the MRAM as long as it is a device in which an internal resistance element for stabilization of operation is provided in the storage unit MC.

[0185] For example, the storage device 100 of the present embodiment can also be a storage device using a variable resistance element (for example, a transition metal oxide element) as a storage element (for example, a resistance change memory such as ReRAM), a storage device using a phase change element as a storage element (for example, a phase change memory such as PCRAM), or a storage device using a ferroelectric element as a storage element (for example, a ferroelectric memory such as FeRAM).

[0186] The storage device 100 of the present embodiment can obtain the effects described in the above-described embodiments even if it is a storage device other than an MRAM.

[0187] The above-described embodiments of the present application are illustrative and not restrictive; the present application is applicable to various modifications and alternative forms; specific settings shown in the embodiments are not intended to limit the scope of the present application, and are included in a patentable scope of the present application. Embodiments and / or their modifications encompassed in the scope of the present application contain various substitutions, selectives, and changes that can be conceived by those skilled in the art and belong to the technical scope of the present application. The scope of the present application is not limited by the embodiments described above, but only by the claims.

Claims

1. A storage device comprising: The first wiring is disposed above the substrate in a first direction perpendicular to the first surface of the substrate; The second wiring is disposed between the substrate and the first wiring; as well as A storage cell, disposed between the first wiring and the second wiring, includes switching elements and magnetoresistive elements arranged in the first direction. The magnetoresistive effect element includes: Electrode 1; The second electrode is disposed above the first electrode in the first direction; A non-magnetic layer is disposed between the first electrode and the second electrode; A first magnetic layer is disposed between the first electrode and the non-magnetic layer; A second magnetic layer is disposed between the second electrode and the non-magnetic layer; and The first layer is disposed between the second electrode and the second magnetic layer. The first layer contains at least one selected from magnesium, transition metals, and lanthanides, and oxygen. The first dimension of the first layer in the first direction is more than 1.1 times and less than 2 times the second dimension of the non-magnetic layer in the first direction. The resistance of the first layer is more than twice and less than 100 times the resistance of the non-magnetic layer.

2. The storage device according to claim 1, The transition metal includes at least one selected from tantalum, cobalt, nickel, iron, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gallium, molybdenum, zirconium, ruthenium, niobium, tungsten, and hafnium.

3. The storage device according to claim 1, The lanthanide elements include at least one selected from lanthanum and lutetium.

4. The storage device according to claim 1, The first magnetic layer is a reference layer. The second magnetic layer is a storage layer. The non-magnetic layer is a tunnel barrier layer.

5. The storage device according to claim 1, The magnetization direction of the first magnetic layer is fixed. The magnetization direction of the second magnetic layer is variable.

6. The storage device according to claim 1, The non-magnetic layer contains oxygen and magnesium.

7. A storage device comprising: The first wiring is disposed above the substrate in a first direction perpendicular to the first surface of the substrate; The second wiring is disposed between the substrate and the first wiring; as well as A storage cell, disposed between the first wiring and the second wiring, includes switching elements and magnetoresistive elements arranged in the first direction. The magnetoresistive effect element includes: Electrode 1; The second electrode is disposed above the first electrode in the first direction; A non-magnetic layer is disposed between the first electrode and the second electrode; A first magnetic layer is disposed between the first electrode and the non-magnetic layer; A second magnetic layer is disposed between the second electrode and the non-magnetic layer; and The first layer is disposed between the first electrode and the first magnetic layer. The first layer contains at least one selected from magnesium, transition metals, and lanthanides, and oxygen. The first dimension of the first layer in the first direction is more than 1.1 times and less than 2 times the second dimension of the non-magnetic layer in the first direction. The resistance of the first layer is more than twice and less than 100 times the resistance of the non-magnetic layer.

8. The storage device according to claim 7, The transition metal includes at least one selected from tantalum, cobalt, nickel, iron, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gallium, molybdenum, zirconium, ruthenium, niobium, tungsten, and hafnium.

9. The storage device according to claim 7, The lanthanide elements include at least one selected from lanthanum and lutetium.

10. The storage device according to claim 7, The first magnetic layer is a reference layer. The second magnetic layer is a storage layer. The non-magnetic layer is a tunnel barrier layer.

11. The storage device according to claim 7, The magnetization direction of the first magnetic layer is fixed. The magnetization direction of the second magnetic layer is variable.

12. The storage device according to claim 7, The non-magnetic layer contains oxygen and magnesium.

13. A storage device comprising: The first wiring is disposed above the substrate in a first direction perpendicular to the first surface of the substrate; The second wiring is disposed between the substrate and the first wiring; as well as A storage cell, disposed between the first wiring and the second wiring, includes switching elements and magnetoresistive elements arranged in the first direction. The magnetoresistive effect element includes: Electrode 1; The second electrode is disposed above the first electrode in the first direction; A first non-magnetic layer is disposed between the first electrode and the second electrode; A first magnetic layer is disposed between the first electrode and the first non-magnetic layer; A second magnetic layer is disposed between the second electrode and the first non-magnetic layer; A third magnetic layer is disposed between the first electrode and the first magnetic layer; and A second non-magnetic layer is disposed between the first magnetic layer and the third magnetic layer. The resistance of the third magnetic layer is higher than that of the first non-magnetic layer.

14. The storage device according to claim 13, The first magnetic layer is a reference layer. The second magnetic layer is a storage layer. The third magnetic layer is a displacement elimination layer. The first non-magnetic layer is a tunnel barrier layer.

15. The storage device according to claim 13, The magnetization direction of the first magnetic layer is fixed, while the magnetization direction of the second magnetic layer is variable.

16. The storage device according to claim 15, The magnetization direction of the third magnetic layer is fixed.

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