A method and system for controlling an atomic gravimeter

Abstract

The present application relates to the technical field of atomic gravimeter, and provides an atomic gravimeter control method and system. A hardware address encoder is arranged at a pin of a port of each functional drive board for docking on a switching board. The switching board outputs a unique address code to each functional drive board through the hardware address encoder, so that when each functional drive board interacts with a main control board through a common data bus on the switching board, the main control board can identify the corresponding data source. The main control board and all functional drive boards are integrated on the switching board, without using any external interconnection line for communication and power supply, so that the number of cables in the system is reduced, the miniaturization of the system is facilitated, and the volume and mass of the system are reduced.

Description

[Technical Field]

[0001] This invention relates to the field of atomic gravimeter technology, and in particular to an atomic gravimeter control method and system. [Background Technology]

[0002] An atomic gravimeter is a precision instrument with important applications in geographical research and geological exploration. It involves a large number of terminal hardware peripherals, which in turn requires a large number of control circuit boards.

[0003] Currently, atomic gravimeters employ techniques such as... Figure 1 The circuit control system designed using the cascaded communication method shown here refers to all circuit boards except the main control board as function driver boards. In this system, the main control board communicates with all function driver boards via a bus cascade, and all communication information between the main control board and all function driver boards is transmitted through the bus. All function circuit boards are designed with two communication connector terminals (e.g., ...). Figure 2 As shown), the pins of the two terminals have identical functions. One terminal is connected to the previous functional driver board via an external interconnect, while the other terminal is connected to the next functional driver board via another external interconnect. Atomic gravimeters require excellent interference immunity (such as electromagnetic compatibility interference), which necessitates that the cables used (especially those for high-speed communication) have built-in metal shielding (in high-speed circuits, a significant portion of electromagnetic compatibility problems are caused by cables), and such cables generally have thicker cores and greater weight.

[0004] As the number of circuit boards increases, so does the number of communication interconnections. Excessive cabling can significantly reduce the internal space of the atomic gravimeter control system and increase its overall mass. Therefore, overcoming the shortcomings of existing technology is a pressing issue in this field. [Summary of the Invention]

[0005] The technical problem that this invention aims to solve is that as the number of circuit boards increases, the number of communication interconnections will also increase accordingly. Excessive cables will significantly occupy the internal space of the atomic gravimeter control system and increase the total mass of the gravimeter control system.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for controlling an atomic gravimeter, using an adapter board on which the main control board ports and various functional drive board ports involved in the atomic gravimeter control system are fabricated, the method comprising:

[0008] The adapter board is used to connect to the ports of various functional driver boards, and a hardware address encoder is set at a designated pin; wherein, the hardware address encoder is composed of a preset number of pins, and a unique address code is assigned to each functional driver board by grounding a specified number of pins and / or connecting a specified number of pins to a high level;

[0009] The adapter board outputs a unique address code to each functional driver board through the hardware address encoder, enabling the main control board to identify the corresponding data source when each functional driver board interacts with the main control board through the common data bus on the adapter board.

[0010] Preferably, the process of forming a unique address code assigned to each functional driver board by grounding a specified number of pins and / or connecting a specified number of pins to a high level specifically involves:

[0011] Grounding a pin represents a bit value of 0, and connecting a pin to a high level represents a bit value of 1. A predetermined number of pins are arranged in sequence, and a specified number of pins grounded and / or a specified number of pins connected to a high level constitute an ordered sequence of bits, thereby realizing the unique address encoding assigned to each functional driver board.

[0012] Preferably, the value of the preset number of pins used to determine the unique address code is set according to the total number of functional driver boards that the corresponding adapter board needs to support; wherein, the result of exponentiation of the preset number of pins as the base 2 must be greater than or equal to the total number of functional driver boards that the adapter board needs to support.

[0013] Preferably, the main control board and each functional driver board are connected to the adapter board, and the method after power-on also includes:

[0014] Each functional driver board identifies its unique address code on the current adapter board through the hardware address encoder at its respective port;

[0015] The main control board sends at least three query commands to the function driver board at each address code in turn to confirm whether a function driver board is installed at that address code and the function of that function driver board, and saves the information obtained from the query.

[0016] Preferably, the instruction protocol used by the query instruction consists of 24 bytes, with the first two bytes combined to form instrument type data;

[0017] The third byte is the address byte, where the first 6 bits of binary data represent the address of the target object, and the last two bits are check bits; the fourth byte is the instruction type byte; the eighth byte is the function type byte, where the first 6 bits of binary data represent the function type of the function driver board, and the last 2 bits are verification encryption data, which is calculated by summing the first 6 bits and keeping only the lowest two bits; the 24th byte is the verification encryption byte, which is obtained by summing the first 23 bytes and keeping only 8 bits; bytes 9 to 22 are reserved bits.

[0018] Preferably, the method for the main control board to identify whether a functional driver board is connected to a corresponding port in the adapter board also includes:

[0019] The adapter board is also equipped with a multiplexer, which connects the VA input signal pin of the main control board to the common port of the multiplexer;

[0020] Each input of the multiplexer is connected to the corresponding VA output signal pin of each functional driver board in each port of the adapter board.

[0021] In this system, each functional driver board sets the corresponding VA output signal pin of its own terminal directly to a low level. When a functional driver board is installed at the port of the adapter board, the corresponding input of the multiplexer is pulled low. Otherwise, the pin at the port of the adapter board remains at a high level.

[0022] Preferably, the control signal pins of the multiplexer include pin A, pin B, pin C, pin D, pin INHIBIT, and pin COMMOM; the output signals (VA) can all be connected to the main control board through the VA pins on the adapter board that serve the main control board port. The main control board controls whether the multiplexer works by controlling the INHIBIT signal, and selects to connect a specified input signal and output signal of the multiplexer by controlling pins A, pin B, pin C, and pin D.

[0023] Preferably, the multiplexer supports 16-channel selection. When the number of function driver boards to be configured on the adapter board is greater than 16, the method further includes:

[0024] Multiplexers are added to the single board. The multiplexer that serves the first 16 function driver boards is called the first multiplexer, while the multiplexer that serves the remaining function driver boards is called the second multiplexer.

[0025] At this time, the ports set on the adapter board for the main control board respectively set up INHIBIT1 control signal output pin for the INHIBIT pin of the first multiplexer; and set up INHIBIT2 control signal output pin for the INHIBIT pin of the second multiplexer. Among them, in the ports set up on the adapter board for the main control board, pins A, B, C and D of the first multiplexer and pins A, B, C and D of the second multiplexer share a set of pins A, B, C and D in one port.

[0026] Preferably, the method further includes:

[0027] Each functional driver board is also equipped with a second hardware address encoder and comparator components;

[0028] When the corresponding function driver board is connected to the adapter board, if the level in the hardware address encoder on the corresponding adapter board port and the second hardware address encoder on the function driver board are inconsistent through the comparator component, the comparator component will trigger the indicator light in the function driver board to flash.

[0029] If the level in the hardware address encoder on the corresponding adapter board port and the second hardware address encoder on the function driver board are consistent through the comparator component, the data port connected to the adapter board of the function driver board enters the transmit / receive state.

[0030] Specifically, before the comparator component obtains the verification result, or when the obtained verification result is inconsistent with the evaluation, the data port connected to the corresponding function driver board and the adapter board remains blocked.

[0031] Thirdly, the present invention also provides a system for controlling an atomic gravimeter, characterized in that it includes a main control board, an adapter board, and multiple functional drive boards, wherein the main control board and the multiple functional drive boards are respectively plugged into corresponding ports of the adapter board and are used to implement the method for controlling the atomic gravimeter as described in the first aspect.

[0032] Thirdly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the atomic gravimeter control method described in the first aspect.

[0033] This invention integrates the main control board and all functional driver boards onto a single adapter board, eliminating the need for any external interconnects for communication and power supply. This reduces the number of cables used in the system, which is beneficial for system miniaturization and reduces the system's size and weight.

[0034] On the other hand, through address allocation and hardware / software combined identification, the system can correctly and automatically identify the addresses and functions of all installed function driver boards. Staff can add or remove function driver boards according to actual needs, enhancing the system's scalability and facilitating system maintenance. [Attached Image Description]

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0036] Figure 1 This is a schematic diagram of an atomic gravimeter control system architecture provided in the prior art according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the transmission port of an atomic gravimeter control system in the prior art provided by the embodiments of the present invention;

[0038] Figure 3 This is a schematic flowchart of an atomic gravimeter control method provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of an atomic gravimeter control system architecture provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of the port structure of an atomic gravimeter control system provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the hardware coding structure in an atomic gravimeter control system provided in an embodiment of the present invention;

[0042] Figure 7 This is a schematic flowchart of an atomic gravimeter control method provided in an embodiment of the present invention;

[0043] Figure 8 This is a schematic diagram of the query command protocol in an atomic gravimeter control method provided in an embodiment of the present invention;

[0044] Figure 9 This is a schematic diagram of the pinout of a multiplexer chip used in an atomic gravimeter control system provided in an embodiment of the present invention;

[0045] Figure 10 This is a schematic flowchart of an atomic gravimeter control method provided in an embodiment of the present invention;

[0046] Figure 11This is a schematic diagram of the pinout of another multiplexer chip used in an atomic gravimeter control system provided in an embodiment of the present invention;

[0047] Figure 12 This is a schematic diagram of an atomic gravimeter control method provided in an embodiment of the present invention.

[0048] Figure 13 This is a schematic diagram of the port structure of another atomic gravimeter control system provided in an embodiment of the present invention;

[0049] Figure 14 This is a schematic diagram of the pinout of a parallel data to serial data converter chip provided in an embodiment of the present invention;

[0050] Figure 15 This is a schematic diagram of the associated pins of a functional driver chip provided in an embodiment of the present invention.

Detailed Implementation Methods

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0052] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0053] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0054] Example 1:

[0055] Embodiment 1 of the present invention provides a method for controlling an atomic gravimeter, using an adapter board to integrate the main control board ports and various functional drive board ports involved in the atomic gravimeter control system. Figure 3 and Figure 4 As shown, the method includes:

[0056] In step 201, the adapter board is used to connect to the ports of various functional driver boards, and a hardware address encoder is set at the designated pin of the corresponding port.

[0057] The hardware address encoder consists of a preset number of pins, and a unique address code is assigned to each functional driver board by grounding a specified number of pins and / or connecting a specified number of pins to a high level.

[0058] In this embodiment of the invention, a hardware address encoder is provided at the designated pin. This can have multiple layers of meaning. For example, in a specific implementation, the corresponding associated pins on the port of the adapter board used to interface with the main control board may not require a hardware address encoder. In actual implementation, to save costs, it is also possible to set the hardware address encoder to empty for one of the function driver board ports. That is, the function driver board outputs a default address of all 0s or all 1s when it does not obtain the unique address code output by the hardware address encoder, thereby reducing the cost of the entire adapter board by one hardware address encoder (combined with the above-mentioned absence of a hardware address encoder on the corresponding port of the main control board, this will result in two ports on the adapter board without the hardware address encoder). However, as a universal and conventional solution, setting a hardware address encoder for each associated pin on each port of the adapter board maximizes the flexibility of the adapter board's configuration and release methods.

[0059] In step 202, the adapter board outputs a unique address code to each functional driver board through the hardware address encoder, so that when each functional driver board interacts with the main control board through the common data bus on the adapter board, the main control board can identify the corresponding data source.

[0060] Among them, the functional driver board includes but is not limited to Figure 4The following are shown: timing control board, storage board, sensor driver board, ion pump driver board, PZT (Piezoelectric ceramics) driver board, LC (Inductance coil) driver board, motor driver board, TA (Tapered amplifiers) driver board, EOM (Electro-Optic Modulator) driver board, AOM (Acoustic-optic modulator) driver board, laser driver board, temperature control board, 2D-MOT (Two-dimensional Magneto-optical trap) driver board, 3D-MOT (Three-dimensional Magneto-optical trap) driver board, PD (Photoelectric detection) signal detection board, etc.

[0061] The main control board and each functional circuit board communicate bidirectionally via a 485 bus or other buses (such as CAN bus). Based on functional requirements, the main control board sends instructions to the target function driver board via the communication bus. The target function driver board then controls the external hardware devices to perform the corresponding actions based on the received instructions.

[0062] This invention integrates the main control board and all functional driver boards onto a single adapter board, eliminating the need for any external interconnects for communication and power supply. This reduces the number of cables used in the system, facilitating system miniaturization and reducing system size and weight.

[0063] In the implementation of this invention, a purely hardware-based solution is also provided for forming unique address codes assigned to each functional driver board by grounding a specified number of pins and / or connecting a specified number of pins to a high level. (See reference...) Figure 5 and Figure 6 Specifically:

[0064] Grounding a pin represents a bit value of 0, and connecting a pin to a high level represents a bit value of 1. A predetermined number of pins are arranged in sequence, and a specified number of pins grounded and / or a specified number of pins connected to a high level constitute an ordered sequence of bits, thereby realizing the unique address encoding assigned to each functional driver board.

[0065] like Figure 5As shown in the diagram, J0 is a port specifically set up for the main control board, while the other ports J1-Jn are ports set up for the function driver boards. The differences between the ports will be further explained in the feature description later. All ports on the adapter board are equipped with address function pins GAn_0-GAn_4 (where n indicates the nth port of the adapter board used to connect to the nth function driver board, for example, pins GA0_0-GA0_4 for the main control board). These pins serve as address codes for the function driver boards installed at the current adapter board port, distinguishing function driver boards with different functions.

[0066] During normal operation, each functional driver board has a different address, and the address setting method is illustrated as follows: Figure 6 (This only schematically shows the combination of 6 male connector terminals) As shown: At least 5 resistors are installed on the adapter board. One end of each resistor is grounded (pull-down) or connected to power (pull-up), and the other end is connected to the control chip on the circuit board via a terminal. These resistors use different pull-up or pull-down combinations. The circuit board recognizes the resistor combination at each terminal, which serves as the circuit board's address code in the system. For example, the resistor combination at a certain set of 6 male connector terminals on the adapter board might be as follows: Figure 6 As shown, the circuit board address codes installed at these male terminals are 00000, 00001, 00010, 00011, 000100, and 000101, which are then converted to hexadecimal as 00, 01, 02, 03, 04, and 05, respectively.

[0067] Based on the examples above, it can be seen that the value of the preset number of pins used to determine the unique address code is set according to the total number of functional driver boards that the corresponding adapter board needs to support; wherein, to satisfy the condition that 2 is the base, the result of the preset number of pins as a power of the base must be greater than or equal to the total number of functional driver boards that the adapter board needs to support.

[0068] In conjunction with the embodiments of the present invention, when the method of Embodiment 1 is implemented in a specific application scenario, especially when the main control board and each functional driver board are connected to the adapter board, after power-on, as... Figure 7 As shown, the method also includes:

[0069] In step 301, each functional driver board identifies its unique address code on the current adapter board through the hardware address encoder at its respective port.

[0070] In step 302, the main control board sends at least three query commands to the function driver board at each address code in turn to confirm whether a function driver board is installed at the address code and the function of the function driver board, and saves the information obtained from the query.

[0071] like Figure 8As shown, this embodiment of the invention also provides a specific and feasible signaling rule method for the query instruction involved in steps 301-302 above. The instruction protocol used by the query instruction consists of 24 bytes. The first two bytes are combined to form instrument type data (e.g., high byte first, low byte last, 0001 represents atomic gravimeter).

[0072] The third byte is the address byte (i.e. Figure 8 The first byte (numbered 2) contains the following bytes: Byte 3: The first 6 bits represent the address of the target object, and the last two bits are check bits; Byte 4: The instruction type byte (including Byte 4 being 01 indicating the current instruction is a query function driver board function type instruction); Byte 8: The function type byte (representing the function type of the function driver board, such as 00 indicating timing control function, meaning the current function driver board is a timing control board). Byte 8 contains the first 6 bits representing the function type of the function driver board, and the last 2 bits are verification encryption data, calculated by summing the first 6 bits and retaining only the lowest two bits; Byte 24 is the verification encryption byte, obtained by summing the first 23 bytes and retaining only 8 bits; Bytes 9 to 22 are reserved bits.

[0073] Combination Figure 5 and Figure 9 For the implementation of the main control board's ability to identify whether a functional driver board is connected to a corresponding port on the adapter board, such as... Figure 10 As shown, the method also includes:

[0074] In step 401, the adapter board is also provided with a multiplexer, and the adapter board connects the VA input signal pin of the main control board to the common port of the multiplexer.

[0075] The multiplexer here is like Figure 9 As shown, the control signal pins of the multiplexer include pin A, pin B, pin C, pin D, pin INHIBIT, and pin COMMOM; the output signal (VA) can be connected to the main control board through the VA pin on the adapter board that serves the main control board port. The main control board controls whether the multiplexer works by controlling the INHIBIT signal, and selects to connect a specified input signal and output signal of the multiplexer by controlling pins A, B, C, and D.

[0076] During normal operation, the main control board first sets the control INHIBIT1 signal to a high level to start the chip. Then, it sets A, B, C, and D to different combinations of high and low levels, sequentially connecting the input signals (VA1-VA16) to the output signal (VA). The main control board determines whether a function driver board is installed at the male terminal corresponding to the current input signal by recognizing the level state of VA.

[0077] During normal operation, the main control board first sets the control INHIBIT1 signal to a high level (i.e., via...). Figure 5 (The output of pin f6 of port J0 is shown) to start the chip. Then set A, B, C, and D to different high and low level combinations, and connect the input signals (VA1-VA16) and output signals (VA) in sequence. The main control board determines whether a function driver board is installed at the male terminal corresponding to the current input signal by recognizing the level state of VA.

[0078] In step 402, each input of the multiplexer is connected to the VA output signal pin of the corresponding receiving function driver board in each port of the adapter board.

[0079] refer to Figure 5 Correspondingly, the output of the control port for the multiplexer is only provided in the J0 port used to connect to the main control board, while the corresponding pins (f2-f7) of the other ports are grounded by default. As an example, Figure 5 In this case, it directly includes pin f6, which can output the INHIBIT1 signal, and pin f7, which can output the INHIBIT2 signal. In other words, it is designed to be comparable to a driver board that can be expanded to implement 32 functions.

[0080] In step 403, each functional driver board sets the corresponding VA output signal pin of its own terminal directly to a low level. When a functional driver board is installed at the port of the adapter board, the corresponding input of the multiplexer is pulled low. Otherwise, the pin at the port of the adapter board remains at a high level.

[0081] In this way, the main control board can accurately determine which functional driver boards are currently installed in the system, facilitating the expansion and removal of driver boards as needed. When a driver board needs to be added or removed, only the new driver board needs to be installed or a driver board needs to be removed, eliminating the need for extensive additional maintenance and significantly reducing the workload. Simultaneously, the triple-check encryption method of the command protocol improves the reliability of data transmission and reduces the possibility of data transmission errors.

[0082] In embodiments of the present invention, for example Figure 9The presented multiplexer supports 16-channel selection. When the number of function driver boards to be configured on the adapter board is greater than 16, refer to... Figure 11 The methods also include:

[0083] Multiplexers are added to the single board. The multiplexer that serves the first 16 function driver boards is called the first multiplexer, while the multiplexer that serves the remaining function driver boards is called the second multiplexer.

[0084] At this time, the ports set on the adapter board for the main control board respectively set up INHIBIT1 control signal output pin for the INHIBIT pin of the first multiplexer; and set up INHIBIT2 control signal output pin for the INHIBIT pin of the second multiplexer. Among them, in the ports set up on the adapter board for the main control board, pins A, B, C and D of the first multiplexer and pins A, B, C and D of the second multiplexer share a set of pins A, B, C and D in one port.

[0085] Example 2:

[0086] The embodiments of the present invention are further improved design schemes based on Embodiment 1, and are made for the application scenarios proposed by the present invention. The embodiments of the present invention fully consider that when there are a large number of corresponding functional driver boards, a single misoperation will bring a lot of resource occupation and loss to the main control board, so as to identify that the corresponding functional driver board is of the wrong type.

[0087] refer to Figure 5 In the preferred embodiment of the present invention, the ports between the corresponding function driving board and the adapter board are standardized. This is to enable the flexibility of the adapter board used in the present invention. However, because of this, the misoperation mentioned at the beginning of this embodiment may occur.

[0088] Therefore, the embodiments of the present invention continue the practices described in Embodiment 1. Figure 6 The method of generating the unique hardware code shown has been extended and expanded, allowing the function driver board to perform calibration and correction itself in the event of erroneous operation. Furthermore, during this calibration and correction process, the corresponding function driver board will block its own pins to avoid unnecessary signaling resource consumption on the main control board. Figure 12 As shown, the method also includes:

[0089] In step 501, each functional driver board is also equipped with a second hardware address encoder and comparator component.

[0090] In step 502, when the corresponding function driver board is connected to the adapter board, if the level of the hardware address encoder on the corresponding adapter board port and the second hardware address encoder on the function driver board are inconsistent through the comparator component, the comparator component triggers the indicator light on the function driver board to flash.

[0091] In step 503, if the level in the hardware address encoder on the corresponding adapter board port and the second hardware address encoder on the function driver board are consistent through the comparator component, the data port connected to the adapter board of the function driver board enters the transmit / receive state.

[0092] Specifically, before the comparator component obtains the verification result, or when the obtained verification result is inconsistent with the evaluation, the data port connected to the corresponding function driver board and the adapter board remains blocked.

[0093] In the specific implementation of this invention in Embodiment 1, if the solution in Embodiment 1 has already adopted borrowed methods such as... Figure 9 The multiplexer shown in the invention uses the method of pulling the VA level low to let the main control board know that a new function driver board has been inserted into the corresponding port. In the corresponding condition of "before the verification result is obtained by the comparator component, or when the verification result is that the levels are inconsistent, the data port connected to the corresponding function driver board and the adapter board shall remain in a blocked state", an additional setting shall be added. That is, when the data port remains in a blocked state, the pin of the corresponding function driver board connected to f8 on the port shall maintain a high output level. However, once the verification is passed, it can be switched from high level to low level.

[0094] Example 3:

[0095] This embodiment employs a functional driver board hardware priority classification, a bus idle check mechanism, and a method for sending and responding to upload requests to further improve and demonstrate the feasibility of the technical solution in Embodiment 1 of the present invention.

[0096] Firstly, the hardware priority classification of the functional driver board:

[0097] Based on the type of functional driver board used, priority is set using preemption priority and response priority. The specific method is as follows: All functional driver boards are grouped into a few groups, with different priorities between each group; the priority between groups is called "preemption priority." Within each group, the priorities of the functional driver boards are different; these priorities are called "response priority."

[0098] Functional driver boards 1, 2, and 3 are primarily used to ensure the instrument operates in a suitable external and internal environment. Functional driver board 1 detects parameters such as air pressure and temperature in the instrument's environment; functional driver board 2 maintains the instrument's balance and stability based on its location; and functional driver board 3 ensures a suitable internal temperature. These three functional driver boards are assigned a maximum preemption priority of 0, with functional driver board 1 having the highest response priority (0), functional driver board 2 having the next highest priority (1), and functional driver board 3 having the lowest response priority (2).

[0099] Functional drive board 4 is used to maintain a suitable vacuum environment for measurement, while functional drive boards 5 and 6 are used for pre-cooling and further cooling of atoms, respectively. These three functional drive boards are assigned a secondary preemption priority of 1, with response priorities of 0, 1, and 2 from high to low.

[0100] Functional driver boards 7, 8, 9, 10, 11, and 12 are used together to control the generation of multiple laser signals and the setting of parameters such as intensity, frequency, and power, ensuring that the laser signals used meet the measurement requirements. These functional driver boards are assigned to a third-level preemption priority of 2, with response priorities from high to low being 0, 1, 2, 3, 4, and 5.

[0101] The functional driver board 13 is used to detect changes in the photoelectric sensor signal caused by interference with the light signal during the falling of atoms, thereby obtaining gravity parameters. Its preemption priority is the lowest, set to 3, and its response priority is 0.

[0102] In practice, the storage board and timing control board do not need to actively transmit messages to the main control board, and priority does not need to be assigned.

[0103] Secondly, the bus idle check mechanism:

[0104] Before each function driver board actively sends a message to the main control board, it must first check whether the bus is in a communication state. If the bus is in a communication state, the bus is in a "busy" state; otherwise, the bus is in an "idle" state. Only when the bus is in an idle state can the function driver board actively send a message to the bus.

[0105] like Figure 13 As shown (corresponding) Figure 13 Through the embodiment 1 of the present invention Figure 5(Based on the evolution of the corresponding circuit structure), the d7 pin of all ports on the adapter board (including port J0, port J1, port J2, ..., port Jn) is set to the IDLE signal, all connected together and pulled up by resistors. This pin is connected to the main control board and the main control chip of each function driver board through terminals. By default, this pin is pulled up high, indicating that the bus is in a "busy" state. The main control board can control the level of this pin to be high or low, while each function driver board can only read the level of this pin and cannot change the level of this pin. When the main control board is not performing any communication operations, it sets this pin to low, indicating that the current bus is in an "idle" state. When each function driver board detects that this pin is low, if it has a message to send to the main control board through the bus, it can send a request to the main control board. If the request is approved, the main control board will send a command message to the function driver board in response. After receiving the message, the function driver board can send the information to the main control board.

[0106] Thirdly, the sending and response of upload requests:

[0107] like Figure 13 As shown, the e5 pins of all male connectors on the adapter board are pulled up by resistors. These pins are connected to the main control board and the main control chips of each function driver board via terminals. This pin serves as the request signal for each function driver board. By default, this pin is pulled high, and no function driver board requests to actively upload messages. Each function driver board can control the level of this pin, but the main control board can only read the pin signal and cannot change its state. When a function driver board needs to transmit a message to the main control board, it sets this pin to low. Figure 14 As shown, these request signal pins are all connected to a parallel data to serial data converter chip. The input of this chip is the request signal, and the output signal is connected to the request signal BUSY on the main control board. The main control board reads a series of signal sequences on the BUSY pin and analyzes the sequences to determine which function drivers have initiated active upload requests.

[0108] like Figure 15 As shown, the request signal from the function driver board is also connected to two 8-input AND gate chips. The outputs of these two chips then pass through a 2-input AND gate chip, and the final output signal BUSY_IRQ is connected to the control chip on the main control board. The control chip on the main control board sets this pin signal to a falling edge trigger interrupt (a falling edge represents a change in the pin state from high to low). When one or more function driver boards submit an active upload request, BUSY_IRQ will go low, and a falling edge signal will be generated during this change. After detecting this signal, the control chip on the main control board immediately sets the bus to a "busy" state and starts from... Figure 14The system reads data from the parallel-to-serial data converter chip, analyzes which functional driver boards have submitted active upload requests, and determines which functional driver board to respond to first based on their preemption and response priorities. Building upon this bus preemption mechanism, to prevent the bus from being constantly occupied by a single functional driver board, the main control board sets the response communication time for each functional driver board within a certain time range. If the time limit is exceeded, the system automatically switches to responding to the next higher-priority functional driver board.

[0109] Example 4:

[0110] This invention also provides a system for controlling an atomic gravimeter, such as... Figure 4 As shown, it includes a main control board, an adapter board, and multiple functional driver boards. The main control board and multiple functional driver boards are respectively plugged into the corresponding ports of the adapter board and are used to implement the atomic gravimeter control method as described in Embodiments 1 and 2.

[0111] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0112] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0113] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for controlling an atomic gravimeter, characterized in that, Using an adapter board, the main control board ports and various functional driver board ports involved in the atomic gravimeter control system are all fabricated on the adapter board. The method includes: The adapter board is used to connect to the ports of various functional driver boards, and a hardware address encoder is set at a designated pin; wherein, the hardware address encoder is composed of a preset number of pins, and a unique address code is assigned to each functional driver board by grounding a specified number of pins and / or connecting a specified number of pins to a high level; The adapter board outputs a unique address code to each functional driver board through the hardware address encoder, so that when each functional driver board interacts with the main control board through the common data bus on the adapter board, the main control board can identify the corresponding data source. The method for the main control board to identify whether a corresponding port on the adapter board is connected to a functional driver board further includes: the adapter board is also equipped with a multiplexer, and the adapter board connects the VA input signal pin of the main control board to the common port of the multiplexer; each input of the multiplexer is connected to the corresponding VA output signal pin of each functional driver board in each port on the adapter board; wherein, each functional driver board directly sets the corresponding VA output signal pin of its own terminal to a low level, when a functional driver board is installed at the port of the adapter board, the corresponding input of the multiplexer is pulled low to a low level, otherwise, the pin at the port of the adapter board remains at a high level.

2. The method for controlling an atomic gravimeter according to claim 1, characterized in that, The process of forming a unique address code assigned to each functional driver board by grounding a specified number of pins and / or connecting a specified number of pins to a high level is as follows: Grounding a pin represents a bit value of 0, and connecting a pin to a high level represents a bit value of 1. A predetermined number of pins are arranged in sequence, and a specified number of pins grounded and / or a specified number of pins connected to a high level constitute an ordered sequence of bits, thereby realizing the unique address encoding assigned to each functional driver board.

3. The method for controlling an atomic gravimeter according to claim 2, characterized in that, The preset number of pins used to define the unique address code is set according to the total number of functional driver boards that the corresponding adapter board needs to support; wherein, the result of exponentiating the preset number of pins as the base 2 must be greater than or equal to the total number of functional driver boards that the adapter board needs to support.

4. The method for controlling an atomic gravimeter according to any one of claims 1-3, characterized in that, The main control board and all functional driver boards are connected to the adapter board. The method after power-on also includes: Each functional driver board identifies its unique address code on the current adapter board through the hardware address encoder at its respective port; The main control board sends at least three query commands to the function driver board at each address code in turn to confirm whether a function driver board is installed at that address code and the function of that function driver board, and saves the information obtained from the query.

5. The method for controlling an atomic gravimeter according to claim 4, characterized in that, The query command uses a 24-byte instruction protocol, with the first two bytes forming the instrument type data. The third byte is the address byte, where the first 6 bits of binary data represent the address of the target object, and the last two bits are check bits; the fourth byte is the instruction type byte; the eighth byte is the function type byte, where the first 6 bits of binary data represent the function type of the function driver board, and the last 2 bits are verification encryption data, which is calculated by summing the first 6 bits and keeping only the lowest two bits; the 24th byte is the verification encryption byte, which is obtained by summing the first 23 bytes and keeping only 8 bits; bytes 9 to 22 are reserved bits.

6. The method for controlling an atomic gravimeter according to claim 1, characterized in that, The control signal pins of the multiplexer include pin A, pin B, pin C, pin D, pin INHIBIT, and pin COMMOM. The output signal (VA) can be connected to the main control board through the VA pin on the adapter board that serves the main control board port. The main control board controls whether the multiplexer is working by controlling the INHIBIT signal, and selects to connect a specific input signal and output signal of the multiplexer by controlling pins A, B, C, and D.

7. The method for controlling an atomic gravimeter according to claim 6, characterized in that, The multiplexer supports 16-channel selection. When the number of function driver boards to be configured on the adapter board is greater than 16, the method further includes: Multiplexers are added to the single board. The multiplexer that serves the first 16 function driver boards is called the first multiplexer, while the multiplexer that serves the remaining function driver boards is called the second multiplexer. At this time, the ports set on the adapter board for the main control board respectively set up INHIBIT1 control signal output pin for the INHIBIT pin of the first multiplexer; and set up INHIBIT2 control signal output pin for the INHIBIT pin of the second multiplexer. Among them, in the ports set up on the adapter board for the main control board, pins A, B, C and D of the first multiplexer and pins A, B, C and D of the second multiplexer share a set of pins A, B, C and D in one port.

8. The method for controlling an atomic gravimeter according to claim 1, characterized in that, The method also includes: Each functional driver board is also equipped with a second hardware address encoder and comparator components; When the corresponding function driver board is connected to the adapter board, if the level in the hardware address encoder on the corresponding adapter board port and the second hardware address encoder on the function driver board are inconsistent through the comparator component, the comparator component will trigger the indicator light in the function driver board to flash. If the level in the hardware address encoder on the corresponding adapter board port and the second hardware address encoder on the function driver board are consistent through the comparator component, the data port connected to the adapter board of the function driver board enters the transmit / receive state. Specifically, before the comparator component obtains the verification result, or when the obtained verification result is inconsistent with the evaluation, the data port connected to the corresponding function driver board and the adapter board remains blocked.

9. A system for controlling an atomic gravimeter, characterized in that, It includes a main control board, an adapter board, and multiple functional driver boards, wherein the main control board and the multiple functional driver boards are respectively plugged into the corresponding ports of the adapter board and are used to implement the method of controlling the atomic gravimeter as described in any one of claims 1-8.

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